2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
46 * The chipsets all follow very much the same design. The original Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 * ICH7 errata #16 - MWDMA1 timings are incorrect
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
86 #include <linux/kernel.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/init.h>
90 #include <linux/blkdev.h>
91 #include <linux/delay.h>
92 #include <linux/device.h>
93 #include <linux/gfp.h>
94 #include <scsi/scsi_host.h>
95 #include <linux/libata.h>
96 #include <linux/dmi.h>
98 #define DRV_NAME "ata_piix"
99 #define DRV_VERSION "2.13"
102 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
103 ICH5_PMR = 0x90, /* port mapping register */
104 ICH5_PCS = 0x92, /* port control and status */
110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
116 PIIX_80C_PRI = (1 << 5) | (1 << 4),
117 PIIX_80C_SEC = (1 << 7) | (1 << 6),
119 /* constants for mapping table */
125 NA = -2, /* not avaliable */
126 RV = -3, /* reserved */
128 PIIX_AHCI_DEVICE = 6,
130 /* host->flags bits */
131 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
134 enum piix_controller_ids {
136 piix_pata_mwdma, /* PIIX3 MWDMA only */
137 piix_pata_33, /* PIIX4 at 33Mhz */
138 ich_pata_33, /* ICH up to UDMA 33 only */
139 ich_pata_66, /* ICH up to 66 Mhz */
140 ich_pata_100, /* ICH up to UDMA 100 */
141 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
147 ich8m_apple_sata, /* locks up on second port enable */
149 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
154 const u16 port_enable;
158 struct piix_host_priv {
161 spinlock_t sidpr_lock; /* FIXME: remove once locking in EH is fixed */
165 static int piix_init_one(struct pci_dev *pdev,
166 const struct pci_device_id *ent);
167 static void piix_remove_one(struct pci_dev *pdev);
168 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
169 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
170 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
171 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
172 static int ich_pata_cable_detect(struct ata_port *ap);
173 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
174 static int piix_sidpr_scr_read(struct ata_link *link,
175 unsigned int reg, u32 *val);
176 static int piix_sidpr_scr_write(struct ata_link *link,
177 unsigned int reg, u32 val);
178 static bool piix_irq_check(struct ata_port *ap);
180 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
181 static int piix_pci_device_resume(struct pci_dev *pdev);
184 static unsigned int in_module_init = 1;
186 static const struct pci_device_id piix_pci_tbl[] = {
187 /* Intel PIIX3 for the 430HX etc */
188 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
190 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
191 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
192 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
193 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
195 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
197 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
199 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
200 /* Intel ICH (i810, i815, i840) UDMA 66*/
201 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
202 /* Intel ICH0 : UDMA 33*/
203 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
205 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
206 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
207 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
209 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
210 /* Intel ICH3 (E7500/1) UDMA 100 */
211 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
212 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
213 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
214 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
216 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
218 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
219 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
220 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
221 /* ICH6 (and 6) (i915) UDMA 100 */
222 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
223 /* ICH7/7-R (i945, i975) UDMA 100*/
224 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
225 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
226 /* ICH8 Mobile PATA Controller */
227 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
232 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
234 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
235 /* 6300ESB (ICH5 variant with broken PCS present bits) */
236 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
237 /* 6300ESB pretending RAID */
238 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
239 /* 82801FB/FW (ICH6/ICH6W) */
240 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
241 /* 82801FR/FRW (ICH6R/ICH6RW) */
242 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
243 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
244 * Attach iff the controller is in IDE mode. */
245 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
246 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
247 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
248 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
249 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
250 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
251 /* Enterprise Southbridge 2 (631xESB/632xESB) */
252 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
253 /* SATA Controller 1 IDE (ICH8) */
254 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
255 /* SATA Controller 2 IDE (ICH8) */
256 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
257 /* Mobile SATA Controller IDE (ICH8M), Apple */
258 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
259 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
260 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
261 /* Mobile SATA Controller IDE (ICH8M) */
262 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
263 /* SATA Controller IDE (ICH9) */
264 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
265 /* SATA Controller IDE (ICH9) */
266 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
267 /* SATA Controller IDE (ICH9) */
268 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
269 /* SATA Controller IDE (ICH9M) */
270 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
271 /* SATA Controller IDE (ICH9M) */
272 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
273 /* SATA Controller IDE (ICH9M) */
274 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
275 /* SATA Controller IDE (Tolapai) */
276 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
277 /* SATA Controller IDE (ICH10) */
278 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
279 /* SATA Controller IDE (ICH10) */
280 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
281 /* SATA Controller IDE (ICH10) */
282 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
283 /* SATA Controller IDE (ICH10) */
284 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
285 /* SATA Controller IDE (PCH) */
286 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
287 /* SATA Controller IDE (PCH) */
288 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
289 /* SATA Controller IDE (PCH) */
290 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
291 /* SATA Controller IDE (PCH) */
292 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
293 /* SATA Controller IDE (PCH) */
294 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
295 /* SATA Controller IDE (PCH) */
296 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
297 /* SATA Controller IDE (CPT) */
298 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
299 /* SATA Controller IDE (CPT) */
300 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
301 /* SATA Controller IDE (CPT) */
302 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
303 /* SATA Controller IDE (CPT) */
304 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
305 /* SATA Controller IDE (PBG) */
306 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
307 /* SATA Controller IDE (PBG) */
308 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
309 { } /* terminate list */
312 static struct pci_driver piix_pci_driver = {
314 .id_table = piix_pci_tbl,
315 .probe = piix_init_one,
316 .remove = piix_remove_one,
318 .suspend = piix_pci_device_suspend,
319 .resume = piix_pci_device_resume,
323 static struct scsi_host_template piix_sht = {
324 ATA_BMDMA_SHT(DRV_NAME),
327 static struct ata_port_operations piix_sata_ops = {
328 .inherits = &ata_bmdma32_port_ops,
329 .sff_irq_check = piix_irq_check,
332 static struct ata_port_operations piix_pata_ops = {
333 .inherits = &piix_sata_ops,
334 .cable_detect = ata_cable_40wire,
335 .set_piomode = piix_set_piomode,
336 .set_dmamode = piix_set_dmamode,
337 .prereset = piix_pata_prereset,
340 static struct ata_port_operations piix_vmw_ops = {
341 .inherits = &piix_pata_ops,
342 .bmdma_status = piix_vmw_bmdma_status,
345 static struct ata_port_operations ich_pata_ops = {
346 .inherits = &piix_pata_ops,
347 .cable_detect = ich_pata_cable_detect,
348 .set_dmamode = ich_set_dmamode,
351 static struct ata_port_operations piix_sidpr_sata_ops = {
352 .inherits = &piix_sata_ops,
353 .hardreset = sata_std_hardreset,
354 .scr_read = piix_sidpr_scr_read,
355 .scr_write = piix_sidpr_scr_write,
358 static const struct piix_map_db ich5_map_db = {
362 /* PM PS SM SS MAP */
363 { P0, NA, P1, NA }, /* 000b */
364 { P1, NA, P0, NA }, /* 001b */
367 { P0, P1, IDE, IDE }, /* 100b */
368 { P1, P0, IDE, IDE }, /* 101b */
369 { IDE, IDE, P0, P1 }, /* 110b */
370 { IDE, IDE, P1, P0 }, /* 111b */
374 static const struct piix_map_db ich6_map_db = {
378 /* PM PS SM SS MAP */
379 { P0, P2, P1, P3 }, /* 00b */
380 { IDE, IDE, P1, P3 }, /* 01b */
381 { P0, P2, IDE, IDE }, /* 10b */
386 static const struct piix_map_db ich6m_map_db = {
390 /* Map 01b isn't specified in the doc but some notebooks use
391 * it anyway. MAP 01b have been spotted on both ICH6M and
395 /* PM PS SM SS MAP */
396 { P0, P2, NA, NA }, /* 00b */
397 { IDE, IDE, P1, P3 }, /* 01b */
398 { P0, P2, IDE, IDE }, /* 10b */
403 static const struct piix_map_db ich8_map_db = {
407 /* PM PS SM SS MAP */
408 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
410 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
415 static const struct piix_map_db ich8_2port_map_db = {
419 /* PM PS SM SS MAP */
420 { P0, NA, P1, NA }, /* 00b */
421 { RV, RV, RV, RV }, /* 01b */
422 { RV, RV, RV, RV }, /* 10b */
427 static const struct piix_map_db ich8m_apple_map_db = {
431 /* PM PS SM SS MAP */
432 { P0, NA, NA, NA }, /* 00b */
434 { P0, P2, IDE, IDE }, /* 10b */
439 static const struct piix_map_db tolapai_map_db = {
443 /* PM PS SM SS MAP */
444 { P0, NA, P1, NA }, /* 00b */
445 { RV, RV, RV, RV }, /* 01b */
446 { RV, RV, RV, RV }, /* 10b */
451 static const struct piix_map_db *piix_map_db_table[] = {
452 [ich5_sata] = &ich5_map_db,
453 [ich6_sata] = &ich6_map_db,
454 [ich6m_sata] = &ich6m_map_db,
455 [ich8_sata] = &ich8_map_db,
456 [ich8_2port_sata] = &ich8_2port_map_db,
457 [ich8m_apple_sata] = &ich8m_apple_map_db,
458 [tolapai_sata] = &tolapai_map_db,
461 static struct ata_port_info piix_port_info[] = {
462 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
464 .flags = PIIX_PATA_FLAGS,
465 .pio_mask = ATA_PIO4,
466 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
467 .port_ops = &piix_pata_ops,
470 [piix_pata_33] = /* PIIX4 at 33MHz */
472 .flags = PIIX_PATA_FLAGS,
473 .pio_mask = ATA_PIO4,
474 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
475 .udma_mask = ATA_UDMA2,
476 .port_ops = &piix_pata_ops,
479 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
481 .flags = PIIX_PATA_FLAGS,
482 .pio_mask = ATA_PIO4,
483 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
484 .udma_mask = ATA_UDMA2,
485 .port_ops = &ich_pata_ops,
488 [ich_pata_66] = /* ICH controllers up to 66MHz */
490 .flags = PIIX_PATA_FLAGS,
491 .pio_mask = ATA_PIO4,
492 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
493 .udma_mask = ATA_UDMA4,
494 .port_ops = &ich_pata_ops,
499 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
500 .pio_mask = ATA_PIO4,
501 .mwdma_mask = ATA_MWDMA12_ONLY,
502 .udma_mask = ATA_UDMA5,
503 .port_ops = &ich_pata_ops,
506 [ich_pata_100_nomwdma1] =
508 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
509 .pio_mask = ATA_PIO4,
510 .mwdma_mask = ATA_MWDMA2_ONLY,
511 .udma_mask = ATA_UDMA5,
512 .port_ops = &ich_pata_ops,
517 .flags = PIIX_SATA_FLAGS,
518 .pio_mask = ATA_PIO4,
519 .mwdma_mask = ATA_MWDMA2,
520 .udma_mask = ATA_UDMA6,
521 .port_ops = &piix_sata_ops,
526 .flags = PIIX_SATA_FLAGS,
527 .pio_mask = ATA_PIO4,
528 .mwdma_mask = ATA_MWDMA2,
529 .udma_mask = ATA_UDMA6,
530 .port_ops = &piix_sata_ops,
535 .flags = PIIX_SATA_FLAGS,
536 .pio_mask = ATA_PIO4,
537 .mwdma_mask = ATA_MWDMA2,
538 .udma_mask = ATA_UDMA6,
539 .port_ops = &piix_sata_ops,
544 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
545 .pio_mask = ATA_PIO4,
546 .mwdma_mask = ATA_MWDMA2,
547 .udma_mask = ATA_UDMA6,
548 .port_ops = &piix_sata_ops,
553 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
554 .pio_mask = ATA_PIO4,
555 .mwdma_mask = ATA_MWDMA2,
556 .udma_mask = ATA_UDMA6,
557 .port_ops = &piix_sata_ops,
562 .flags = PIIX_SATA_FLAGS,
563 .pio_mask = ATA_PIO4,
564 .mwdma_mask = ATA_MWDMA2,
565 .udma_mask = ATA_UDMA6,
566 .port_ops = &piix_sata_ops,
571 .flags = PIIX_SATA_FLAGS,
572 .pio_mask = ATA_PIO4,
573 .mwdma_mask = ATA_MWDMA2,
574 .udma_mask = ATA_UDMA6,
575 .port_ops = &piix_sata_ops,
580 .flags = PIIX_PATA_FLAGS,
581 .pio_mask = ATA_PIO4,
582 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
583 .udma_mask = ATA_UDMA2,
584 .port_ops = &piix_vmw_ops,
589 static struct pci_bits piix_enable_bits[] = {
590 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
591 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
594 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
595 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
596 MODULE_LICENSE("GPL");
597 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
598 MODULE_VERSION(DRV_VERSION);
607 * List of laptops that use short cables rather than 80 wire
610 static const struct ich_laptop ich_laptop[] = {
611 /* devid, subvendor, subdev */
612 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
613 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
614 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
615 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
616 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
617 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
618 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */
619 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
620 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
621 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
622 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
623 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
624 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
625 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
631 * ich_pata_cable_detect - Probe host controller cable detect info
632 * @ap: Port for which cable detect info is desired
634 * Read 80c cable indicator from ATA PCI device's PCI config
635 * register. This register is normally set by firmware (BIOS).
638 * None (inherited from caller).
641 static int ich_pata_cable_detect(struct ata_port *ap)
643 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
644 struct piix_host_priv *hpriv = ap->host->private_data;
645 const struct ich_laptop *lap = &ich_laptop[0];
648 /* Check for specials - Acer Aspire 5602WLMi */
649 while (lap->device) {
650 if (lap->device == pdev->device &&
651 lap->subvendor == pdev->subsystem_vendor &&
652 lap->subdevice == pdev->subsystem_device)
653 return ATA_CBL_PATA40_SHORT;
658 /* check BIOS cable detect results */
659 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
660 if ((hpriv->saved_iocfg & mask) == 0)
661 return ATA_CBL_PATA40;
662 return ATA_CBL_PATA80;
666 * piix_pata_prereset - prereset for PATA host controller
668 * @deadline: deadline jiffies for the operation
671 * None (inherited from caller).
673 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
675 struct ata_port *ap = link->ap;
676 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
678 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
680 return ata_sff_prereset(link, deadline);
683 static DEFINE_SPINLOCK(piix_lock);
686 * piix_set_piomode - Initialize host controller PATA PIO timings
687 * @ap: Port whose timings we are configuring
690 * Set PIO mode for device, in host controller PCI config space.
693 * None (inherited from caller).
696 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
698 struct pci_dev *dev = to_pci_dev(ap->host->dev);
700 unsigned int pio = adev->pio_mode - XFER_PIO_0;
701 unsigned int is_slave = (adev->devno != 0);
702 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
703 unsigned int slave_port = 0x44;
710 * See Intel Document 298600-004 for the timing programing rules
711 * for ICH controllers.
714 static const /* ISP RTC */
715 u8 timings[][2] = { { 0, 0 },
722 control |= 1; /* TIME1 enable */
723 if (ata_pio_need_iordy(adev))
724 control |= 2; /* IE enable */
726 /* Intel specifies that the PPE functionality is for disk only */
727 if (adev->class == ATA_DEV_ATA)
728 control |= 4; /* PPE enable */
730 spin_lock_irqsave(&piix_lock, flags);
732 /* PIO configuration clears DTE unconditionally. It will be
733 * programmed in set_dmamode which is guaranteed to be called
734 * after set_piomode if any DMA mode is available.
736 pci_read_config_word(dev, master_port, &master_data);
738 /* clear TIME1|IE1|PPE1|DTE1 */
739 master_data &= 0xff0f;
740 /* Enable SITRE (separate slave timing register) */
741 master_data |= 0x4000;
742 /* enable PPE1, IE1 and TIME1 as needed */
743 master_data |= (control << 4);
744 pci_read_config_byte(dev, slave_port, &slave_data);
745 slave_data &= (ap->port_no ? 0x0f : 0xf0);
746 /* Load the timing nibble for this slave */
747 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
748 << (ap->port_no ? 4 : 0);
750 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
751 master_data &= 0xccf0;
752 /* Enable PPE, IE and TIME as appropriate */
753 master_data |= control;
754 /* load ISP and RCT */
756 (timings[pio][0] << 12) |
757 (timings[pio][1] << 8);
759 pci_write_config_word(dev, master_port, master_data);
761 pci_write_config_byte(dev, slave_port, slave_data);
763 /* Ensure the UDMA bit is off - it will be turned back on if
767 pci_read_config_byte(dev, 0x48, &udma_enable);
768 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
769 pci_write_config_byte(dev, 0x48, udma_enable);
772 spin_unlock_irqrestore(&piix_lock, flags);
776 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
777 * @ap: Port whose timings we are configuring
778 * @adev: Drive in question
779 * @isich: set if the chip is an ICH device
781 * Set UDMA mode for device, in host controller PCI config space.
784 * None (inherited from caller).
787 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
789 struct pci_dev *dev = to_pci_dev(ap->host->dev);
791 u8 master_port = ap->port_no ? 0x42 : 0x40;
793 u8 speed = adev->dma_mode;
794 int devid = adev->devno + 2 * ap->port_no;
797 static const /* ISP RTC */
798 u8 timings[][2] = { { 0, 0 },
804 spin_lock_irqsave(&piix_lock, flags);
806 pci_read_config_word(dev, master_port, &master_data);
808 pci_read_config_byte(dev, 0x48, &udma_enable);
810 if (speed >= XFER_UDMA_0) {
811 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
814 int u_clock, u_speed;
817 * UDMA is handled by a combination of clock switching and
818 * selection of dividers
820 * Handy rule: Odd modes are UDMATIMx 01, even are 02
821 * except UDMA0 which is 00
823 u_speed = min(2 - (udma & 1), udma);
825 u_clock = 0x1000; /* 100Mhz */
827 u_clock = 1; /* 66Mhz */
829 u_clock = 0; /* 33Mhz */
831 udma_enable |= (1 << devid);
833 /* Load the CT/RP selection */
834 pci_read_config_word(dev, 0x4A, &udma_timing);
835 udma_timing &= ~(3 << (4 * devid));
836 udma_timing |= u_speed << (4 * devid);
837 pci_write_config_word(dev, 0x4A, udma_timing);
840 /* Select a 33/66/100Mhz clock */
841 pci_read_config_word(dev, 0x54, &ideconf);
842 ideconf &= ~(0x1001 << devid);
843 ideconf |= u_clock << devid;
844 /* For ICH or later we should set bit 10 for better
845 performance (WR_PingPong_En) */
846 pci_write_config_word(dev, 0x54, ideconf);
850 * MWDMA is driven by the PIO timings. We must also enable
851 * IORDY unconditionally along with TIME1. PPE has already
852 * been set when the PIO timing was set.
854 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
855 unsigned int control;
857 const unsigned int needed_pio[3] = {
858 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
860 int pio = needed_pio[mwdma] - XFER_PIO_0;
862 control = 3; /* IORDY|TIME1 */
864 /* If the drive MWDMA is faster than it can do PIO then
865 we must force PIO into PIO0 */
867 if (adev->pio_mode < needed_pio[mwdma])
868 /* Enable DMA timing only */
869 control |= 8; /* PIO cycles in PIO0 */
871 if (adev->devno) { /* Slave */
872 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
873 master_data |= control << 4;
874 pci_read_config_byte(dev, 0x44, &slave_data);
875 slave_data &= (ap->port_no ? 0x0f : 0xf0);
876 /* Load the matching timing */
877 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
878 pci_write_config_byte(dev, 0x44, slave_data);
879 } else { /* Master */
880 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
881 and master timing bits */
882 master_data |= control;
884 (timings[pio][0] << 12) |
885 (timings[pio][1] << 8);
889 udma_enable &= ~(1 << devid);
891 pci_write_config_word(dev, master_port, master_data);
893 /* Don't scribble on 0x48 if the controller does not support UDMA */
895 pci_write_config_byte(dev, 0x48, udma_enable);
897 spin_unlock_irqrestore(&piix_lock, flags);
901 * piix_set_dmamode - Initialize host controller PATA DMA timings
902 * @ap: Port whose timings we are configuring
905 * Set MW/UDMA mode for device, in host controller PCI config space.
908 * None (inherited from caller).
911 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
913 do_pata_set_dmamode(ap, adev, 0);
917 * ich_set_dmamode - Initialize host controller PATA DMA timings
918 * @ap: Port whose timings we are configuring
921 * Set MW/UDMA mode for device, in host controller PCI config space.
924 * None (inherited from caller).
927 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
929 do_pata_set_dmamode(ap, adev, 1);
933 * Serial ATA Index/Data Pair Superset Registers access
935 * Beginning from ICH8, there's a sane way to access SCRs using index
936 * and data register pair located at BAR5 which means that we have
937 * separate SCRs for master and slave. This is handled using libata
938 * slave_link facility.
940 static const int piix_sidx_map[] = {
946 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
948 struct ata_port *ap = link->ap;
949 struct piix_host_priv *hpriv = ap->host->private_data;
951 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
952 hpriv->sidpr + PIIX_SIDPR_IDX);
955 static int piix_sidpr_scr_read(struct ata_link *link,
956 unsigned int reg, u32 *val)
958 struct piix_host_priv *hpriv = link->ap->host->private_data;
961 if (reg >= ARRAY_SIZE(piix_sidx_map))
964 spin_lock_irqsave(&hpriv->sidpr_lock, flags);
965 piix_sidpr_sel(link, reg);
966 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
967 spin_unlock_irqrestore(&hpriv->sidpr_lock, flags);
971 static int piix_sidpr_scr_write(struct ata_link *link,
972 unsigned int reg, u32 val)
974 struct piix_host_priv *hpriv = link->ap->host->private_data;
977 if (reg >= ARRAY_SIZE(piix_sidx_map))
980 spin_lock_irqsave(&hpriv->sidpr_lock, flags);
981 piix_sidpr_sel(link, reg);
982 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
983 spin_unlock_irqrestore(&hpriv->sidpr_lock, flags);
987 static bool piix_irq_check(struct ata_port *ap)
989 if (unlikely(!ap->ioaddr.bmdma_addr))
992 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
996 static int piix_broken_suspend(void)
998 static const struct dmi_system_id sysids[] = {
1000 .ident = "TECRA M3",
1002 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1003 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1007 .ident = "TECRA M3",
1009 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1010 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1014 .ident = "TECRA M4",
1016 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1017 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1021 .ident = "TECRA M4",
1023 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1024 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
1028 .ident = "TECRA M5",
1030 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1031 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1035 .ident = "TECRA M6",
1037 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1038 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1042 .ident = "TECRA M7",
1044 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1045 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1049 .ident = "TECRA A8",
1051 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1052 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1056 .ident = "Satellite R20",
1058 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1059 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1063 .ident = "Satellite R25",
1065 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1066 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1070 .ident = "Satellite U200",
1072 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1073 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1077 .ident = "Satellite U200",
1079 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1080 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1084 .ident = "Satellite Pro U200",
1086 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1087 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1091 .ident = "Satellite U205",
1093 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1094 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1098 .ident = "SATELLITE U205",
1100 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1101 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1105 .ident = "Portege M500",
1107 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1108 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1112 .ident = "VGN-BX297XP",
1114 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
1115 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
1119 { } /* terminate list */
1121 static const char *oemstrs[] = {
1126 if (dmi_check_system(sysids))
1129 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1130 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1133 /* TECRA M4 sometimes forgets its identify and reports bogus
1134 * DMI information. As the bogus information is a bit
1135 * generic, match as many entries as possible. This manual
1136 * matching is necessary because dmi_system_id.matches is
1137 * limited to four entries.
1139 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
1140 dmi_match(DMI_PRODUCT_NAME, "000000") &&
1141 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
1142 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
1143 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
1144 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
1145 dmi_match(DMI_BOARD_VERSION, "Version A0"))
1151 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1153 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1154 unsigned long flags;
1157 rc = ata_host_suspend(host, mesg);
1161 /* Some braindamaged ACPI suspend implementations expect the
1162 * controller to be awake on entry; otherwise, it burns cpu
1163 * cycles and power trying to do something to the sleeping
1166 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1167 pci_save_state(pdev);
1169 /* mark its power state as "unknown", since we don't
1170 * know if e.g. the BIOS will change its device state
1173 if (pdev->current_state == PCI_D0)
1174 pdev->current_state = PCI_UNKNOWN;
1176 /* tell resume that it's waking up from broken suspend */
1177 spin_lock_irqsave(&host->lock, flags);
1178 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1179 spin_unlock_irqrestore(&host->lock, flags);
1181 ata_pci_device_do_suspend(pdev, mesg);
1186 static int piix_pci_device_resume(struct pci_dev *pdev)
1188 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1189 unsigned long flags;
1192 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1193 spin_lock_irqsave(&host->lock, flags);
1194 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1195 spin_unlock_irqrestore(&host->lock, flags);
1197 pci_set_power_state(pdev, PCI_D0);
1198 pci_restore_state(pdev);
1200 /* PCI device wasn't disabled during suspend. Use
1201 * pci_reenable_device() to avoid affecting the enable
1204 rc = pci_reenable_device(pdev);
1206 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1207 "device after resume (%d)\n", rc);
1209 rc = ata_pci_device_do_resume(pdev);
1212 ata_host_resume(host);
1218 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1220 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1223 #define AHCI_PCI_BAR 5
1224 #define AHCI_GLOBAL_CTL 0x04
1225 #define AHCI_ENABLE (1 << 31)
1226 static int piix_disable_ahci(struct pci_dev *pdev)
1232 /* BUG: pci_enable_device has not yet been called. This
1233 * works because this device is usually set up by BIOS.
1236 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1237 !pci_resource_len(pdev, AHCI_PCI_BAR))
1240 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1244 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1245 if (tmp & AHCI_ENABLE) {
1246 tmp &= ~AHCI_ENABLE;
1247 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1249 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1250 if (tmp & AHCI_ENABLE)
1254 pci_iounmap(pdev, mmio);
1259 * piix_check_450nx_errata - Check for problem 450NX setup
1260 * @ata_dev: the PCI device to check
1262 * Check for the present of 450NX errata #19 and errata #25. If
1263 * they are found return an error code so we can turn off DMA
1266 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1268 struct pci_dev *pdev = NULL;
1270 int no_piix_dma = 0;
1272 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1273 /* Look for 450NX PXB. Check for problem configurations
1274 A PCI quirk checks bit 6 already */
1275 pci_read_config_word(pdev, 0x41, &cfg);
1276 /* Only on the original revision: IDE DMA can hang */
1277 if (pdev->revision == 0x00)
1279 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1280 else if (cfg & (1<<14) && pdev->revision < 5)
1284 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1285 if (no_piix_dma == 2)
1286 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1290 static void __devinit piix_init_pcs(struct ata_host *host,
1291 const struct piix_map_db *map_db)
1293 struct pci_dev *pdev = to_pci_dev(host->dev);
1296 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1298 new_pcs = pcs | map_db->port_enable;
1300 if (new_pcs != pcs) {
1301 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1302 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1307 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1308 struct ata_port_info *pinfo,
1309 const struct piix_map_db *map_db)
1312 int i, invalid_map = 0;
1315 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1317 map = map_db->map[map_value & map_db->mask];
1319 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1320 for (i = 0; i < 4; i++) {
1332 WARN_ON((i & 1) || map[i + 1] != IDE);
1333 pinfo[i / 2] = piix_port_info[ich_pata_100];
1339 printk(" P%d", map[i]);
1341 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1348 dev_printk(KERN_ERR, &pdev->dev,
1349 "invalid MAP value %u\n", map_value);
1354 static bool piix_no_sidpr(struct ata_host *host)
1356 struct pci_dev *pdev = to_pci_dev(host->dev);
1359 * Samsung DB-P70 only has three ATA ports exposed and
1360 * curiously the unconnected first port reports link online
1361 * while not responding to SRST protocol causing excessive
1364 * Unfortunately, the system doesn't carry enough DMI
1365 * information to identify the machine but does have subsystem
1366 * vendor and device set. As it's unclear whether the
1367 * subsystem vendor/device is used only for this specific
1368 * board, the port can't be disabled solely with the
1369 * information; however, turning off SIDPR access works around
1370 * the problem. Turn it off.
1372 * This problem is reported in bnc#441240.
1374 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1376 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1377 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1378 pdev->subsystem_device == 0xb049) {
1379 dev_printk(KERN_WARNING, host->dev,
1380 "Samsung DB-P70 detected, disabling SIDPR\n");
1387 static int __devinit piix_init_sidpr(struct ata_host *host)
1389 struct pci_dev *pdev = to_pci_dev(host->dev);
1390 struct piix_host_priv *hpriv = host->private_data;
1391 struct ata_link *link0 = &host->ports[0]->link;
1395 /* check for availability */
1396 for (i = 0; i < 4; i++)
1397 if (hpriv->map[i] == IDE)
1400 /* is it blacklisted? */
1401 if (piix_no_sidpr(host))
1404 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1407 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1408 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1411 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1414 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1416 /* SCR access via SIDPR doesn't work on some configurations.
1417 * Give it a test drive by inhibiting power save modes which
1420 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1422 /* if IPM is already 3, SCR access is probably working. Don't
1423 * un-inhibit power save modes as BIOS might have inhibited
1424 * them for a reason.
1426 if ((scontrol & 0xf00) != 0x300) {
1428 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1429 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1431 if ((scontrol & 0xf00) != 0x300) {
1432 dev_printk(KERN_INFO, host->dev, "SCR access via "
1433 "SIDPR is available but doesn't work\n");
1438 /* okay, SCRs available, set ops and ask libata for slave_link */
1439 for (i = 0; i < 2; i++) {
1440 struct ata_port *ap = host->ports[i];
1442 ap->ops = &piix_sidpr_sata_ops;
1444 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1445 rc = ata_slave_link_init(ap);
1454 static void piix_iocfg_bit18_quirk(struct ata_host *host)
1456 static const struct dmi_system_id sysids[] = {
1458 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1459 * isn't used to boot the system which
1460 * disables the channel.
1464 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1465 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1469 { } /* terminate list */
1471 struct pci_dev *pdev = to_pci_dev(host->dev);
1472 struct piix_host_priv *hpriv = host->private_data;
1474 if (!dmi_check_system(sysids))
1477 /* The datasheet says that bit 18 is NOOP but certain systems
1478 * seem to use it to disable a channel. Clear the bit on the
1481 if (hpriv->saved_iocfg & (1 << 18)) {
1482 dev_printk(KERN_INFO, &pdev->dev,
1483 "applying IOCFG bit18 quirk\n");
1484 pci_write_config_dword(pdev, PIIX_IOCFG,
1485 hpriv->saved_iocfg & ~(1 << 18));
1489 static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1491 static const struct dmi_system_id broken_systems[] = {
1493 .ident = "HP Compaq 2510p",
1495 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1496 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1498 /* PCI slot number of the controller */
1499 .driver_data = (void *)0x1FUL,
1502 .ident = "HP Compaq nc6000",
1504 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1505 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1507 /* PCI slot number of the controller */
1508 .driver_data = (void *)0x1FUL,
1511 { } /* terminate list */
1513 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1516 unsigned long slot = (unsigned long)dmi->driver_data;
1517 /* apply the quirk only to on-board controllers */
1518 return slot == PCI_SLOT(pdev->devfn);
1525 * piix_init_one - Register PIIX ATA PCI device with kernel services
1526 * @pdev: PCI device to register
1527 * @ent: Entry in piix_pci_tbl matching with @pdev
1529 * Called from kernel PCI layer. We probe for combined mode (sigh),
1530 * and then hand over control to libata, for it to do the rest.
1533 * Inherited from PCI layer (may sleep).
1536 * Zero on success, or -ERRNO value.
1539 static int __devinit piix_init_one(struct pci_dev *pdev,
1540 const struct pci_device_id *ent)
1542 static int printed_version;
1543 struct device *dev = &pdev->dev;
1544 struct ata_port_info port_info[2];
1545 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1546 unsigned long port_flags;
1547 struct ata_host *host;
1548 struct piix_host_priv *hpriv;
1551 if (!printed_version++)
1552 dev_printk(KERN_DEBUG, &pdev->dev,
1553 "version " DRV_VERSION "\n");
1555 /* no hotplugging support for later devices (FIXME) */
1556 if (!in_module_init && ent->driver_data >= ich5_sata)
1559 if (piix_broken_system_poweroff(pdev)) {
1560 piix_port_info[ent->driver_data].flags |=
1561 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1562 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1563 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1564 "on poweroff and hibernation\n");
1567 port_info[0] = piix_port_info[ent->driver_data];
1568 port_info[1] = piix_port_info[ent->driver_data];
1570 port_flags = port_info[0].flags;
1572 /* enable device and prepare host */
1573 rc = pcim_enable_device(pdev);
1577 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1580 spin_lock_init(&hpriv->sidpr_lock);
1582 /* Save IOCFG, this will be used for cable detection, quirk
1583 * detection and restoration on detach. This is necessary
1584 * because some ACPI implementations mess up cable related
1585 * bits on _STM. Reported on kernel bz#11879.
1587 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1589 /* ICH6R may be driven by either ata_piix or ahci driver
1590 * regardless of BIOS configuration. Make sure AHCI mode is
1593 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1594 rc = piix_disable_ahci(pdev);
1599 /* SATA map init can change port_info, do it before prepping host */
1600 if (port_flags & ATA_FLAG_SATA)
1601 hpriv->map = piix_init_sata_map(pdev, port_info,
1602 piix_map_db_table[ent->driver_data]);
1604 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1607 host->private_data = hpriv;
1609 /* initialize controller */
1610 if (port_flags & ATA_FLAG_SATA) {
1611 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1612 rc = piix_init_sidpr(host);
1617 /* apply IOCFG bit18 quirk */
1618 piix_iocfg_bit18_quirk(host);
1620 /* On ICH5, some BIOSen disable the interrupt using the
1621 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1622 * On ICH6, this bit has the same effect, but only when
1623 * MSI is disabled (and it is disabled, as we don't use
1624 * message-signalled interrupts currently).
1626 if (port_flags & PIIX_FLAG_CHECKINTR)
1629 if (piix_check_450nx_errata(pdev)) {
1630 /* This writes into the master table but it does not
1631 really matter for this errata as we will apply it to
1632 all the PIIX devices on the board */
1633 host->ports[0]->mwdma_mask = 0;
1634 host->ports[0]->udma_mask = 0;
1635 host->ports[1]->mwdma_mask = 0;
1636 host->ports[1]->udma_mask = 0;
1638 host->flags |= ATA_HOST_PARALLEL_SCAN;
1640 pci_set_master(pdev);
1641 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, &piix_sht);
1644 static void piix_remove_one(struct pci_dev *pdev)
1646 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1647 struct piix_host_priv *hpriv = host->private_data;
1649 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1651 ata_pci_remove_one(pdev);
1654 static int __init piix_init(void)
1658 DPRINTK("pci_register_driver\n");
1659 rc = pci_register_driver(&piix_pci_driver);
1669 static void __exit piix_exit(void)
1671 pci_unregister_driver(&piix_pci_driver);
1674 module_init(piix_init);
1675 module_exit(piix_exit);