2 * libahci.c - Common AHCI SATA low-level routines
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include <linux/pci.h>
50 static int ahci_skip_host_reset;
52 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
54 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
55 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
57 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
58 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
60 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
62 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
63 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
65 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
70 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
71 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
72 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
73 static int ahci_port_start(struct ata_port *ap);
74 static void ahci_port_stop(struct ata_port *ap);
75 static void ahci_qc_prep(struct ata_queued_cmd *qc);
76 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
77 static void ahci_freeze(struct ata_port *ap);
78 static void ahci_thaw(struct ata_port *ap);
79 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
80 static void ahci_enable_fbs(struct ata_port *ap);
81 static void ahci_disable_fbs(struct ata_port *ap);
82 static void ahci_pmp_attach(struct ata_port *ap);
83 static void ahci_pmp_detach(struct ata_port *ap);
84 static int ahci_softreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static void ahci_postreset(struct ata_link *link, unsigned int *class);
91 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
92 static void ahci_dev_config(struct ata_device *dev);
94 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
96 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
97 static ssize_t ahci_activity_store(struct ata_device *dev,
98 enum sw_activity val);
99 static void ahci_init_sw_activity(struct ata_link *link);
101 static ssize_t ahci_show_host_caps(struct device *dev,
102 struct device_attribute *attr, char *buf);
103 static ssize_t ahci_show_host_cap2(struct device *dev,
104 struct device_attribute *attr, char *buf);
105 static ssize_t ahci_show_host_version(struct device *dev,
106 struct device_attribute *attr, char *buf);
107 static ssize_t ahci_show_port_cmd(struct device *dev,
108 struct device_attribute *attr, char *buf);
109 static ssize_t ahci_read_em_buffer(struct device *dev,
110 struct device_attribute *attr, char *buf);
111 static ssize_t ahci_store_em_buffer(struct device *dev,
112 struct device_attribute *attr,
113 const char *buf, size_t size);
114 static ssize_t ahci_show_em_supported(struct device *dev,
115 struct device_attribute *attr, char *buf);
116 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
118 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
119 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
120 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
121 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
122 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
123 ahci_read_em_buffer, ahci_store_em_buffer);
124 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
126 struct device_attribute *ahci_shost_attrs[] = {
127 &dev_attr_link_power_management_policy,
128 &dev_attr_em_message_type,
129 &dev_attr_em_message,
130 &dev_attr_ahci_host_caps,
131 &dev_attr_ahci_host_cap2,
132 &dev_attr_ahci_host_version,
133 &dev_attr_ahci_port_cmd,
135 &dev_attr_em_message_supported,
138 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
140 struct device_attribute *ahci_sdev_attrs[] = {
141 &dev_attr_sw_activity,
142 &dev_attr_unload_heads,
145 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
147 struct ata_port_operations ahci_ops = {
148 .inherits = &sata_pmp_port_ops,
150 .qc_defer = ahci_pmp_qc_defer,
151 .qc_prep = ahci_qc_prep,
152 .qc_issue = ahci_qc_issue,
153 .qc_fill_rtf = ahci_qc_fill_rtf,
155 .freeze = ahci_freeze,
157 .softreset = ahci_softreset,
158 .hardreset = ahci_hardreset,
159 .postreset = ahci_postreset,
160 .pmp_softreset = ahci_softreset,
161 .error_handler = ahci_error_handler,
162 .post_internal_cmd = ahci_post_internal_cmd,
163 .dev_config = ahci_dev_config,
165 .scr_read = ahci_scr_read,
166 .scr_write = ahci_scr_write,
167 .pmp_attach = ahci_pmp_attach,
168 .pmp_detach = ahci_pmp_detach,
170 .set_lpm = ahci_set_lpm,
171 .em_show = ahci_led_show,
172 .em_store = ahci_led_store,
173 .sw_activity_show = ahci_activity_show,
174 .sw_activity_store = ahci_activity_store,
175 .transmit_led_message = ahci_transmit_led_message,
177 .port_suspend = ahci_port_suspend,
178 .port_resume = ahci_port_resume,
180 .port_start = ahci_port_start,
181 .port_stop = ahci_port_stop,
183 EXPORT_SYMBOL_GPL(ahci_ops);
185 struct ata_port_operations ahci_pmp_retry_srst_ops = {
186 .inherits = &ahci_ops,
187 .softreset = ahci_pmp_retry_softreset,
189 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
191 static bool ahci_em_messages __read_mostly = true;
192 EXPORT_SYMBOL_GPL(ahci_em_messages);
193 module_param(ahci_em_messages, bool, 0444);
194 /* add other LED protocol types when they become supported */
195 MODULE_PARM_DESC(ahci_em_messages,
196 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
198 /* device sleep idle timeout in ms */
199 static int devslp_idle_timeout __read_mostly = 1000;
200 module_param(devslp_idle_timeout, int, 0644);
201 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
203 static void ahci_enable_ahci(void __iomem *mmio)
208 /* turn on AHCI_EN */
209 tmp = readl(mmio + HOST_CTL);
210 if (tmp & HOST_AHCI_EN)
213 /* Some controllers need AHCI_EN to be written multiple times.
214 * Try a few times before giving up.
216 for (i = 0; i < 5; i++) {
218 writel(tmp, mmio + HOST_CTL);
219 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
220 if (tmp & HOST_AHCI_EN)
228 static ssize_t ahci_show_host_caps(struct device *dev,
229 struct device_attribute *attr, char *buf)
231 struct Scsi_Host *shost = class_to_shost(dev);
232 struct ata_port *ap = ata_shost_to_port(shost);
233 struct ahci_host_priv *hpriv = ap->host->private_data;
235 return sprintf(buf, "%x\n", hpriv->cap);
238 static ssize_t ahci_show_host_cap2(struct device *dev,
239 struct device_attribute *attr, char *buf)
241 struct Scsi_Host *shost = class_to_shost(dev);
242 struct ata_port *ap = ata_shost_to_port(shost);
243 struct ahci_host_priv *hpriv = ap->host->private_data;
245 return sprintf(buf, "%x\n", hpriv->cap2);
248 static ssize_t ahci_show_host_version(struct device *dev,
249 struct device_attribute *attr, char *buf)
251 struct Scsi_Host *shost = class_to_shost(dev);
252 struct ata_port *ap = ata_shost_to_port(shost);
253 struct ahci_host_priv *hpriv = ap->host->private_data;
254 void __iomem *mmio = hpriv->mmio;
256 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
259 static ssize_t ahci_show_port_cmd(struct device *dev,
260 struct device_attribute *attr, char *buf)
262 struct Scsi_Host *shost = class_to_shost(dev);
263 struct ata_port *ap = ata_shost_to_port(shost);
264 void __iomem *port_mmio = ahci_port_base(ap);
266 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
269 static ssize_t ahci_read_em_buffer(struct device *dev,
270 struct device_attribute *attr, char *buf)
272 struct Scsi_Host *shost = class_to_shost(dev);
273 struct ata_port *ap = ata_shost_to_port(shost);
274 struct ahci_host_priv *hpriv = ap->host->private_data;
275 void __iomem *mmio = hpriv->mmio;
276 void __iomem *em_mmio = mmio + hpriv->em_loc;
282 spin_lock_irqsave(ap->lock, flags);
284 em_ctl = readl(mmio + HOST_EM_CTL);
285 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
286 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
287 spin_unlock_irqrestore(ap->lock, flags);
291 if (!(em_ctl & EM_CTL_MR)) {
292 spin_unlock_irqrestore(ap->lock, flags);
296 if (!(em_ctl & EM_CTL_SMB))
297 em_mmio += hpriv->em_buf_sz;
299 count = hpriv->em_buf_sz;
301 /* the count should not be larger than PAGE_SIZE */
302 if (count > PAGE_SIZE) {
303 if (printk_ratelimit())
305 "EM read buffer size too large: "
306 "buffer size %u, page size %lu\n",
307 hpriv->em_buf_sz, PAGE_SIZE);
311 for (i = 0; i < count; i += 4) {
312 msg = readl(em_mmio + i);
314 buf[i + 1] = (msg >> 8) & 0xff;
315 buf[i + 2] = (msg >> 16) & 0xff;
316 buf[i + 3] = (msg >> 24) & 0xff;
319 spin_unlock_irqrestore(ap->lock, flags);
324 static ssize_t ahci_store_em_buffer(struct device *dev,
325 struct device_attribute *attr,
326 const char *buf, size_t size)
328 struct Scsi_Host *shost = class_to_shost(dev);
329 struct ata_port *ap = ata_shost_to_port(shost);
330 struct ahci_host_priv *hpriv = ap->host->private_data;
331 void __iomem *mmio = hpriv->mmio;
332 void __iomem *em_mmio = mmio + hpriv->em_loc;
333 const unsigned char *msg_buf = buf;
338 /* check size validity */
339 if (!(ap->flags & ATA_FLAG_EM) ||
340 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
341 size % 4 || size > hpriv->em_buf_sz)
344 spin_lock_irqsave(ap->lock, flags);
346 em_ctl = readl(mmio + HOST_EM_CTL);
347 if (em_ctl & EM_CTL_TM) {
348 spin_unlock_irqrestore(ap->lock, flags);
352 for (i = 0; i < size; i += 4) {
353 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
354 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
355 writel(msg, em_mmio + i);
358 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
360 spin_unlock_irqrestore(ap->lock, flags);
365 static ssize_t ahci_show_em_supported(struct device *dev,
366 struct device_attribute *attr, char *buf)
368 struct Scsi_Host *shost = class_to_shost(dev);
369 struct ata_port *ap = ata_shost_to_port(shost);
370 struct ahci_host_priv *hpriv = ap->host->private_data;
371 void __iomem *mmio = hpriv->mmio;
374 em_ctl = readl(mmio + HOST_EM_CTL);
376 return sprintf(buf, "%s%s%s%s\n",
377 em_ctl & EM_CTL_LED ? "led " : "",
378 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
379 em_ctl & EM_CTL_SES ? "ses-2 " : "",
380 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
384 * ahci_save_initial_config - Save and fixup initial config values
385 * @dev: target AHCI device
386 * @hpriv: host private area to store config values
388 * Some registers containing configuration info might be setup by
389 * BIOS and might be cleared on reset. This function saves the
390 * initial values of those registers into @hpriv such that they
391 * can be restored after controller reset.
393 * If inconsistent, config values are fixed up by this function.
395 * If it is not set already this function sets hpriv->start_engine to
401 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
403 void __iomem *mmio = hpriv->mmio;
404 u32 cap, cap2, vers, port_map;
407 /* make sure AHCI mode is enabled before accessing CAP */
408 ahci_enable_ahci(mmio);
410 /* Values prefixed with saved_ are written back to host after
411 * reset. Values without are used for driver operation.
413 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
414 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
416 /* CAP2 register is only defined for AHCI 1.2 and later */
417 vers = readl(mmio + HOST_VERSION);
418 if ((vers >> 16) > 1 ||
419 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
420 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
422 hpriv->saved_cap2 = cap2 = 0;
424 /* some chips have errata preventing 64bit use */
425 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
426 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
430 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
431 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
432 cap &= ~HOST_CAP_NCQ;
435 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
436 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
440 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
441 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
442 cap &= ~HOST_CAP_PMP;
445 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
447 "controller can't do SNTF, turning off CAP_SNTF\n");
448 cap &= ~HOST_CAP_SNTF;
451 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
453 "controller can't do DEVSLP, turning off\n");
454 cap2 &= ~HOST_CAP2_SDS;
455 cap2 &= ~HOST_CAP2_SADM;
458 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
459 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
463 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
464 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
465 cap &= ~HOST_CAP_FBS;
468 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
469 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
470 port_map, hpriv->force_port_map);
471 port_map = hpriv->force_port_map;
474 if (hpriv->mask_port_map) {
475 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
477 port_map & hpriv->mask_port_map);
478 port_map &= hpriv->mask_port_map;
481 /* cross check port_map and cap.n_ports */
485 for (i = 0; i < AHCI_MAX_PORTS; i++)
486 if (port_map & (1 << i))
489 /* If PI has more ports than n_ports, whine, clear
490 * port_map and let it be generated from n_ports.
492 if (map_ports > ahci_nr_ports(cap)) {
494 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
495 port_map, ahci_nr_ports(cap));
500 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
501 if (!port_map && vers < 0x10300) {
502 port_map = (1 << ahci_nr_ports(cap)) - 1;
503 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
505 /* write the fixed up value to the PI register */
506 hpriv->saved_port_map = port_map;
509 /* record values to use during operation */
512 hpriv->port_map = port_map;
514 if (!hpriv->start_engine)
515 hpriv->start_engine = ahci_start_engine;
517 if (!hpriv->irq_handler)
518 hpriv->irq_handler = ahci_single_level_irq_intr;
520 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
523 * ahci_restore_initial_config - Restore initial config
524 * @host: target ATA host
526 * Restore initial config stored by ahci_save_initial_config().
531 static void ahci_restore_initial_config(struct ata_host *host)
533 struct ahci_host_priv *hpriv = host->private_data;
534 void __iomem *mmio = hpriv->mmio;
536 writel(hpriv->saved_cap, mmio + HOST_CAP);
537 if (hpriv->saved_cap2)
538 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
539 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
540 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
543 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
545 static const int offset[] = {
546 [SCR_STATUS] = PORT_SCR_STAT,
547 [SCR_CONTROL] = PORT_SCR_CTL,
548 [SCR_ERROR] = PORT_SCR_ERR,
549 [SCR_ACTIVE] = PORT_SCR_ACT,
550 [SCR_NOTIFICATION] = PORT_SCR_NTF,
552 struct ahci_host_priv *hpriv = ap->host->private_data;
554 if (sc_reg < ARRAY_SIZE(offset) &&
555 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
556 return offset[sc_reg];
560 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
562 void __iomem *port_mmio = ahci_port_base(link->ap);
563 int offset = ahci_scr_offset(link->ap, sc_reg);
566 *val = readl(port_mmio + offset);
572 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
574 void __iomem *port_mmio = ahci_port_base(link->ap);
575 int offset = ahci_scr_offset(link->ap, sc_reg);
578 writel(val, port_mmio + offset);
584 void ahci_start_engine(struct ata_port *ap)
586 void __iomem *port_mmio = ahci_port_base(ap);
590 tmp = readl(port_mmio + PORT_CMD);
591 tmp |= PORT_CMD_START;
592 writel(tmp, port_mmio + PORT_CMD);
593 readl(port_mmio + PORT_CMD); /* flush */
595 EXPORT_SYMBOL_GPL(ahci_start_engine);
597 int ahci_stop_engine(struct ata_port *ap)
599 void __iomem *port_mmio = ahci_port_base(ap);
600 struct ahci_host_priv *hpriv = ap->host->private_data;
604 * On some controllers, stopping a port's DMA engine while the port
605 * is in ALPM state (partial or slumber) results in failures on
606 * subsequent DMA engine starts. For those controllers, put the
607 * port back in active state before stopping its DMA engine.
609 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
610 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
611 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
612 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
616 tmp = readl(port_mmio + PORT_CMD);
618 /* check if the HBA is idle */
619 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
622 /* setting HBA to idle */
623 tmp &= ~PORT_CMD_START;
624 writel(tmp, port_mmio + PORT_CMD);
626 /* wait for engine to stop. This could be as long as 500 msec */
627 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
628 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
629 if (tmp & PORT_CMD_LIST_ON)
634 EXPORT_SYMBOL_GPL(ahci_stop_engine);
636 void ahci_start_fis_rx(struct ata_port *ap)
638 void __iomem *port_mmio = ahci_port_base(ap);
639 struct ahci_host_priv *hpriv = ap->host->private_data;
640 struct ahci_port_priv *pp = ap->private_data;
643 /* set FIS registers */
644 if (hpriv->cap & HOST_CAP_64)
645 writel((pp->cmd_slot_dma >> 16) >> 16,
646 port_mmio + PORT_LST_ADDR_HI);
647 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
649 if (hpriv->cap & HOST_CAP_64)
650 writel((pp->rx_fis_dma >> 16) >> 16,
651 port_mmio + PORT_FIS_ADDR_HI);
652 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
654 /* enable FIS reception */
655 tmp = readl(port_mmio + PORT_CMD);
656 tmp |= PORT_CMD_FIS_RX;
657 writel(tmp, port_mmio + PORT_CMD);
660 readl(port_mmio + PORT_CMD);
662 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
664 static int ahci_stop_fis_rx(struct ata_port *ap)
666 void __iomem *port_mmio = ahci_port_base(ap);
669 /* disable FIS reception */
670 tmp = readl(port_mmio + PORT_CMD);
671 tmp &= ~PORT_CMD_FIS_RX;
672 writel(tmp, port_mmio + PORT_CMD);
674 /* wait for completion, spec says 500ms, give it 1000 */
675 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
676 PORT_CMD_FIS_ON, 10, 1000);
677 if (tmp & PORT_CMD_FIS_ON)
683 static void ahci_power_up(struct ata_port *ap)
685 struct ahci_host_priv *hpriv = ap->host->private_data;
686 void __iomem *port_mmio = ahci_port_base(ap);
689 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
692 if (hpriv->cap & HOST_CAP_SSS) {
693 cmd |= PORT_CMD_SPIN_UP;
694 writel(cmd, port_mmio + PORT_CMD);
698 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
701 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
704 struct ata_port *ap = link->ap;
705 struct ahci_host_priv *hpriv = ap->host->private_data;
706 struct ahci_port_priv *pp = ap->private_data;
707 void __iomem *port_mmio = ahci_port_base(ap);
709 if (policy != ATA_LPM_MAX_POWER) {
710 /* wakeup flag only applies to the max power policy */
711 hints &= ~ATA_LPM_WAKE_ONLY;
714 * Disable interrupts on Phy Ready. This keeps us from
715 * getting woken up due to spurious phy ready
718 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
719 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
721 sata_link_scr_lpm(link, policy, false);
724 if (hpriv->cap & HOST_CAP_ALPM) {
725 u32 cmd = readl(port_mmio + PORT_CMD);
727 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
728 if (!(hints & ATA_LPM_WAKE_ONLY))
729 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
730 cmd |= PORT_CMD_ICC_ACTIVE;
732 writel(cmd, port_mmio + PORT_CMD);
733 readl(port_mmio + PORT_CMD);
735 /* wait 10ms to be sure we've come out of LPM state */
738 if (hints & ATA_LPM_WAKE_ONLY)
741 cmd |= PORT_CMD_ALPE;
742 if (policy == ATA_LPM_MIN_POWER)
745 /* write out new cmd value */
746 writel(cmd, port_mmio + PORT_CMD);
750 /* set aggressive device sleep */
751 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
752 (hpriv->cap2 & HOST_CAP2_SADM) &&
753 (link->device->flags & ATA_DFLAG_DEVSLP)) {
754 if (policy == ATA_LPM_MIN_POWER)
755 ahci_set_aggressive_devslp(ap, true);
757 ahci_set_aggressive_devslp(ap, false);
760 if (policy == ATA_LPM_MAX_POWER) {
761 sata_link_scr_lpm(link, policy, false);
763 /* turn PHYRDY IRQ back on */
764 pp->intr_mask |= PORT_IRQ_PHYRDY;
765 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
772 static void ahci_power_down(struct ata_port *ap)
774 struct ahci_host_priv *hpriv = ap->host->private_data;
775 void __iomem *port_mmio = ahci_port_base(ap);
778 if (!(hpriv->cap & HOST_CAP_SSS))
781 /* put device into listen mode, first set PxSCTL.DET to 0 */
782 scontrol = readl(port_mmio + PORT_SCR_CTL);
784 writel(scontrol, port_mmio + PORT_SCR_CTL);
786 /* then set PxCMD.SUD to 0 */
787 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
788 cmd &= ~PORT_CMD_SPIN_UP;
789 writel(cmd, port_mmio + PORT_CMD);
793 static void ahci_start_port(struct ata_port *ap)
795 struct ahci_host_priv *hpriv = ap->host->private_data;
796 struct ahci_port_priv *pp = ap->private_data;
797 struct ata_link *link;
798 struct ahci_em_priv *emp;
802 /* enable FIS reception */
803 ahci_start_fis_rx(ap);
806 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
807 hpriv->start_engine(ap);
810 if (ap->flags & ATA_FLAG_EM) {
811 ata_for_each_link(link, ap, EDGE) {
812 emp = &pp->em_priv[link->pmp];
814 /* EM Transmit bit maybe busy during init */
815 for (i = 0; i < EM_MAX_RETRY; i++) {
816 rc = ap->ops->transmit_led_message(ap,
820 * If busy, give a breather but do not
821 * release EH ownership by using msleep()
822 * instead of ata_msleep(). EM Transmit
823 * bit is busy for the whole host and
824 * releasing ownership will cause other
825 * ports to fail the same way.
835 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
836 ata_for_each_link(link, ap, EDGE)
837 ahci_init_sw_activity(link);
841 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
846 rc = ahci_stop_engine(ap);
848 *emsg = "failed to stop engine";
852 /* disable FIS reception */
853 rc = ahci_stop_fis_rx(ap);
855 *emsg = "failed stop FIS RX";
862 int ahci_reset_controller(struct ata_host *host)
864 struct ahci_host_priv *hpriv = host->private_data;
865 void __iomem *mmio = hpriv->mmio;
868 /* we must be in AHCI mode, before using anything
869 * AHCI-specific, such as HOST_RESET.
871 ahci_enable_ahci(mmio);
873 /* global controller reset */
874 if (!ahci_skip_host_reset) {
875 tmp = readl(mmio + HOST_CTL);
876 if ((tmp & HOST_RESET) == 0) {
877 writel(tmp | HOST_RESET, mmio + HOST_CTL);
878 readl(mmio + HOST_CTL); /* flush */
882 * to perform host reset, OS should set HOST_RESET
883 * and poll until this bit is read to be "0".
884 * reset must complete within 1 second, or
885 * the hardware should be considered fried.
887 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
888 HOST_RESET, 10, 1000);
890 if (tmp & HOST_RESET) {
891 dev_err(host->dev, "controller reset failed (0x%x)\n",
896 /* turn on AHCI mode */
897 ahci_enable_ahci(mmio);
899 /* Some registers might be cleared on reset. Restore
902 ahci_restore_initial_config(host);
904 dev_info(host->dev, "skipping global host reset\n");
908 EXPORT_SYMBOL_GPL(ahci_reset_controller);
910 static void ahci_sw_activity(struct ata_link *link)
912 struct ata_port *ap = link->ap;
913 struct ahci_port_priv *pp = ap->private_data;
914 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
916 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
920 if (!timer_pending(&emp->timer))
921 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
924 static void ahci_sw_activity_blink(unsigned long arg)
926 struct ata_link *link = (struct ata_link *)arg;
927 struct ata_port *ap = link->ap;
928 struct ahci_port_priv *pp = ap->private_data;
929 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
930 unsigned long led_message = emp->led_state;
931 u32 activity_led_state;
934 led_message &= EM_MSG_LED_VALUE;
935 led_message |= ap->port_no | (link->pmp << 8);
937 /* check to see if we've had activity. If so,
938 * toggle state of LED and reset timer. If not,
939 * turn LED to desired idle state.
941 spin_lock_irqsave(ap->lock, flags);
942 if (emp->saved_activity != emp->activity) {
943 emp->saved_activity = emp->activity;
944 /* get the current LED state */
945 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
947 if (activity_led_state)
948 activity_led_state = 0;
950 activity_led_state = 1;
952 /* clear old state */
953 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
956 led_message |= (activity_led_state << 16);
957 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
960 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
961 if (emp->blink_policy == BLINK_OFF)
962 led_message |= (1 << 16);
964 spin_unlock_irqrestore(ap->lock, flags);
965 ap->ops->transmit_led_message(ap, led_message, 4);
968 static void ahci_init_sw_activity(struct ata_link *link)
970 struct ata_port *ap = link->ap;
971 struct ahci_port_priv *pp = ap->private_data;
972 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
974 /* init activity stats, setup timer */
975 emp->saved_activity = emp->activity = 0;
976 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
978 /* check our blink policy and set flag for link if it's enabled */
979 if (emp->blink_policy)
980 link->flags |= ATA_LFLAG_SW_ACTIVITY;
983 int ahci_reset_em(struct ata_host *host)
985 struct ahci_host_priv *hpriv = host->private_data;
986 void __iomem *mmio = hpriv->mmio;
989 em_ctl = readl(mmio + HOST_EM_CTL);
990 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
993 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
996 EXPORT_SYMBOL_GPL(ahci_reset_em);
998 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1001 struct ahci_host_priv *hpriv = ap->host->private_data;
1002 struct ahci_port_priv *pp = ap->private_data;
1003 void __iomem *mmio = hpriv->mmio;
1005 u32 message[] = {0, 0};
1006 unsigned long flags;
1008 struct ahci_em_priv *emp;
1010 /* get the slot number from the message */
1011 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1012 if (pmp < EM_MAX_SLOTS)
1013 emp = &pp->em_priv[pmp];
1017 spin_lock_irqsave(ap->lock, flags);
1020 * if we are still busy transmitting a previous message,
1023 em_ctl = readl(mmio + HOST_EM_CTL);
1024 if (em_ctl & EM_CTL_TM) {
1025 spin_unlock_irqrestore(ap->lock, flags);
1029 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1031 * create message header - this is all zero except for
1032 * the message size, which is 4 bytes.
1034 message[0] |= (4 << 8);
1036 /* ignore 0:4 of byte zero, fill in port info yourself */
1037 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1039 /* write message to EM_LOC */
1040 writel(message[0], mmio + hpriv->em_loc);
1041 writel(message[1], mmio + hpriv->em_loc+4);
1044 * tell hardware to transmit the message
1046 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1049 /* save off new led state for port/slot */
1050 emp->led_state = state;
1052 spin_unlock_irqrestore(ap->lock, flags);
1056 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1058 struct ahci_port_priv *pp = ap->private_data;
1059 struct ata_link *link;
1060 struct ahci_em_priv *emp;
1063 ata_for_each_link(link, ap, EDGE) {
1064 emp = &pp->em_priv[link->pmp];
1065 rc += sprintf(buf, "%lx\n", emp->led_state);
1070 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1075 struct ahci_port_priv *pp = ap->private_data;
1076 struct ahci_em_priv *emp;
1078 if (kstrtouint(buf, 0, &state) < 0)
1081 /* get the slot number from the message */
1082 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1083 if (pmp < EM_MAX_SLOTS)
1084 emp = &pp->em_priv[pmp];
1088 /* mask off the activity bits if we are in sw_activity
1089 * mode, user should turn off sw_activity before setting
1090 * activity led through em_message
1092 if (emp->blink_policy)
1093 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1095 return ap->ops->transmit_led_message(ap, state, size);
1098 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1100 struct ata_link *link = dev->link;
1101 struct ata_port *ap = link->ap;
1102 struct ahci_port_priv *pp = ap->private_data;
1103 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1104 u32 port_led_state = emp->led_state;
1106 /* save the desired Activity LED behavior */
1109 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1111 /* set the LED to OFF */
1112 port_led_state &= EM_MSG_LED_VALUE_OFF;
1113 port_led_state |= (ap->port_no | (link->pmp << 8));
1114 ap->ops->transmit_led_message(ap, port_led_state, 4);
1116 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1117 if (val == BLINK_OFF) {
1118 /* set LED to ON for idle */
1119 port_led_state &= EM_MSG_LED_VALUE_OFF;
1120 port_led_state |= (ap->port_no | (link->pmp << 8));
1121 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1122 ap->ops->transmit_led_message(ap, port_led_state, 4);
1125 emp->blink_policy = val;
1129 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1131 struct ata_link *link = dev->link;
1132 struct ata_port *ap = link->ap;
1133 struct ahci_port_priv *pp = ap->private_data;
1134 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1136 /* display the saved value of activity behavior for this
1139 return sprintf(buf, "%d\n", emp->blink_policy);
1142 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1143 int port_no, void __iomem *mmio,
1144 void __iomem *port_mmio)
1146 struct ahci_host_priv *hpriv = ap->host->private_data;
1147 const char *emsg = NULL;
1151 /* make sure port is not active */
1152 rc = ahci_deinit_port(ap, &emsg);
1154 dev_warn(dev, "%s (%d)\n", emsg, rc);
1157 tmp = readl(port_mmio + PORT_SCR_ERR);
1158 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1159 writel(tmp, port_mmio + PORT_SCR_ERR);
1161 /* clear port IRQ */
1162 tmp = readl(port_mmio + PORT_IRQ_STAT);
1163 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1165 writel(tmp, port_mmio + PORT_IRQ_STAT);
1167 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1169 /* mark esata ports */
1170 tmp = readl(port_mmio + PORT_CMD);
1171 if ((tmp & PORT_CMD_HPCP) ||
1172 ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)))
1173 ap->pflags |= ATA_PFLAG_EXTERNAL;
1176 void ahci_init_controller(struct ata_host *host)
1178 struct ahci_host_priv *hpriv = host->private_data;
1179 void __iomem *mmio = hpriv->mmio;
1181 void __iomem *port_mmio;
1184 for (i = 0; i < host->n_ports; i++) {
1185 struct ata_port *ap = host->ports[i];
1187 port_mmio = ahci_port_base(ap);
1188 if (ata_port_is_dummy(ap))
1191 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1194 tmp = readl(mmio + HOST_CTL);
1195 VPRINTK("HOST_CTL 0x%x\n", tmp);
1196 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1197 tmp = readl(mmio + HOST_CTL);
1198 VPRINTK("HOST_CTL 0x%x\n", tmp);
1200 EXPORT_SYMBOL_GPL(ahci_init_controller);
1202 static void ahci_dev_config(struct ata_device *dev)
1204 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1206 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1207 dev->max_sectors = 255;
1209 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1213 unsigned int ahci_dev_classify(struct ata_port *ap)
1215 void __iomem *port_mmio = ahci_port_base(ap);
1216 struct ata_taskfile tf;
1219 tmp = readl(port_mmio + PORT_SIG);
1220 tf.lbah = (tmp >> 24) & 0xff;
1221 tf.lbam = (tmp >> 16) & 0xff;
1222 tf.lbal = (tmp >> 8) & 0xff;
1223 tf.nsect = (tmp) & 0xff;
1225 return ata_dev_classify(&tf);
1227 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1229 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1232 dma_addr_t cmd_tbl_dma;
1234 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1236 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1237 pp->cmd_slot[tag].status = 0;
1238 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1239 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1241 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1243 int ahci_kick_engine(struct ata_port *ap)
1245 void __iomem *port_mmio = ahci_port_base(ap);
1246 struct ahci_host_priv *hpriv = ap->host->private_data;
1247 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1252 rc = ahci_stop_engine(ap);
1257 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1259 busy = status & (ATA_BUSY | ATA_DRQ);
1260 if (!busy && !sata_pmp_attached(ap)) {
1265 if (!(hpriv->cap & HOST_CAP_CLO)) {
1271 tmp = readl(port_mmio + PORT_CMD);
1272 tmp |= PORT_CMD_CLO;
1273 writel(tmp, port_mmio + PORT_CMD);
1276 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1277 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1278 if (tmp & PORT_CMD_CLO)
1281 /* restart engine */
1283 hpriv->start_engine(ap);
1286 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1288 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1289 struct ata_taskfile *tf, int is_cmd, u16 flags,
1290 unsigned long timeout_msec)
1292 const u32 cmd_fis_len = 5; /* five dwords */
1293 struct ahci_port_priv *pp = ap->private_data;
1294 void __iomem *port_mmio = ahci_port_base(ap);
1295 u8 *fis = pp->cmd_tbl;
1298 /* prep the command */
1299 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1300 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1302 /* set port value for softreset of Port Multiplier */
1303 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1304 tmp = readl(port_mmio + PORT_FBS);
1305 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1306 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1307 writel(tmp, port_mmio + PORT_FBS);
1308 pp->fbs_last_dev = pmp;
1312 writel(1, port_mmio + PORT_CMD_ISSUE);
1315 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1316 0x1, 0x1, 1, timeout_msec);
1318 ahci_kick_engine(ap);
1322 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1327 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1328 int pmp, unsigned long deadline,
1329 int (*check_ready)(struct ata_link *link))
1331 struct ata_port *ap = link->ap;
1332 struct ahci_host_priv *hpriv = ap->host->private_data;
1333 struct ahci_port_priv *pp = ap->private_data;
1334 const char *reason = NULL;
1335 unsigned long now, msecs;
1336 struct ata_taskfile tf;
1337 bool fbs_disabled = false;
1342 /* prepare for SRST (AHCI-1.1 10.4.1) */
1343 rc = ahci_kick_engine(ap);
1344 if (rc && rc != -EOPNOTSUPP)
1345 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1348 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1349 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1350 * that is attached to port multiplier.
1352 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1353 ahci_disable_fbs(ap);
1354 fbs_disabled = true;
1357 ata_tf_init(link->device, &tf);
1359 /* issue the first D2H Register FIS */
1362 if (time_after(deadline, now))
1363 msecs = jiffies_to_msecs(deadline - now);
1366 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1367 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1369 reason = "1st FIS failed";
1373 /* spec says at least 5us, but be generous and sleep for 1ms */
1376 /* issue the second D2H Register FIS */
1377 tf.ctl &= ~ATA_SRST;
1378 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1380 /* wait for link to become ready */
1381 rc = ata_wait_after_reset(link, deadline, check_ready);
1382 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1384 * Workaround for cases where link online status can't
1385 * be trusted. Treat device readiness timeout as link
1388 ata_link_info(link, "device not ready, treating as offline\n");
1389 *class = ATA_DEV_NONE;
1391 /* link occupied, -ENODEV too is an error */
1392 reason = "device not ready";
1395 *class = ahci_dev_classify(ap);
1397 /* re-enable FBS if disabled before */
1399 ahci_enable_fbs(ap);
1401 DPRINTK("EXIT, class=%u\n", *class);
1405 ata_link_err(link, "softreset failed (%s)\n", reason);
1409 int ahci_check_ready(struct ata_link *link)
1411 void __iomem *port_mmio = ahci_port_base(link->ap);
1412 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1414 return ata_check_ready(status);
1416 EXPORT_SYMBOL_GPL(ahci_check_ready);
1418 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1419 unsigned long deadline)
1421 int pmp = sata_srst_pmp(link);
1425 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1427 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1429 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1431 void __iomem *port_mmio = ahci_port_base(link->ap);
1432 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1433 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1436 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1437 * which can save timeout delay.
1439 if (irq_status & PORT_IRQ_BAD_PMP)
1442 return ata_check_ready(status);
1445 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1446 unsigned long deadline)
1448 struct ata_port *ap = link->ap;
1449 void __iomem *port_mmio = ahci_port_base(ap);
1450 int pmp = sata_srst_pmp(link);
1456 rc = ahci_do_softreset(link, class, pmp, deadline,
1457 ahci_bad_pmp_check_ready);
1460 * Soft reset fails with IPMS set when PMP is enabled but
1461 * SATA HDD/ODD is connected to SATA port, do soft reset
1465 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1466 if (irq_sts & PORT_IRQ_BAD_PMP) {
1468 "applying PMP SRST workaround "
1470 rc = ahci_do_softreset(link, class, 0, deadline,
1478 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1479 unsigned long deadline)
1481 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1482 struct ata_port *ap = link->ap;
1483 struct ahci_port_priv *pp = ap->private_data;
1484 struct ahci_host_priv *hpriv = ap->host->private_data;
1485 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1486 struct ata_taskfile tf;
1492 ahci_stop_engine(ap);
1494 /* clear D2H reception area to properly wait for D2H FIS */
1495 ata_tf_init(link->device, &tf);
1496 tf.command = ATA_BUSY;
1497 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1499 rc = sata_link_hardreset(link, timing, deadline, &online,
1502 hpriv->start_engine(ap);
1505 *class = ahci_dev_classify(ap);
1507 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1511 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1513 struct ata_port *ap = link->ap;
1514 void __iomem *port_mmio = ahci_port_base(ap);
1517 ata_std_postreset(link, class);
1519 /* Make sure port's ATAPI bit is set appropriately */
1520 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1521 if (*class == ATA_DEV_ATAPI)
1522 new_tmp |= PORT_CMD_ATAPI;
1524 new_tmp &= ~PORT_CMD_ATAPI;
1525 if (new_tmp != tmp) {
1526 writel(new_tmp, port_mmio + PORT_CMD);
1527 readl(port_mmio + PORT_CMD); /* flush */
1531 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1533 struct scatterlist *sg;
1534 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1540 * Next, the S/G list.
1542 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1543 dma_addr_t addr = sg_dma_address(sg);
1544 u32 sg_len = sg_dma_len(sg);
1546 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1547 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1548 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1554 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1556 struct ata_port *ap = qc->ap;
1557 struct ahci_port_priv *pp = ap->private_data;
1559 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1560 return ata_std_qc_defer(qc);
1562 return sata_pmp_qc_defer_cmd_switch(qc);
1565 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1567 struct ata_port *ap = qc->ap;
1568 struct ahci_port_priv *pp = ap->private_data;
1569 int is_atapi = ata_is_atapi(qc->tf.protocol);
1572 const u32 cmd_fis_len = 5; /* five dwords */
1573 unsigned int n_elem;
1576 * Fill in command table information. First, the header,
1577 * a SATA Register - Host to Device command FIS.
1579 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1581 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1583 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1584 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1588 if (qc->flags & ATA_QCFLAG_DMAMAP)
1589 n_elem = ahci_fill_sg(qc, cmd_tbl);
1592 * Fill in command slot information.
1594 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1595 if (qc->tf.flags & ATA_TFLAG_WRITE)
1596 opts |= AHCI_CMD_WRITE;
1598 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1600 ahci_fill_cmd_slot(pp, qc->tag, opts);
1603 static void ahci_fbs_dec_intr(struct ata_port *ap)
1605 struct ahci_port_priv *pp = ap->private_data;
1606 void __iomem *port_mmio = ahci_port_base(ap);
1607 u32 fbs = readl(port_mmio + PORT_FBS);
1611 BUG_ON(!pp->fbs_enabled);
1613 /* time to wait for DEC is not specified by AHCI spec,
1614 * add a retry loop for safety.
1616 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1617 fbs = readl(port_mmio + PORT_FBS);
1618 while ((fbs & PORT_FBS_DEC) && retries--) {
1620 fbs = readl(port_mmio + PORT_FBS);
1623 if (fbs & PORT_FBS_DEC)
1624 dev_err(ap->host->dev, "failed to clear device error\n");
1627 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1629 struct ahci_host_priv *hpriv = ap->host->private_data;
1630 struct ahci_port_priv *pp = ap->private_data;
1631 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1632 struct ata_link *link = NULL;
1633 struct ata_queued_cmd *active_qc;
1634 struct ata_eh_info *active_ehi;
1635 bool fbs_need_dec = false;
1638 /* determine active link with error */
1639 if (pp->fbs_enabled) {
1640 void __iomem *port_mmio = ahci_port_base(ap);
1641 u32 fbs = readl(port_mmio + PORT_FBS);
1642 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1644 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1645 link = &ap->pmp_link[pmp];
1646 fbs_need_dec = true;
1650 ata_for_each_link(link, ap, EDGE)
1651 if (ata_link_active(link))
1657 active_qc = ata_qc_from_tag(ap, link->active_tag);
1658 active_ehi = &link->eh_info;
1660 /* record irq stat */
1661 ata_ehi_clear_desc(host_ehi);
1662 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1664 /* AHCI needs SError cleared; otherwise, it might lock up */
1665 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1666 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1667 host_ehi->serror |= serror;
1669 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1670 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1671 irq_stat &= ~PORT_IRQ_IF_ERR;
1673 if (irq_stat & PORT_IRQ_TF_ERR) {
1674 /* If qc is active, charge it; otherwise, the active
1675 * link. There's no active qc on NCQ errors. It will
1676 * be determined by EH by reading log page 10h.
1679 active_qc->err_mask |= AC_ERR_DEV;
1681 active_ehi->err_mask |= AC_ERR_DEV;
1683 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1684 host_ehi->serror &= ~SERR_INTERNAL;
1687 if (irq_stat & PORT_IRQ_UNK_FIS) {
1688 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1690 active_ehi->err_mask |= AC_ERR_HSM;
1691 active_ehi->action |= ATA_EH_RESET;
1692 ata_ehi_push_desc(active_ehi,
1693 "unknown FIS %08x %08x %08x %08x" ,
1694 unk[0], unk[1], unk[2], unk[3]);
1697 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1698 active_ehi->err_mask |= AC_ERR_HSM;
1699 active_ehi->action |= ATA_EH_RESET;
1700 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1703 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1704 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1705 host_ehi->action |= ATA_EH_RESET;
1706 ata_ehi_push_desc(host_ehi, "host bus error");
1709 if (irq_stat & PORT_IRQ_IF_ERR) {
1711 active_ehi->err_mask |= AC_ERR_DEV;
1713 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1714 host_ehi->action |= ATA_EH_RESET;
1717 ata_ehi_push_desc(host_ehi, "interface fatal error");
1720 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1721 ata_ehi_hotplugged(host_ehi);
1722 ata_ehi_push_desc(host_ehi, "%s",
1723 irq_stat & PORT_IRQ_CONNECT ?
1724 "connection status changed" : "PHY RDY changed");
1727 /* okay, let's hand over to EH */
1729 if (irq_stat & PORT_IRQ_FREEZE)
1730 ata_port_freeze(ap);
1731 else if (fbs_need_dec) {
1732 ata_link_abort(link);
1733 ahci_fbs_dec_intr(ap);
1738 static void ahci_handle_port_interrupt(struct ata_port *ap,
1739 void __iomem *port_mmio, u32 status)
1741 struct ata_eh_info *ehi = &ap->link.eh_info;
1742 struct ahci_port_priv *pp = ap->private_data;
1743 struct ahci_host_priv *hpriv = ap->host->private_data;
1744 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1748 /* ignore BAD_PMP while resetting */
1749 if (unlikely(resetting))
1750 status &= ~PORT_IRQ_BAD_PMP;
1752 if (sata_lpm_ignore_phy_events(&ap->link)) {
1753 status &= ~PORT_IRQ_PHYRDY;
1754 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1757 if (unlikely(status & PORT_IRQ_ERROR)) {
1758 ahci_error_intr(ap, status);
1762 if (status & PORT_IRQ_SDB_FIS) {
1763 /* If SNotification is available, leave notification
1764 * handling to sata_async_notification(). If not,
1765 * emulate it by snooping SDB FIS RX area.
1767 * Snooping FIS RX area is probably cheaper than
1768 * poking SNotification but some constrollers which
1769 * implement SNotification, ICH9 for example, don't
1770 * store AN SDB FIS into receive area.
1772 if (hpriv->cap & HOST_CAP_SNTF)
1773 sata_async_notification(ap);
1775 /* If the 'N' bit in word 0 of the FIS is set,
1776 * we just received asynchronous notification.
1777 * Tell libata about it.
1779 * Lack of SNotification should not appear in
1780 * ahci 1.2, so the workaround is unnecessary
1781 * when FBS is enabled.
1783 if (pp->fbs_enabled)
1786 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1787 u32 f0 = le32_to_cpu(f[0]);
1789 sata_async_notification(ap);
1794 /* pp->active_link is not reliable once FBS is enabled, both
1795 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1796 * NCQ and non-NCQ commands may be in flight at the same time.
1798 if (pp->fbs_enabled) {
1799 if (ap->qc_active) {
1800 qc_active = readl(port_mmio + PORT_SCR_ACT);
1801 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1804 /* pp->active_link is valid iff any command is in flight */
1805 if (ap->qc_active && pp->active_link->sactive)
1806 qc_active = readl(port_mmio + PORT_SCR_ACT);
1808 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1812 rc = ata_qc_complete_multiple(ap, qc_active);
1814 /* while resetting, invalid completions are expected */
1815 if (unlikely(rc < 0 && !resetting)) {
1816 ehi->err_mask |= AC_ERR_HSM;
1817 ehi->action |= ATA_EH_RESET;
1818 ata_port_freeze(ap);
1822 static void ahci_port_intr(struct ata_port *ap)
1824 void __iomem *port_mmio = ahci_port_base(ap);
1827 status = readl(port_mmio + PORT_IRQ_STAT);
1828 writel(status, port_mmio + PORT_IRQ_STAT);
1830 ahci_handle_port_interrupt(ap, port_mmio, status);
1833 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
1835 struct ata_port *ap = dev_instance;
1836 void __iomem *port_mmio = ahci_port_base(ap);
1841 status = readl(port_mmio + PORT_IRQ_STAT);
1842 writel(status, port_mmio + PORT_IRQ_STAT);
1844 spin_lock(ap->lock);
1845 ahci_handle_port_interrupt(ap, port_mmio, status);
1846 spin_unlock(ap->lock);
1853 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1855 unsigned int i, handled = 0;
1857 for (i = 0; i < host->n_ports; i++) {
1858 struct ata_port *ap;
1860 if (!(irq_masked & (1 << i)))
1863 ap = host->ports[i];
1866 VPRINTK("port %u\n", i);
1868 VPRINTK("port %u (no irq)\n", i);
1869 if (ata_ratelimit())
1871 "interrupt on disabled port %u\n", i);
1879 EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
1881 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1883 struct ata_host *host = dev_instance;
1884 struct ahci_host_priv *hpriv;
1885 unsigned int rc = 0;
1887 u32 irq_stat, irq_masked;
1891 hpriv = host->private_data;
1894 /* sigh. 0xffffffff is a valid return from h/w */
1895 irq_stat = readl(mmio + HOST_IRQ_STAT);
1899 irq_masked = irq_stat & hpriv->port_map;
1901 spin_lock(&host->lock);
1903 rc = ahci_handle_port_intr(host, irq_masked);
1905 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1906 * it should be cleared after all the port events are cleared;
1907 * otherwise, it will raise a spurious interrupt after each
1908 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1911 * Also, use the unmasked value to clear interrupt as spurious
1912 * pending event on a dummy port might cause screaming IRQ.
1914 writel(irq_stat, mmio + HOST_IRQ_STAT);
1916 spin_unlock(&host->lock);
1920 return IRQ_RETVAL(rc);
1923 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1925 struct ata_port *ap = qc->ap;
1926 void __iomem *port_mmio = ahci_port_base(ap);
1927 struct ahci_port_priv *pp = ap->private_data;
1929 /* Keep track of the currently active link. It will be used
1930 * in completion path to determine whether NCQ phase is in
1933 pp->active_link = qc->dev->link;
1935 if (qc->tf.protocol == ATA_PROT_NCQ)
1936 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1938 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1939 u32 fbs = readl(port_mmio + PORT_FBS);
1940 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1941 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1942 writel(fbs, port_mmio + PORT_FBS);
1943 pp->fbs_last_dev = qc->dev->link->pmp;
1946 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1948 ahci_sw_activity(qc->dev->link);
1952 EXPORT_SYMBOL_GPL(ahci_qc_issue);
1954 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1956 struct ahci_port_priv *pp = qc->ap->private_data;
1957 u8 *rx_fis = pp->rx_fis;
1959 if (pp->fbs_enabled)
1960 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1963 * After a successful execution of an ATA PIO data-in command,
1964 * the device doesn't send D2H Reg FIS to update the TF and
1965 * the host should take TF and E_Status from the preceding PIO
1968 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
1969 !(qc->flags & ATA_QCFLAG_FAILED)) {
1970 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
1971 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
1973 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
1978 static void ahci_freeze(struct ata_port *ap)
1980 void __iomem *port_mmio = ahci_port_base(ap);
1983 writel(0, port_mmio + PORT_IRQ_MASK);
1986 static void ahci_thaw(struct ata_port *ap)
1988 struct ahci_host_priv *hpriv = ap->host->private_data;
1989 void __iomem *mmio = hpriv->mmio;
1990 void __iomem *port_mmio = ahci_port_base(ap);
1992 struct ahci_port_priv *pp = ap->private_data;
1995 tmp = readl(port_mmio + PORT_IRQ_STAT);
1996 writel(tmp, port_mmio + PORT_IRQ_STAT);
1997 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1999 /* turn IRQ back on */
2000 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2003 void ahci_error_handler(struct ata_port *ap)
2005 struct ahci_host_priv *hpriv = ap->host->private_data;
2007 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2008 /* restart engine */
2009 ahci_stop_engine(ap);
2010 hpriv->start_engine(ap);
2013 sata_pmp_error_handler(ap);
2015 if (!ata_dev_enabled(ap->link.device))
2016 ahci_stop_engine(ap);
2018 EXPORT_SYMBOL_GPL(ahci_error_handler);
2020 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2022 struct ata_port *ap = qc->ap;
2024 /* make DMA engine forget about the failed command */
2025 if (qc->flags & ATA_QCFLAG_FAILED)
2026 ahci_kick_engine(ap);
2029 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2031 struct ahci_host_priv *hpriv = ap->host->private_data;
2032 void __iomem *port_mmio = ahci_port_base(ap);
2033 struct ata_device *dev = ap->link.device;
2034 u32 devslp, dm, dito, mdat, deto;
2036 unsigned int err_mask;
2038 devslp = readl(port_mmio + PORT_DEVSLP);
2039 if (!(devslp & PORT_DEVSLP_DSP)) {
2040 dev_info(ap->host->dev, "port does not support device sleep\n");
2044 /* disable device sleep */
2046 if (devslp & PORT_DEVSLP_ADSE) {
2047 writel(devslp & ~PORT_DEVSLP_ADSE,
2048 port_mmio + PORT_DEVSLP);
2049 err_mask = ata_dev_set_feature(dev,
2050 SETFEATURES_SATA_DISABLE,
2052 if (err_mask && err_mask != AC_ERR_DEV)
2053 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2058 /* device sleep was already enabled */
2059 if (devslp & PORT_DEVSLP_ADSE)
2062 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2063 rc = ahci_stop_engine(ap);
2067 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2068 dito = devslp_idle_timeout / (dm + 1);
2072 /* Use the nominal value 10 ms if the read MDAT is zero,
2073 * the nominal value of DETO is 20 ms.
2075 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2076 ATA_LOG_DEVSLP_VALID_MASK) {
2077 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2078 ATA_LOG_DEVSLP_MDAT_MASK;
2081 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2089 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2090 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2091 (deto << PORT_DEVSLP_DETO_OFFSET) |
2093 writel(devslp, port_mmio + PORT_DEVSLP);
2095 hpriv->start_engine(ap);
2097 /* enable device sleep feature for the drive */
2098 err_mask = ata_dev_set_feature(dev,
2099 SETFEATURES_SATA_ENABLE,
2101 if (err_mask && err_mask != AC_ERR_DEV)
2102 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2105 static void ahci_enable_fbs(struct ata_port *ap)
2107 struct ahci_host_priv *hpriv = ap->host->private_data;
2108 struct ahci_port_priv *pp = ap->private_data;
2109 void __iomem *port_mmio = ahci_port_base(ap);
2113 if (!pp->fbs_supported)
2116 fbs = readl(port_mmio + PORT_FBS);
2117 if (fbs & PORT_FBS_EN) {
2118 pp->fbs_enabled = true;
2119 pp->fbs_last_dev = -1; /* initialization */
2123 rc = ahci_stop_engine(ap);
2127 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2128 fbs = readl(port_mmio + PORT_FBS);
2129 if (fbs & PORT_FBS_EN) {
2130 dev_info(ap->host->dev, "FBS is enabled\n");
2131 pp->fbs_enabled = true;
2132 pp->fbs_last_dev = -1; /* initialization */
2134 dev_err(ap->host->dev, "Failed to enable FBS\n");
2136 hpriv->start_engine(ap);
2139 static void ahci_disable_fbs(struct ata_port *ap)
2141 struct ahci_host_priv *hpriv = ap->host->private_data;
2142 struct ahci_port_priv *pp = ap->private_data;
2143 void __iomem *port_mmio = ahci_port_base(ap);
2147 if (!pp->fbs_supported)
2150 fbs = readl(port_mmio + PORT_FBS);
2151 if ((fbs & PORT_FBS_EN) == 0) {
2152 pp->fbs_enabled = false;
2156 rc = ahci_stop_engine(ap);
2160 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2161 fbs = readl(port_mmio + PORT_FBS);
2162 if (fbs & PORT_FBS_EN)
2163 dev_err(ap->host->dev, "Failed to disable FBS\n");
2165 dev_info(ap->host->dev, "FBS is disabled\n");
2166 pp->fbs_enabled = false;
2169 hpriv->start_engine(ap);
2172 static void ahci_pmp_attach(struct ata_port *ap)
2174 void __iomem *port_mmio = ahci_port_base(ap);
2175 struct ahci_port_priv *pp = ap->private_data;
2178 cmd = readl(port_mmio + PORT_CMD);
2179 cmd |= PORT_CMD_PMP;
2180 writel(cmd, port_mmio + PORT_CMD);
2182 ahci_enable_fbs(ap);
2184 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2187 * We must not change the port interrupt mask register if the
2188 * port is marked frozen, the value in pp->intr_mask will be
2189 * restored later when the port is thawed.
2191 * Note that during initialization, the port is marked as
2192 * frozen since the irq handler is not yet registered.
2194 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2195 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2198 static void ahci_pmp_detach(struct ata_port *ap)
2200 void __iomem *port_mmio = ahci_port_base(ap);
2201 struct ahci_port_priv *pp = ap->private_data;
2204 ahci_disable_fbs(ap);
2206 cmd = readl(port_mmio + PORT_CMD);
2207 cmd &= ~PORT_CMD_PMP;
2208 writel(cmd, port_mmio + PORT_CMD);
2210 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2212 /* see comment above in ahci_pmp_attach() */
2213 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2214 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2217 int ahci_port_resume(struct ata_port *ap)
2220 ahci_start_port(ap);
2222 if (sata_pmp_attached(ap))
2223 ahci_pmp_attach(ap);
2225 ahci_pmp_detach(ap);
2229 EXPORT_SYMBOL_GPL(ahci_port_resume);
2232 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2234 const char *emsg = NULL;
2237 rc = ahci_deinit_port(ap, &emsg);
2239 ahci_power_down(ap);
2241 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2242 ata_port_freeze(ap);
2249 static int ahci_port_start(struct ata_port *ap)
2251 struct ahci_host_priv *hpriv = ap->host->private_data;
2252 struct device *dev = ap->host->dev;
2253 struct ahci_port_priv *pp;
2256 size_t dma_sz, rx_fis_sz;
2258 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2262 if (ap->host->n_ports > 1) {
2263 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2264 if (!pp->irq_desc) {
2265 devm_kfree(dev, pp);
2268 snprintf(pp->irq_desc, 8,
2269 "%s%d", dev_driver_string(dev), ap->port_no);
2272 /* check FBS capability */
2273 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2274 void __iomem *port_mmio = ahci_port_base(ap);
2275 u32 cmd = readl(port_mmio + PORT_CMD);
2276 if (cmd & PORT_CMD_FBSCP)
2277 pp->fbs_supported = true;
2278 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2279 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2281 pp->fbs_supported = true;
2283 dev_warn(dev, "port %d is not capable of FBS\n",
2287 if (pp->fbs_supported) {
2288 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2289 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2291 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2292 rx_fis_sz = AHCI_RX_FIS_SZ;
2295 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2298 memset(mem, 0, dma_sz);
2301 * First item in chunk of DMA memory: 32-slot command table,
2302 * 32 bytes each in size
2305 pp->cmd_slot_dma = mem_dma;
2307 mem += AHCI_CMD_SLOT_SZ;
2308 mem_dma += AHCI_CMD_SLOT_SZ;
2311 * Second item: Received-FIS area
2314 pp->rx_fis_dma = mem_dma;
2317 mem_dma += rx_fis_sz;
2320 * Third item: data area for storing a single command
2321 * and its scatter-gather table
2324 pp->cmd_tbl_dma = mem_dma;
2327 * Save off initial list of interrupts to be enabled.
2328 * This could be changed later
2330 pp->intr_mask = DEF_PORT_IRQ;
2333 * Switch to per-port locking in case each port has its own MSI vector.
2335 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2336 spin_lock_init(&pp->lock);
2337 ap->lock = &pp->lock;
2340 ap->private_data = pp;
2342 /* engage engines, captain */
2343 return ahci_port_resume(ap);
2346 static void ahci_port_stop(struct ata_port *ap)
2348 const char *emsg = NULL;
2351 /* de-initialize port */
2352 rc = ahci_deinit_port(ap, &emsg);
2354 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2357 void ahci_print_info(struct ata_host *host, const char *scc_s)
2359 struct ahci_host_priv *hpriv = host->private_data;
2360 void __iomem *mmio = hpriv->mmio;
2361 u32 vers, cap, cap2, impl, speed;
2362 const char *speed_s;
2364 vers = readl(mmio + HOST_VERSION);
2367 impl = hpriv->port_map;
2369 speed = (cap >> 20) & 0xf;
2372 else if (speed == 2)
2374 else if (speed == 3)
2380 "AHCI %02x%02x.%02x%02x "
2381 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2384 (vers >> 24) & 0xff,
2385 (vers >> 16) & 0xff,
2389 ((cap >> 8) & 0x1f) + 1,
2403 cap & HOST_CAP_64 ? "64bit " : "",
2404 cap & HOST_CAP_NCQ ? "ncq " : "",
2405 cap & HOST_CAP_SNTF ? "sntf " : "",
2406 cap & HOST_CAP_MPS ? "ilck " : "",
2407 cap & HOST_CAP_SSS ? "stag " : "",
2408 cap & HOST_CAP_ALPM ? "pm " : "",
2409 cap & HOST_CAP_LED ? "led " : "",
2410 cap & HOST_CAP_CLO ? "clo " : "",
2411 cap & HOST_CAP_ONLY ? "only " : "",
2412 cap & HOST_CAP_PMP ? "pmp " : "",
2413 cap & HOST_CAP_FBS ? "fbs " : "",
2414 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2415 cap & HOST_CAP_SSC ? "slum " : "",
2416 cap & HOST_CAP_PART ? "part " : "",
2417 cap & HOST_CAP_CCC ? "ccc " : "",
2418 cap & HOST_CAP_EMS ? "ems " : "",
2419 cap & HOST_CAP_SXS ? "sxs " : "",
2420 cap2 & HOST_CAP2_DESO ? "deso " : "",
2421 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2422 cap2 & HOST_CAP2_SDS ? "sds " : "",
2423 cap2 & HOST_CAP2_APST ? "apst " : "",
2424 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2425 cap2 & HOST_CAP2_BOH ? "boh " : ""
2428 EXPORT_SYMBOL_GPL(ahci_print_info);
2430 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2431 struct ata_port_info *pi)
2434 void __iomem *mmio = hpriv->mmio;
2435 u32 em_loc = readl(mmio + HOST_EM_LOC);
2436 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2438 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2441 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2445 hpriv->em_loc = ((em_loc >> 16) * 4);
2446 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2447 hpriv->em_msg_type = messages;
2448 pi->flags |= ATA_FLAG_EM;
2449 if (!(em_ctl & EM_CTL_ALHD))
2450 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2453 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2455 static int ahci_host_activate_multi_irqs(struct ata_host *host,
2456 struct scsi_host_template *sht)
2458 struct ahci_host_priv *hpriv = host->private_data;
2461 rc = ata_host_start(host);
2465 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2466 * allocated. That is one MSI per port, starting from @irq.
2468 for (i = 0; i < host->n_ports; i++) {
2469 struct ahci_port_priv *pp = host->ports[i]->private_data;
2470 int irq = ahci_irq_vector(hpriv, i);
2472 /* Do not receive interrupts sent by dummy ports */
2474 disable_irq(irq + i);
2478 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2479 0, pp->irq_desc, host->ports[i]);
2483 ata_port_desc(host->ports[i], "irq %d", irq);
2486 return ata_host_register(host, sht);
2490 * ahci_host_activate - start AHCI host, request IRQs and register it
2491 * @host: target ATA host
2492 * @sht: scsi_host_template to use when registering the host
2495 * Inherited from calling layer (may sleep).
2498 * 0 on success, -errno otherwise.
2500 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2502 struct ahci_host_priv *hpriv = host->private_data;
2503 int irq = hpriv->irq;
2506 if (hpriv->flags & (AHCI_HFLAG_MULTI_MSI | AHCI_HFLAG_MULTI_MSIX)) {
2507 if (hpriv->irq_handler)
2508 dev_warn(host->dev, "both AHCI_HFLAG_MULTI_MSI flag set \
2509 and custom irq handler implemented\n");
2511 rc = ahci_host_activate_multi_irqs(host, sht);
2513 rc = ata_host_activate(host, irq, hpriv->irq_handler,
2520 EXPORT_SYMBOL_GPL(ahci_host_activate);
2522 MODULE_AUTHOR("Jeff Garzik");
2523 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2524 MODULE_LICENSE("GPL");