2 * libata-sff.c - helper library for PCI IDE BMDMA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2006 Jeff Garzik
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/pci.h>
38 #include <linux/libata.h>
39 #include <linux/highmem.h>
43 static struct workqueue_struct *ata_sff_wq;
45 const struct ata_port_operations ata_sff_port_ops = {
46 .inherits = &ata_base_port_ops,
48 .qc_prep = ata_noop_qc_prep,
49 .qc_issue = ata_sff_qc_issue,
50 .qc_fill_rtf = ata_sff_qc_fill_rtf,
52 .freeze = ata_sff_freeze,
54 .prereset = ata_sff_prereset,
55 .softreset = ata_sff_softreset,
56 .hardreset = sata_sff_hardreset,
57 .postreset = ata_sff_postreset,
58 .error_handler = ata_sff_error_handler,
60 .sff_dev_select = ata_sff_dev_select,
61 .sff_check_status = ata_sff_check_status,
62 .sff_tf_load = ata_sff_tf_load,
63 .sff_tf_read = ata_sff_tf_read,
64 .sff_exec_command = ata_sff_exec_command,
65 .sff_data_xfer = ata_sff_data_xfer,
66 .sff_drain_fifo = ata_sff_drain_fifo,
68 .lost_interrupt = ata_sff_lost_interrupt,
70 EXPORT_SYMBOL_GPL(ata_sff_port_ops);
73 * ata_sff_check_status - Read device status reg & clear interrupt
74 * @ap: port where the device is
76 * Reads ATA taskfile status register for currently-selected device
77 * and return its value. This also clears pending interrupts
81 * Inherited from caller.
83 u8 ata_sff_check_status(struct ata_port *ap)
85 return ioread8(ap->ioaddr.status_addr);
87 EXPORT_SYMBOL_GPL(ata_sff_check_status);
90 * ata_sff_altstatus - Read device alternate status reg
91 * @ap: port where the device is
93 * Reads ATA taskfile alternate status register for
94 * currently-selected device and return its value.
96 * Note: may NOT be used as the check_altstatus() entry in
97 * ata_port_operations.
100 * Inherited from caller.
102 static u8 ata_sff_altstatus(struct ata_port *ap)
104 if (ap->ops->sff_check_altstatus)
105 return ap->ops->sff_check_altstatus(ap);
107 return ioread8(ap->ioaddr.altstatus_addr);
111 * ata_sff_irq_status - Check if the device is busy
112 * @ap: port where the device is
114 * Determine if the port is currently busy. Uses altstatus
115 * if available in order to avoid clearing shared IRQ status
116 * when finding an IRQ source. Non ctl capable devices don't
117 * share interrupt lines fortunately for us.
120 * Inherited from caller.
122 static u8 ata_sff_irq_status(struct ata_port *ap)
126 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
127 status = ata_sff_altstatus(ap);
128 /* Not us: We are busy */
129 if (status & ATA_BUSY)
132 /* Clear INTRQ latch */
133 status = ap->ops->sff_check_status(ap);
138 * ata_sff_sync - Flush writes
139 * @ap: Port to wait for.
142 * If we have an mmio device with no ctl and no altstatus
143 * method this will fail. No such devices are known to exist.
146 * Inherited from caller.
149 static void ata_sff_sync(struct ata_port *ap)
151 if (ap->ops->sff_check_altstatus)
152 ap->ops->sff_check_altstatus(ap);
153 else if (ap->ioaddr.altstatus_addr)
154 ioread8(ap->ioaddr.altstatus_addr);
158 * ata_sff_pause - Flush writes and wait 400nS
159 * @ap: Port to pause for.
162 * If we have an mmio device with no ctl and no altstatus
163 * method this will fail. No such devices are known to exist.
166 * Inherited from caller.
169 void ata_sff_pause(struct ata_port *ap)
174 EXPORT_SYMBOL_GPL(ata_sff_pause);
177 * ata_sff_dma_pause - Pause before commencing DMA
178 * @ap: Port to pause for.
180 * Perform I/O fencing and ensure sufficient cycle delays occur
181 * for the HDMA1:0 transition
184 void ata_sff_dma_pause(struct ata_port *ap)
186 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
187 /* An altstatus read will cause the needed delay without
188 messing up the IRQ status */
189 ata_sff_altstatus(ap);
192 /* There are no DMA controllers without ctl. BUG here to ensure
193 we never violate the HDMA1:0 transition timing and risk
197 EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
200 * ata_sff_busy_sleep - sleep until BSY clears, or timeout
201 * @ap: port containing status register to be polled
202 * @tmout_pat: impatience timeout in msecs
203 * @tmout: overall timeout in msecs
205 * Sleep until ATA Status register bit BSY clears,
206 * or a timeout occurs.
209 * Kernel thread context (may sleep).
212 * 0 on success, -errno otherwise.
214 int ata_sff_busy_sleep(struct ata_port *ap,
215 unsigned long tmout_pat, unsigned long tmout)
217 unsigned long timer_start, timeout;
220 status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
221 timer_start = jiffies;
222 timeout = ata_deadline(timer_start, tmout_pat);
223 while (status != 0xff && (status & ATA_BUSY) &&
224 time_before(jiffies, timeout)) {
226 status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
229 if (status != 0xff && (status & ATA_BUSY))
230 ata_port_printk(ap, KERN_WARNING,
231 "port is slow to respond, please be patient "
232 "(Status 0x%x)\n", status);
234 timeout = ata_deadline(timer_start, tmout);
235 while (status != 0xff && (status & ATA_BUSY) &&
236 time_before(jiffies, timeout)) {
238 status = ap->ops->sff_check_status(ap);
244 if (status & ATA_BUSY) {
245 ata_port_printk(ap, KERN_ERR, "port failed to respond "
246 "(%lu secs, Status 0x%x)\n",
247 DIV_ROUND_UP(tmout, 1000), status);
253 EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
255 static int ata_sff_check_ready(struct ata_link *link)
257 u8 status = link->ap->ops->sff_check_status(link->ap);
259 return ata_check_ready(status);
263 * ata_sff_wait_ready - sleep until BSY clears, or timeout
264 * @link: SFF link to wait ready status for
265 * @deadline: deadline jiffies for the operation
267 * Sleep until ATA Status register bit BSY clears, or timeout
271 * Kernel thread context (may sleep).
274 * 0 on success, -errno otherwise.
276 int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
278 return ata_wait_ready(link, deadline, ata_sff_check_ready);
280 EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
283 * ata_sff_set_devctl - Write device control reg
284 * @ap: port where the device is
285 * @ctl: value to write
287 * Writes ATA taskfile device control register.
289 * Note: may NOT be used as the sff_set_devctl() entry in
290 * ata_port_operations.
293 * Inherited from caller.
295 static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl)
297 if (ap->ops->sff_set_devctl)
298 ap->ops->sff_set_devctl(ap, ctl);
300 iowrite8(ctl, ap->ioaddr.ctl_addr);
304 * ata_sff_dev_select - Select device 0/1 on ATA bus
305 * @ap: ATA channel to manipulate
306 * @device: ATA device (numbered from zero) to select
308 * Use the method defined in the ATA specification to
309 * make either device 0, or device 1, active on the
310 * ATA channel. Works with both PIO and MMIO.
312 * May be used as the dev_select() entry in ata_port_operations.
317 void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
322 tmp = ATA_DEVICE_OBS;
324 tmp = ATA_DEVICE_OBS | ATA_DEV1;
326 iowrite8(tmp, ap->ioaddr.device_addr);
327 ata_sff_pause(ap); /* needed; also flushes, for mmio */
329 EXPORT_SYMBOL_GPL(ata_sff_dev_select);
332 * ata_dev_select - Select device 0/1 on ATA bus
333 * @ap: ATA channel to manipulate
334 * @device: ATA device (numbered from zero) to select
335 * @wait: non-zero to wait for Status register BSY bit to clear
336 * @can_sleep: non-zero if context allows sleeping
338 * Use the method defined in the ATA specification to
339 * make either device 0, or device 1, active on the
342 * This is a high-level version of ata_sff_dev_select(), which
343 * additionally provides the services of inserting the proper
344 * pauses and status polling, where needed.
349 static void ata_dev_select(struct ata_port *ap, unsigned int device,
350 unsigned int wait, unsigned int can_sleep)
352 if (ata_msg_probe(ap))
353 ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, "
354 "device %u, wait %u\n", device, wait);
359 ap->ops->sff_dev_select(ap, device);
362 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
369 * ata_sff_irq_on - Enable interrupts on a port.
370 * @ap: Port on which interrupts are enabled.
372 * Enable interrupts on a legacy IDE device using MMIO or PIO,
373 * wait for idle, clear any pending interrupts.
375 * Note: may NOT be used as the sff_irq_on() entry in
376 * ata_port_operations.
379 * Inherited from caller.
381 void ata_sff_irq_on(struct ata_port *ap)
383 struct ata_ioports *ioaddr = &ap->ioaddr;
385 if (ap->ops->sff_irq_on) {
386 ap->ops->sff_irq_on(ap);
390 ap->ctl &= ~ATA_NIEN;
391 ap->last_ctl = ap->ctl;
393 if (ap->ops->sff_set_devctl || ioaddr->ctl_addr)
394 ata_sff_set_devctl(ap, ap->ctl);
397 if (ap->ops->sff_irq_clear)
398 ap->ops->sff_irq_clear(ap);
400 EXPORT_SYMBOL_GPL(ata_sff_irq_on);
403 * ata_sff_tf_load - send taskfile registers to host controller
404 * @ap: Port to which output is sent
405 * @tf: ATA taskfile register set
407 * Outputs ATA taskfile to standard ATA host controller.
410 * Inherited from caller.
412 void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
414 struct ata_ioports *ioaddr = &ap->ioaddr;
415 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
417 if (tf->ctl != ap->last_ctl) {
418 if (ioaddr->ctl_addr)
419 iowrite8(tf->ctl, ioaddr->ctl_addr);
420 ap->last_ctl = tf->ctl;
424 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
425 WARN_ON_ONCE(!ioaddr->ctl_addr);
426 iowrite8(tf->hob_feature, ioaddr->feature_addr);
427 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
428 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
429 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
430 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
431 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
440 iowrite8(tf->feature, ioaddr->feature_addr);
441 iowrite8(tf->nsect, ioaddr->nsect_addr);
442 iowrite8(tf->lbal, ioaddr->lbal_addr);
443 iowrite8(tf->lbam, ioaddr->lbam_addr);
444 iowrite8(tf->lbah, ioaddr->lbah_addr);
445 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
453 if (tf->flags & ATA_TFLAG_DEVICE) {
454 iowrite8(tf->device, ioaddr->device_addr);
455 VPRINTK("device 0x%X\n", tf->device);
460 EXPORT_SYMBOL_GPL(ata_sff_tf_load);
463 * ata_sff_tf_read - input device's ATA taskfile shadow registers
464 * @ap: Port from which input is read
465 * @tf: ATA taskfile register set for storing input
467 * Reads ATA taskfile registers for currently-selected device
468 * into @tf. Assumes the device has a fully SFF compliant task file
469 * layout and behaviour. If you device does not (eg has a different
470 * status method) then you will need to provide a replacement tf_read
473 * Inherited from caller.
475 void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
477 struct ata_ioports *ioaddr = &ap->ioaddr;
479 tf->command = ata_sff_check_status(ap);
480 tf->feature = ioread8(ioaddr->error_addr);
481 tf->nsect = ioread8(ioaddr->nsect_addr);
482 tf->lbal = ioread8(ioaddr->lbal_addr);
483 tf->lbam = ioread8(ioaddr->lbam_addr);
484 tf->lbah = ioread8(ioaddr->lbah_addr);
485 tf->device = ioread8(ioaddr->device_addr);
487 if (tf->flags & ATA_TFLAG_LBA48) {
488 if (likely(ioaddr->ctl_addr)) {
489 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
490 tf->hob_feature = ioread8(ioaddr->error_addr);
491 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
492 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
493 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
494 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
495 iowrite8(tf->ctl, ioaddr->ctl_addr);
496 ap->last_ctl = tf->ctl;
501 EXPORT_SYMBOL_GPL(ata_sff_tf_read);
504 * ata_sff_exec_command - issue ATA command to host controller
505 * @ap: port to which command is being issued
506 * @tf: ATA taskfile register set
508 * Issues ATA command, with proper synchronization with interrupt
509 * handler / other threads.
512 * spin_lock_irqsave(host lock)
514 void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
516 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
518 iowrite8(tf->command, ap->ioaddr.command_addr);
521 EXPORT_SYMBOL_GPL(ata_sff_exec_command);
524 * ata_tf_to_host - issue ATA taskfile to host controller
525 * @ap: port to which command is being issued
526 * @tf: ATA taskfile register set
528 * Issues ATA taskfile register set to ATA host controller,
529 * with proper synchronization with interrupt handler and
533 * spin_lock_irqsave(host lock)
535 static inline void ata_tf_to_host(struct ata_port *ap,
536 const struct ata_taskfile *tf)
538 ap->ops->sff_tf_load(ap, tf);
539 ap->ops->sff_exec_command(ap, tf);
543 * ata_sff_data_xfer - Transfer data by PIO
544 * @dev: device to target
546 * @buflen: buffer length
549 * Transfer data from/to the device data register by PIO.
552 * Inherited from caller.
557 unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf,
558 unsigned int buflen, int rw)
560 struct ata_port *ap = dev->link->ap;
561 void __iomem *data_addr = ap->ioaddr.data_addr;
562 unsigned int words = buflen >> 1;
564 /* Transfer multiple of 2 bytes */
566 ioread16_rep(data_addr, buf, words);
568 iowrite16_rep(data_addr, buf, words);
570 /* Transfer trailing byte, if any. */
571 if (unlikely(buflen & 0x01)) {
572 unsigned char pad[2];
574 /* Point buf to the tail of buffer */
578 * Use io*16_rep() accessors here as well to avoid pointlessly
579 * swapping bytes to and from on the big endian machines...
582 ioread16_rep(data_addr, pad, 1);
586 iowrite16_rep(data_addr, pad, 1);
593 EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
596 * ata_sff_data_xfer32 - Transfer data by PIO
597 * @dev: device to target
599 * @buflen: buffer length
602 * Transfer data from/to the device data register by PIO using 32bit
606 * Inherited from caller.
612 unsigned int ata_sff_data_xfer32(struct ata_device *dev, unsigned char *buf,
613 unsigned int buflen, int rw)
615 struct ata_port *ap = dev->link->ap;
616 void __iomem *data_addr = ap->ioaddr.data_addr;
617 unsigned int words = buflen >> 2;
618 int slop = buflen & 3;
620 if (!(ap->pflags & ATA_PFLAG_PIO32))
621 return ata_sff_data_xfer(dev, buf, buflen, rw);
623 /* Transfer multiple of 4 bytes */
625 ioread32_rep(data_addr, buf, words);
627 iowrite32_rep(data_addr, buf, words);
629 /* Transfer trailing bytes, if any */
630 if (unlikely(slop)) {
631 unsigned char pad[4];
633 /* Point buf to the tail of buffer */
634 buf += buflen - slop;
637 * Use io*_rep() accessors here as well to avoid pointlessly
638 * swapping bytes to and from on the big endian machines...
642 ioread16_rep(data_addr, pad, 1);
644 ioread32_rep(data_addr, pad, 1);
645 memcpy(buf, pad, slop);
647 memcpy(pad, buf, slop);
649 iowrite16_rep(data_addr, pad, 1);
651 iowrite32_rep(data_addr, pad, 1);
654 return (buflen + 1) & ~1;
656 EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
659 * ata_sff_data_xfer_noirq - Transfer data by PIO
660 * @dev: device to target
662 * @buflen: buffer length
665 * Transfer data from/to the device data register by PIO. Do the
666 * transfer with interrupts disabled.
669 * Inherited from caller.
674 unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
675 unsigned int buflen, int rw)
678 unsigned int consumed;
680 local_irq_save(flags);
681 consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
682 local_irq_restore(flags);
686 EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq);
689 * ata_pio_sector - Transfer a sector of data.
690 * @qc: Command on going
692 * Transfer qc->sect_size bytes of data from/to the ATA device.
695 * Inherited from caller.
697 static void ata_pio_sector(struct ata_queued_cmd *qc)
699 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
700 struct ata_port *ap = qc->ap;
705 if (qc->curbytes == qc->nbytes - qc->sect_size)
706 ap->hsm_task_state = HSM_ST_LAST;
708 page = sg_page(qc->cursg);
709 offset = qc->cursg->offset + qc->cursg_ofs;
711 /* get the current page and offset */
712 page = nth_page(page, (offset >> PAGE_SHIFT));
715 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
717 if (PageHighMem(page)) {
720 /* FIXME: use a bounce buffer */
721 local_irq_save(flags);
722 buf = kmap_atomic(page, KM_IRQ0);
724 /* do the actual data transfer */
725 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
728 kunmap_atomic(buf, KM_IRQ0);
729 local_irq_restore(flags);
731 buf = page_address(page);
732 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
736 if (!do_write && !PageSlab(page))
737 flush_dcache_page(page);
739 qc->curbytes += qc->sect_size;
740 qc->cursg_ofs += qc->sect_size;
742 if (qc->cursg_ofs == qc->cursg->length) {
743 qc->cursg = sg_next(qc->cursg);
749 * ata_pio_sectors - Transfer one or many sectors.
750 * @qc: Command on going
752 * Transfer one or many sectors of data from/to the
753 * ATA device for the DRQ request.
756 * Inherited from caller.
758 static void ata_pio_sectors(struct ata_queued_cmd *qc)
760 if (is_multi_taskfile(&qc->tf)) {
761 /* READ/WRITE MULTIPLE */
764 WARN_ON_ONCE(qc->dev->multi_count == 0);
766 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
767 qc->dev->multi_count);
773 ata_sff_sync(qc->ap); /* flush */
777 * atapi_send_cdb - Write CDB bytes to hardware
778 * @ap: Port to which ATAPI device is attached.
779 * @qc: Taskfile currently active
781 * When device has indicated its readiness to accept
782 * a CDB, this function is called. Send the CDB.
787 static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
790 DPRINTK("send cdb\n");
791 WARN_ON_ONCE(qc->dev->cdb_len < 12);
793 ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
795 /* FIXME: If the CDB is for DMA do we need to do the transition delay
796 or is bmdma_start guaranteed to do it ? */
797 switch (qc->tf.protocol) {
799 ap->hsm_task_state = HSM_ST;
801 case ATAPI_PROT_NODATA:
802 ap->hsm_task_state = HSM_ST_LAST;
804 #ifdef CONFIG_ATA_BMDMA
806 ap->hsm_task_state = HSM_ST_LAST;
808 ap->ops->bmdma_start(qc);
810 #endif /* CONFIG_ATA_BMDMA */
817 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
818 * @qc: Command on going
819 * @bytes: number of bytes
821 * Transfer Transfer data from/to the ATAPI device.
824 * Inherited from caller.
827 static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
829 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
830 struct ata_port *ap = qc->ap;
831 struct ata_device *dev = qc->dev;
832 struct ata_eh_info *ehi = &dev->link->eh_info;
833 struct scatterlist *sg;
836 unsigned int offset, count, consumed;
841 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
842 "buf=%u cur=%u bytes=%u",
843 qc->nbytes, qc->curbytes, bytes);
848 offset = sg->offset + qc->cursg_ofs;
850 /* get the current page and offset */
851 page = nth_page(page, (offset >> PAGE_SHIFT));
854 /* don't overrun current sg */
855 count = min(sg->length - qc->cursg_ofs, bytes);
857 /* don't cross page boundaries */
858 count = min(count, (unsigned int)PAGE_SIZE - offset);
860 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
862 if (PageHighMem(page)) {
865 /* FIXME: use bounce buffer */
866 local_irq_save(flags);
867 buf = kmap_atomic(page, KM_IRQ0);
869 /* do the actual data transfer */
870 consumed = ap->ops->sff_data_xfer(dev, buf + offset,
873 kunmap_atomic(buf, KM_IRQ0);
874 local_irq_restore(flags);
876 buf = page_address(page);
877 consumed = ap->ops->sff_data_xfer(dev, buf + offset,
881 bytes -= min(bytes, consumed);
882 qc->curbytes += count;
883 qc->cursg_ofs += count;
885 if (qc->cursg_ofs == sg->length) {
886 qc->cursg = sg_next(qc->cursg);
891 * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed);
892 * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
893 * check correctly as it doesn't know if it is the last request being
894 * made. Somebody should implement a proper sanity check.
902 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
903 * @qc: Command on going
905 * Transfer Transfer data from/to the ATAPI device.
908 * Inherited from caller.
910 static void atapi_pio_bytes(struct ata_queued_cmd *qc)
912 struct ata_port *ap = qc->ap;
913 struct ata_device *dev = qc->dev;
914 struct ata_eh_info *ehi = &dev->link->eh_info;
915 unsigned int ireason, bc_lo, bc_hi, bytes;
916 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
918 /* Abuse qc->result_tf for temp storage of intermediate TF
919 * here to save some kernel stack usage.
920 * For normal completion, qc->result_tf is not relevant. For
921 * error, qc->result_tf is later overwritten by ata_qc_complete().
922 * So, the correctness of qc->result_tf is not affected.
924 ap->ops->sff_tf_read(ap, &qc->result_tf);
925 ireason = qc->result_tf.nsect;
926 bc_lo = qc->result_tf.lbam;
927 bc_hi = qc->result_tf.lbah;
928 bytes = (bc_hi << 8) | bc_lo;
930 /* shall be cleared to zero, indicating xfer of data */
931 if (unlikely(ireason & (1 << 0)))
934 /* make sure transfer direction matches expected */
935 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
936 if (unlikely(do_write != i_write))
939 if (unlikely(!bytes))
942 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
944 if (unlikely(__atapi_pio_bytes(qc, bytes)))
946 ata_sff_sync(ap); /* flush */
951 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
954 qc->err_mask |= AC_ERR_HSM;
955 ap->hsm_task_state = HSM_ST_ERR;
959 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
960 * @ap: the target ata_port
964 * 1 if ok in workqueue, 0 otherwise.
966 static inline int ata_hsm_ok_in_wq(struct ata_port *ap,
967 struct ata_queued_cmd *qc)
969 if (qc->tf.flags & ATA_TFLAG_POLLING)
972 if (ap->hsm_task_state == HSM_ST_FIRST) {
973 if (qc->tf.protocol == ATA_PROT_PIO &&
974 (qc->tf.flags & ATA_TFLAG_WRITE))
977 if (ata_is_atapi(qc->tf.protocol) &&
978 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
986 * ata_hsm_qc_complete - finish a qc running on standard HSM
987 * @qc: Command to complete
988 * @in_wq: 1 if called from workqueue, 0 otherwise
990 * Finish @qc which is running on standard HSM.
993 * If @in_wq is zero, spin_lock_irqsave(host lock).
994 * Otherwise, none on entry and grabs host lock.
996 static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
998 struct ata_port *ap = qc->ap;
1001 if (ap->ops->error_handler) {
1003 spin_lock_irqsave(ap->lock, flags);
1005 /* EH might have kicked in while host lock is
1008 qc = ata_qc_from_tag(ap, qc->tag);
1010 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
1012 ata_qc_complete(qc);
1014 ata_port_freeze(ap);
1017 spin_unlock_irqrestore(ap->lock, flags);
1019 if (likely(!(qc->err_mask & AC_ERR_HSM)))
1020 ata_qc_complete(qc);
1022 ata_port_freeze(ap);
1026 spin_lock_irqsave(ap->lock, flags);
1028 ata_qc_complete(qc);
1029 spin_unlock_irqrestore(ap->lock, flags);
1031 ata_qc_complete(qc);
1036 * ata_sff_hsm_move - move the HSM to the next state.
1037 * @ap: the target ata_port
1039 * @status: current device status
1040 * @in_wq: 1 if called from workqueue, 0 otherwise
1043 * 1 when poll next status needed, 0 otherwise.
1045 int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1046 u8 status, int in_wq)
1048 struct ata_eh_info *ehi = &ap->link.eh_info;
1049 unsigned long flags = 0;
1052 WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
1054 /* Make sure ata_sff_qc_issue() does not throw things
1055 * like DMA polling into the workqueue. Notice that
1056 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1058 WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc));
1061 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1062 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1064 switch (ap->hsm_task_state) {
1066 /* Send first data block or PACKET CDB */
1068 /* If polling, we will stay in the work queue after
1069 * sending the data. Otherwise, interrupt handler
1070 * takes over after sending the data.
1072 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1074 /* check device status */
1075 if (unlikely((status & ATA_DRQ) == 0)) {
1076 /* handle BSY=0, DRQ=0 as error */
1077 if (likely(status & (ATA_ERR | ATA_DF)))
1078 /* device stops HSM for abort/error */
1079 qc->err_mask |= AC_ERR_DEV;
1081 /* HSM violation. Let EH handle this */
1082 ata_ehi_push_desc(ehi,
1083 "ST_FIRST: !(DRQ|ERR|DF)");
1084 qc->err_mask |= AC_ERR_HSM;
1087 ap->hsm_task_state = HSM_ST_ERR;
1091 /* Device should not ask for data transfer (DRQ=1)
1092 * when it finds something wrong.
1093 * We ignore DRQ here and stop the HSM by
1094 * changing hsm_task_state to HSM_ST_ERR and
1095 * let the EH abort the command or reset the device.
1097 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1098 /* Some ATAPI tape drives forget to clear the ERR bit
1099 * when doing the next command (mostly request sense).
1100 * We ignore ERR here to workaround and proceed sending
1103 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1104 ata_ehi_push_desc(ehi, "ST_FIRST: "
1105 "DRQ=1 with device error, "
1106 "dev_stat 0x%X", status);
1107 qc->err_mask |= AC_ERR_HSM;
1108 ap->hsm_task_state = HSM_ST_ERR;
1113 /* Send the CDB (atapi) or the first data block (ata pio out).
1114 * During the state transition, interrupt handler shouldn't
1115 * be invoked before the data transfer is complete and
1116 * hsm_task_state is changed. Hence, the following locking.
1119 spin_lock_irqsave(ap->lock, flags);
1121 if (qc->tf.protocol == ATA_PROT_PIO) {
1122 /* PIO data out protocol.
1123 * send first data block.
1126 /* ata_pio_sectors() might change the state
1127 * to HSM_ST_LAST. so, the state is changed here
1128 * before ata_pio_sectors().
1130 ap->hsm_task_state = HSM_ST;
1131 ata_pio_sectors(qc);
1134 atapi_send_cdb(ap, qc);
1137 spin_unlock_irqrestore(ap->lock, flags);
1139 /* if polling, ata_sff_pio_task() handles the rest.
1140 * otherwise, interrupt handler takes over from here.
1145 /* complete command or read/write the data register */
1146 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1147 /* ATAPI PIO protocol */
1148 if ((status & ATA_DRQ) == 0) {
1149 /* No more data to transfer or device error.
1150 * Device error will be tagged in HSM_ST_LAST.
1152 ap->hsm_task_state = HSM_ST_LAST;
1156 /* Device should not ask for data transfer (DRQ=1)
1157 * when it finds something wrong.
1158 * We ignore DRQ here and stop the HSM by
1159 * changing hsm_task_state to HSM_ST_ERR and
1160 * let the EH abort the command or reset the device.
1162 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1163 ata_ehi_push_desc(ehi, "ST-ATAPI: "
1164 "DRQ=1 with device error, "
1165 "dev_stat 0x%X", status);
1166 qc->err_mask |= AC_ERR_HSM;
1167 ap->hsm_task_state = HSM_ST_ERR;
1171 atapi_pio_bytes(qc);
1173 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1174 /* bad ireason reported by device */
1178 /* ATA PIO protocol */
1179 if (unlikely((status & ATA_DRQ) == 0)) {
1180 /* handle BSY=0, DRQ=0 as error */
1181 if (likely(status & (ATA_ERR | ATA_DF))) {
1182 /* device stops HSM for abort/error */
1183 qc->err_mask |= AC_ERR_DEV;
1185 /* If diagnostic failed and this is
1186 * IDENTIFY, it's likely a phantom
1187 * device. Mark hint.
1189 if (qc->dev->horkage &
1190 ATA_HORKAGE_DIAGNOSTIC)
1194 /* HSM violation. Let EH handle this.
1195 * Phantom devices also trigger this
1196 * condition. Mark hint.
1198 ata_ehi_push_desc(ehi, "ST-ATA: "
1199 "DRQ=0 without device error, "
1200 "dev_stat 0x%X", status);
1201 qc->err_mask |= AC_ERR_HSM |
1205 ap->hsm_task_state = HSM_ST_ERR;
1209 /* For PIO reads, some devices may ask for
1210 * data transfer (DRQ=1) alone with ERR=1.
1211 * We respect DRQ here and transfer one
1212 * block of junk data before changing the
1213 * hsm_task_state to HSM_ST_ERR.
1215 * For PIO writes, ERR=1 DRQ=1 doesn't make
1216 * sense since the data block has been
1217 * transferred to the device.
1219 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1220 /* data might be corrputed */
1221 qc->err_mask |= AC_ERR_DEV;
1223 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1224 ata_pio_sectors(qc);
1225 status = ata_wait_idle(ap);
1228 if (status & (ATA_BUSY | ATA_DRQ)) {
1229 ata_ehi_push_desc(ehi, "ST-ATA: "
1230 "BUSY|DRQ persists on ERR|DF, "
1231 "dev_stat 0x%X", status);
1232 qc->err_mask |= AC_ERR_HSM;
1235 /* There are oddball controllers with
1236 * status register stuck at 0x7f and
1237 * lbal/m/h at zero which makes it
1238 * pass all other presence detection
1239 * mechanisms we have. Set NODEV_HINT
1240 * for it. Kernel bz#7241.
1243 qc->err_mask |= AC_ERR_NODEV_HINT;
1245 /* ata_pio_sectors() might change the
1246 * state to HSM_ST_LAST. so, the state
1247 * is changed after ata_pio_sectors().
1249 ap->hsm_task_state = HSM_ST_ERR;
1253 ata_pio_sectors(qc);
1255 if (ap->hsm_task_state == HSM_ST_LAST &&
1256 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1258 status = ata_wait_idle(ap);
1267 if (unlikely(!ata_ok(status))) {
1268 qc->err_mask |= __ac_err_mask(status);
1269 ap->hsm_task_state = HSM_ST_ERR;
1273 /* no more data to transfer */
1274 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1275 ap->print_id, qc->dev->devno, status);
1277 WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
1279 ap->hsm_task_state = HSM_ST_IDLE;
1281 /* complete taskfile transaction */
1282 ata_hsm_qc_complete(qc, in_wq);
1288 ap->hsm_task_state = HSM_ST_IDLE;
1290 /* complete taskfile transaction */
1291 ata_hsm_qc_complete(qc, in_wq);
1302 EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
1304 void ata_sff_queue_pio_task(struct ata_port *ap, unsigned long delay)
1306 /* may fail if ata_sff_flush_pio_task() in progress */
1307 queue_delayed_work(ata_sff_wq, &ap->sff_pio_task,
1308 msecs_to_jiffies(delay));
1310 EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task);
1312 void ata_sff_flush_pio_task(struct ata_port *ap)
1316 cancel_rearming_delayed_work(&ap->sff_pio_task);
1317 ap->hsm_task_state = HSM_ST_IDLE;
1319 if (ata_msg_ctl(ap))
1320 ata_port_printk(ap, KERN_DEBUG, "%s: EXIT\n", __func__);
1323 static void ata_sff_pio_task(struct work_struct *work)
1325 struct ata_port *ap =
1326 container_of(work, struct ata_port, sff_pio_task.work);
1327 struct ata_queued_cmd *qc;
1331 /* qc can be NULL if timeout occurred */
1332 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1337 WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE);
1340 * This is purely heuristic. This is a fast path.
1341 * Sometimes when we enter, BSY will be cleared in
1342 * a chk-status or two. If not, the drive is probably seeking
1343 * or something. Snooze for a couple msecs, then
1344 * chk-status again. If still busy, queue delayed work.
1346 status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
1347 if (status & ATA_BUSY) {
1349 status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
1350 if (status & ATA_BUSY) {
1351 ata_sff_queue_pio_task(ap, ATA_SHORT_PAUSE);
1357 poll_next = ata_sff_hsm_move(ap, qc, status, 1);
1359 /* another command or interrupt handler
1360 * may be running at this point.
1367 * ata_sff_qc_issue - issue taskfile to a SFF controller
1368 * @qc: command to issue to device
1370 * This function issues a PIO or NODATA command to a SFF
1374 * spin_lock_irqsave(host lock)
1377 * Zero on success, AC_ERR_* mask on failure
1379 unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
1381 struct ata_port *ap = qc->ap;
1383 /* Use polling pio if the LLD doesn't handle
1384 * interrupt driven pio and atapi CDB interrupt.
1386 if (ap->flags & ATA_FLAG_PIO_POLLING)
1387 qc->tf.flags |= ATA_TFLAG_POLLING;
1389 /* select the device */
1390 ata_dev_select(ap, qc->dev->devno, 1, 0);
1392 /* start the command */
1393 switch (qc->tf.protocol) {
1394 case ATA_PROT_NODATA:
1395 if (qc->tf.flags & ATA_TFLAG_POLLING)
1396 ata_qc_set_polling(qc);
1398 ata_tf_to_host(ap, &qc->tf);
1399 ap->hsm_task_state = HSM_ST_LAST;
1401 if (qc->tf.flags & ATA_TFLAG_POLLING)
1402 ata_sff_queue_pio_task(ap, 0);
1407 if (qc->tf.flags & ATA_TFLAG_POLLING)
1408 ata_qc_set_polling(qc);
1410 ata_tf_to_host(ap, &qc->tf);
1412 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1413 /* PIO data out protocol */
1414 ap->hsm_task_state = HSM_ST_FIRST;
1415 ata_sff_queue_pio_task(ap, 0);
1417 /* always send first data block using the
1418 * ata_sff_pio_task() codepath.
1421 /* PIO data in protocol */
1422 ap->hsm_task_state = HSM_ST;
1424 if (qc->tf.flags & ATA_TFLAG_POLLING)
1425 ata_sff_queue_pio_task(ap, 0);
1427 /* if polling, ata_sff_pio_task() handles the
1428 * rest. otherwise, interrupt handler takes
1435 case ATAPI_PROT_PIO:
1436 case ATAPI_PROT_NODATA:
1437 if (qc->tf.flags & ATA_TFLAG_POLLING)
1438 ata_qc_set_polling(qc);
1440 ata_tf_to_host(ap, &qc->tf);
1442 ap->hsm_task_state = HSM_ST_FIRST;
1444 /* send cdb by polling if no cdb interrupt */
1445 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1446 (qc->tf.flags & ATA_TFLAG_POLLING))
1447 ata_sff_queue_pio_task(ap, 0);
1452 return AC_ERR_SYSTEM;
1457 EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
1460 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
1461 * @qc: qc to fill result TF for
1463 * @qc is finished and result TF needs to be filled. Fill it
1464 * using ->sff_tf_read.
1467 * spin_lock_irqsave(host lock)
1470 * true indicating that result TF is successfully filled.
1472 bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
1474 qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
1477 EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
1479 static unsigned int ata_sff_idle_irq(struct ata_port *ap)
1481 ap->stats.idle_irq++;
1484 if ((ap->stats.idle_irq % 1000) == 0) {
1485 ap->ops->sff_check_status(ap);
1486 if (ap->ops->sff_irq_clear)
1487 ap->ops->sff_irq_clear(ap);
1488 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
1492 return 0; /* irq not handled */
1495 static unsigned int __ata_sff_port_intr(struct ata_port *ap,
1496 struct ata_queued_cmd *qc,
1501 VPRINTK("ata%u: protocol %d task_state %d\n",
1502 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1504 /* Check whether we are expecting interrupt in this state */
1505 switch (ap->hsm_task_state) {
1507 /* Some pre-ATAPI-4 devices assert INTRQ
1508 * at this state when ready to receive CDB.
1511 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1512 * The flag was turned on only for atapi devices. No
1513 * need to check ata_is_atapi(qc->tf.protocol) again.
1515 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1516 return ata_sff_idle_irq(ap);
1522 return ata_sff_idle_irq(ap);
1525 /* check main status, clearing INTRQ if needed */
1526 status = ata_sff_irq_status(ap);
1527 if (status & ATA_BUSY) {
1529 /* BMDMA engine is already stopped, we're screwed */
1530 qc->err_mask |= AC_ERR_HSM;
1531 ap->hsm_task_state = HSM_ST_ERR;
1533 return ata_sff_idle_irq(ap);
1536 /* clear irq events */
1537 if (ap->ops->sff_irq_clear)
1538 ap->ops->sff_irq_clear(ap);
1540 ata_sff_hsm_move(ap, qc, status, 0);
1542 return 1; /* irq handled */
1546 * ata_sff_port_intr - Handle SFF port interrupt
1547 * @ap: Port on which interrupt arrived (possibly...)
1548 * @qc: Taskfile currently active in engine
1550 * Handle port interrupt for given queued command.
1553 * spin_lock_irqsave(host lock)
1556 * One if interrupt was handled, zero if not (shared irq).
1558 unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
1560 return __ata_sff_port_intr(ap, qc, false);
1562 EXPORT_SYMBOL_GPL(ata_sff_port_intr);
1564 static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance,
1565 unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *))
1567 struct ata_host *host = dev_instance;
1568 bool retried = false;
1570 unsigned int handled, idle, polling;
1571 unsigned long flags;
1573 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1574 spin_lock_irqsave(&host->lock, flags);
1577 handled = idle = polling = 0;
1578 for (i = 0; i < host->n_ports; i++) {
1579 struct ata_port *ap = host->ports[i];
1580 struct ata_queued_cmd *qc;
1582 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1584 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
1585 handled |= port_intr(ap, qc);
1593 * If no port was expecting IRQ but the controller is actually
1594 * asserting IRQ line, nobody cared will ensue. Check IRQ
1595 * pending status if available and clear spurious IRQ.
1597 if (!handled && !retried) {
1600 for (i = 0; i < host->n_ports; i++) {
1601 struct ata_port *ap = host->ports[i];
1603 if (polling & (1 << i))
1606 if (!ap->ops->sff_irq_check ||
1607 !ap->ops->sff_irq_check(ap))
1610 if (idle & (1 << i)) {
1611 ap->ops->sff_check_status(ap);
1612 if (ap->ops->sff_irq_clear)
1613 ap->ops->sff_irq_clear(ap);
1615 /* clear INTRQ and check if BUSY cleared */
1616 if (!(ap->ops->sff_check_status(ap) & ATA_BUSY))
1619 * With command in flight, we can't do
1620 * sff_irq_clear() w/o racing with completion.
1631 spin_unlock_irqrestore(&host->lock, flags);
1633 return IRQ_RETVAL(handled);
1637 * ata_sff_interrupt - Default SFF ATA host interrupt handler
1638 * @irq: irq line (unused)
1639 * @dev_instance: pointer to our ata_host information structure
1641 * Default interrupt handler for PCI IDE devices. Calls
1642 * ata_sff_port_intr() for each port that is not disabled.
1645 * Obtains host lock during operation.
1648 * IRQ_NONE or IRQ_HANDLED.
1650 irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
1652 return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr);
1654 EXPORT_SYMBOL_GPL(ata_sff_interrupt);
1657 * ata_sff_lost_interrupt - Check for an apparent lost interrupt
1658 * @ap: port that appears to have timed out
1660 * Called from the libata error handlers when the core code suspects
1661 * an interrupt has been lost. If it has complete anything we can and
1662 * then return. Interface must support altstatus for this faster
1663 * recovery to occur.
1666 * Caller holds host lock
1669 void ata_sff_lost_interrupt(struct ata_port *ap)
1672 struct ata_queued_cmd *qc;
1674 /* Only one outstanding command per SFF channel */
1675 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1676 /* We cannot lose an interrupt on a non-existent or polled command */
1677 if (!qc || qc->tf.flags & ATA_TFLAG_POLLING)
1679 /* See if the controller thinks it is still busy - if so the command
1680 isn't a lost IRQ but is still in progress */
1681 status = ata_sff_altstatus(ap);
1682 if (status & ATA_BUSY)
1685 /* There was a command running, we are no longer busy and we have
1687 ata_port_printk(ap, KERN_WARNING, "lost interrupt (Status 0x%x)\n",
1689 /* Run the host interrupt logic as if the interrupt had not been
1691 ata_sff_port_intr(ap, qc);
1693 EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
1696 * ata_sff_freeze - Freeze SFF controller port
1697 * @ap: port to freeze
1699 * Freeze SFF controller port.
1702 * Inherited from caller.
1704 void ata_sff_freeze(struct ata_port *ap)
1706 ap->ctl |= ATA_NIEN;
1707 ap->last_ctl = ap->ctl;
1709 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr)
1710 ata_sff_set_devctl(ap, ap->ctl);
1712 /* Under certain circumstances, some controllers raise IRQ on
1713 * ATA_NIEN manipulation. Also, many controllers fail to mask
1714 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1716 ap->ops->sff_check_status(ap);
1718 if (ap->ops->sff_irq_clear)
1719 ap->ops->sff_irq_clear(ap);
1721 EXPORT_SYMBOL_GPL(ata_sff_freeze);
1724 * ata_sff_thaw - Thaw SFF controller port
1727 * Thaw SFF controller port.
1730 * Inherited from caller.
1732 void ata_sff_thaw(struct ata_port *ap)
1734 /* clear & re-enable interrupts */
1735 ap->ops->sff_check_status(ap);
1736 if (ap->ops->sff_irq_clear)
1737 ap->ops->sff_irq_clear(ap);
1740 EXPORT_SYMBOL_GPL(ata_sff_thaw);
1743 * ata_sff_prereset - prepare SFF link for reset
1744 * @link: SFF link to be reset
1745 * @deadline: deadline jiffies for the operation
1747 * SFF link @link is about to be reset. Initialize it. It first
1748 * calls ata_std_prereset() and wait for !BSY if the port is
1752 * Kernel thread context (may sleep)
1755 * 0 on success, -errno otherwise.
1757 int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
1759 struct ata_eh_context *ehc = &link->eh_context;
1762 rc = ata_std_prereset(link, deadline);
1766 /* if we're about to do hardreset, nothing more to do */
1767 if (ehc->i.action & ATA_EH_HARDRESET)
1770 /* wait for !BSY if we don't know that no device is attached */
1771 if (!ata_link_offline(link)) {
1772 rc = ata_sff_wait_ready(link, deadline);
1773 if (rc && rc != -ENODEV) {
1774 ata_link_printk(link, KERN_WARNING, "device not ready "
1775 "(errno=%d), forcing hardreset\n", rc);
1776 ehc->i.action |= ATA_EH_HARDRESET;
1782 EXPORT_SYMBOL_GPL(ata_sff_prereset);
1785 * ata_devchk - PATA device presence detection
1786 * @ap: ATA channel to examine
1787 * @device: Device to examine (starting at zero)
1789 * This technique was originally described in
1790 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1791 * later found its way into the ATA/ATAPI spec.
1793 * Write a pattern to the ATA shadow registers,
1794 * and if a device is present, it will respond by
1795 * correctly storing and echoing back the
1796 * ATA shadow register contents.
1801 static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
1803 struct ata_ioports *ioaddr = &ap->ioaddr;
1806 ap->ops->sff_dev_select(ap, device);
1808 iowrite8(0x55, ioaddr->nsect_addr);
1809 iowrite8(0xaa, ioaddr->lbal_addr);
1811 iowrite8(0xaa, ioaddr->nsect_addr);
1812 iowrite8(0x55, ioaddr->lbal_addr);
1814 iowrite8(0x55, ioaddr->nsect_addr);
1815 iowrite8(0xaa, ioaddr->lbal_addr);
1817 nsect = ioread8(ioaddr->nsect_addr);
1818 lbal = ioread8(ioaddr->lbal_addr);
1820 if ((nsect == 0x55) && (lbal == 0xaa))
1821 return 1; /* we found a device */
1823 return 0; /* nothing found */
1827 * ata_sff_dev_classify - Parse returned ATA device signature
1828 * @dev: ATA device to classify (starting at zero)
1829 * @present: device seems present
1830 * @r_err: Value of error register on completion
1832 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1833 * an ATA/ATAPI-defined set of values is placed in the ATA
1834 * shadow registers, indicating the results of device detection
1837 * Select the ATA device, and read the values from the ATA shadow
1838 * registers. Then parse according to the Error register value,
1839 * and the spec-defined values examined by ata_dev_classify().
1845 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1847 unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
1850 struct ata_port *ap = dev->link->ap;
1851 struct ata_taskfile tf;
1855 ap->ops->sff_dev_select(ap, dev->devno);
1857 memset(&tf, 0, sizeof(tf));
1859 ap->ops->sff_tf_read(ap, &tf);
1864 /* see if device passed diags: continue and warn later */
1866 /* diagnostic fail : do nothing _YET_ */
1867 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1870 else if ((dev->devno == 0) && (err == 0x81))
1873 return ATA_DEV_NONE;
1875 /* determine if device is ATA or ATAPI */
1876 class = ata_dev_classify(&tf);
1878 if (class == ATA_DEV_UNKNOWN) {
1879 /* If the device failed diagnostic, it's likely to
1880 * have reported incorrect device signature too.
1881 * Assume ATA device if the device seems present but
1882 * device signature is invalid with diagnostic
1885 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1886 class = ATA_DEV_ATA;
1888 class = ATA_DEV_NONE;
1889 } else if ((class == ATA_DEV_ATA) &&
1890 (ap->ops->sff_check_status(ap) == 0))
1891 class = ATA_DEV_NONE;
1895 EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
1898 * ata_sff_wait_after_reset - wait for devices to become ready after reset
1899 * @link: SFF link which is just reset
1900 * @devmask: mask of present devices
1901 * @deadline: deadline jiffies for the operation
1903 * Wait devices attached to SFF @link to become ready after
1904 * reset. It contains preceding 150ms wait to avoid accessing TF
1905 * status register too early.
1908 * Kernel thread context (may sleep).
1911 * 0 on success, -ENODEV if some or all of devices in @devmask
1912 * don't seem to exist. -errno on other errors.
1914 int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
1915 unsigned long deadline)
1917 struct ata_port *ap = link->ap;
1918 struct ata_ioports *ioaddr = &ap->ioaddr;
1919 unsigned int dev0 = devmask & (1 << 0);
1920 unsigned int dev1 = devmask & (1 << 1);
1923 msleep(ATA_WAIT_AFTER_RESET);
1925 /* always check readiness of the master device */
1926 rc = ata_sff_wait_ready(link, deadline);
1927 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
1928 * and TF status is 0xff, bail out on it too.
1933 /* if device 1 was found in ata_devchk, wait for register
1934 * access briefly, then wait for BSY to clear.
1939 ap->ops->sff_dev_select(ap, 1);
1941 /* Wait for register access. Some ATAPI devices fail
1942 * to set nsect/lbal after reset, so don't waste too
1943 * much time on it. We're gonna wait for !BSY anyway.
1945 for (i = 0; i < 2; i++) {
1948 nsect = ioread8(ioaddr->nsect_addr);
1949 lbal = ioread8(ioaddr->lbal_addr);
1950 if ((nsect == 1) && (lbal == 1))
1952 msleep(50); /* give drive a breather */
1955 rc = ata_sff_wait_ready(link, deadline);
1963 /* is all this really necessary? */
1964 ap->ops->sff_dev_select(ap, 0);
1966 ap->ops->sff_dev_select(ap, 1);
1968 ap->ops->sff_dev_select(ap, 0);
1972 EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
1974 static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
1975 unsigned long deadline)
1977 struct ata_ioports *ioaddr = &ap->ioaddr;
1979 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
1981 /* software reset. causes dev0 to be selected */
1982 iowrite8(ap->ctl, ioaddr->ctl_addr);
1983 udelay(20); /* FIXME: flush */
1984 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1985 udelay(20); /* FIXME: flush */
1986 iowrite8(ap->ctl, ioaddr->ctl_addr);
1987 ap->last_ctl = ap->ctl;
1989 /* wait the port to become ready */
1990 return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
1994 * ata_sff_softreset - reset host port via ATA SRST
1995 * @link: ATA link to reset
1996 * @classes: resulting classes of attached devices
1997 * @deadline: deadline jiffies for the operation
1999 * Reset host port using ATA SRST.
2002 * Kernel thread context (may sleep)
2005 * 0 on success, -errno otherwise.
2007 int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
2008 unsigned long deadline)
2010 struct ata_port *ap = link->ap;
2011 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2012 unsigned int devmask = 0;
2018 /* determine if device 0/1 are present */
2019 if (ata_devchk(ap, 0))
2020 devmask |= (1 << 0);
2021 if (slave_possible && ata_devchk(ap, 1))
2022 devmask |= (1 << 1);
2024 /* select device 0 again */
2025 ap->ops->sff_dev_select(ap, 0);
2027 /* issue bus reset */
2028 DPRINTK("about to softreset, devmask=%x\n", devmask);
2029 rc = ata_bus_softreset(ap, devmask, deadline);
2030 /* if link is occupied, -ENODEV too is an error */
2031 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
2032 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
2036 /* determine by signature whether we have ATA or ATAPI devices */
2037 classes[0] = ata_sff_dev_classify(&link->device[0],
2038 devmask & (1 << 0), &err);
2039 if (slave_possible && err != 0x81)
2040 classes[1] = ata_sff_dev_classify(&link->device[1],
2041 devmask & (1 << 1), &err);
2043 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2046 EXPORT_SYMBOL_GPL(ata_sff_softreset);
2049 * sata_sff_hardreset - reset host port via SATA phy reset
2050 * @link: link to reset
2051 * @class: resulting class of attached device
2052 * @deadline: deadline jiffies for the operation
2054 * SATA phy-reset host port using DET bits of SControl register,
2055 * wait for !BSY and classify the attached device.
2058 * Kernel thread context (may sleep)
2061 * 0 on success, -errno otherwise.
2063 int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
2064 unsigned long deadline)
2066 struct ata_eh_context *ehc = &link->eh_context;
2067 const unsigned long *timing = sata_ehc_deb_timing(ehc);
2071 rc = sata_link_hardreset(link, timing, deadline, &online,
2072 ata_sff_check_ready);
2074 *class = ata_sff_dev_classify(link->device, 1, NULL);
2076 DPRINTK("EXIT, class=%u\n", *class);
2079 EXPORT_SYMBOL_GPL(sata_sff_hardreset);
2082 * ata_sff_postreset - SFF postreset callback
2083 * @link: the target SFF ata_link
2084 * @classes: classes of attached devices
2086 * This function is invoked after a successful reset. It first
2087 * calls ata_std_postreset() and performs SFF specific postreset
2091 * Kernel thread context (may sleep)
2093 void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
2095 struct ata_port *ap = link->ap;
2097 ata_std_postreset(link, classes);
2099 /* is double-select really necessary? */
2100 if (classes[0] != ATA_DEV_NONE)
2101 ap->ops->sff_dev_select(ap, 1);
2102 if (classes[1] != ATA_DEV_NONE)
2103 ap->ops->sff_dev_select(ap, 0);
2105 /* bail out if no device is present */
2106 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2107 DPRINTK("EXIT, no device\n");
2111 /* set up device control */
2112 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) {
2113 ata_sff_set_devctl(ap, ap->ctl);
2114 ap->last_ctl = ap->ctl;
2117 EXPORT_SYMBOL_GPL(ata_sff_postreset);
2120 * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers
2123 * Drain the FIFO and device of any stuck data following a command
2124 * failing to complete. In some cases this is necessary before a
2125 * reset will recover the device.
2129 void ata_sff_drain_fifo(struct ata_queued_cmd *qc)
2132 struct ata_port *ap;
2134 /* We only need to flush incoming data when a command was running */
2135 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
2139 /* Drain up to 64K of data before we give up this recovery method */
2140 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
2141 && count < 65536; count += 2)
2142 ioread16(ap->ioaddr.data_addr);
2144 /* Can become DEBUG later */
2146 ata_port_printk(ap, KERN_DEBUG,
2147 "drained %d bytes to clear DRQ.\n", count);
2150 EXPORT_SYMBOL_GPL(ata_sff_drain_fifo);
2153 * ata_sff_error_handler - Stock error handler for SFF controller
2154 * @ap: port to handle error for
2156 * Stock error handler for SFF controller. It can handle both
2157 * PATA and SATA controllers. Many controllers should be able to
2158 * use this EH as-is or with some added handling before and
2162 * Kernel thread context (may sleep)
2164 void ata_sff_error_handler(struct ata_port *ap)
2166 ata_reset_fn_t softreset = ap->ops->softreset;
2167 ata_reset_fn_t hardreset = ap->ops->hardreset;
2168 struct ata_queued_cmd *qc;
2169 unsigned long flags;
2171 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2172 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2175 spin_lock_irqsave(ap->lock, flags);
2178 * We *MUST* do FIFO draining before we issue a reset as
2179 * several devices helpfully clear their internal state and
2180 * will lock solid if we touch the data port post reset. Pass
2181 * qc in case anyone wants to do different PIO/DMA recovery or
2182 * has per command fixups
2184 if (ap->ops->sff_drain_fifo)
2185 ap->ops->sff_drain_fifo(qc);
2187 spin_unlock_irqrestore(ap->lock, flags);
2189 /* ignore ata_sff_softreset if ctl isn't accessible */
2190 if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr)
2193 /* ignore built-in hardresets if SCR access is not available */
2194 if ((hardreset == sata_std_hardreset ||
2195 hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link))
2198 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2199 ap->ops->postreset);
2201 EXPORT_SYMBOL_GPL(ata_sff_error_handler);
2204 * ata_sff_std_ports - initialize ioaddr with standard port offsets.
2205 * @ioaddr: IO address structure to be initialized
2207 * Utility function which initializes data_addr, error_addr,
2208 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2209 * device_addr, status_addr, and command_addr to standard offsets
2210 * relative to cmd_addr.
2212 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2214 void ata_sff_std_ports(struct ata_ioports *ioaddr)
2216 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2217 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2218 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2219 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2220 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2221 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2222 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2223 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2224 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2225 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2227 EXPORT_SYMBOL_GPL(ata_sff_std_ports);
2231 static int ata_resources_present(struct pci_dev *pdev, int port)
2235 /* Check the PCI resources for this channel are enabled */
2237 for (i = 0; i < 2; i++) {
2238 if (pci_resource_start(pdev, port + i) == 0 ||
2239 pci_resource_len(pdev, port + i) == 0)
2246 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
2247 * @host: target ATA host
2249 * Acquire native PCI ATA resources for @host and initialize the
2250 * first two ports of @host accordingly. Ports marked dummy are
2251 * skipped and allocation failure makes the port dummy.
2253 * Note that native PCI resources are valid even for legacy hosts
2254 * as we fix up pdev resources array early in boot, so this
2255 * function can be used for both native and legacy SFF hosts.
2258 * Inherited from calling layer (may sleep).
2261 * 0 if at least one port is initialized, -ENODEV if no port is
2264 int ata_pci_sff_init_host(struct ata_host *host)
2266 struct device *gdev = host->dev;
2267 struct pci_dev *pdev = to_pci_dev(gdev);
2268 unsigned int mask = 0;
2271 /* request, iomap BARs and init port addresses accordingly */
2272 for (i = 0; i < 2; i++) {
2273 struct ata_port *ap = host->ports[i];
2275 void __iomem * const *iomap;
2277 if (ata_port_is_dummy(ap))
2280 /* Discard disabled ports. Some controllers show
2281 * their unused channels this way. Disabled ports are
2284 if (!ata_resources_present(pdev, i)) {
2285 ap->ops = &ata_dummy_port_ops;
2289 rc = pcim_iomap_regions(pdev, 0x3 << base,
2290 dev_driver_string(gdev));
2292 dev_printk(KERN_WARNING, gdev,
2293 "failed to request/iomap BARs for port %d "
2294 "(errno=%d)\n", i, rc);
2296 pcim_pin_device(pdev);
2297 ap->ops = &ata_dummy_port_ops;
2300 host->iomap = iomap = pcim_iomap_table(pdev);
2302 ap->ioaddr.cmd_addr = iomap[base];
2303 ap->ioaddr.altstatus_addr =
2304 ap->ioaddr.ctl_addr = (void __iomem *)
2305 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
2306 ata_sff_std_ports(&ap->ioaddr);
2308 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2309 (unsigned long long)pci_resource_start(pdev, base),
2310 (unsigned long long)pci_resource_start(pdev, base + 1));
2316 dev_printk(KERN_ERR, gdev, "no available native port\n");
2322 EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
2325 * ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host
2326 * @pdev: target PCI device
2327 * @ppi: array of port_info, must be enough for two ports
2328 * @r_host: out argument for the initialized ATA host
2330 * Helper to allocate PIO-only SFF ATA host for @pdev, acquire
2331 * all PCI resources and initialize it accordingly in one go.
2334 * Inherited from calling layer (may sleep).
2337 * 0 on success, -errno otherwise.
2339 int ata_pci_sff_prepare_host(struct pci_dev *pdev,
2340 const struct ata_port_info * const *ppi,
2341 struct ata_host **r_host)
2343 struct ata_host *host;
2346 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2349 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2351 dev_printk(KERN_ERR, &pdev->dev,
2352 "failed to allocate ATA host\n");
2357 rc = ata_pci_sff_init_host(host);
2361 devres_remove_group(&pdev->dev, NULL);
2366 devres_release_group(&pdev->dev, NULL);
2369 EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
2372 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
2373 * @host: target SFF ATA host
2374 * @irq_handler: irq_handler used when requesting IRQ(s)
2375 * @sht: scsi_host_template to use when registering the host
2377 * This is the counterpart of ata_host_activate() for SFF ATA
2378 * hosts. This separate helper is necessary because SFF hosts
2379 * use two separate interrupts in legacy mode.
2382 * Inherited from calling layer (may sleep).
2385 * 0 on success, -errno otherwise.
2387 int ata_pci_sff_activate_host(struct ata_host *host,
2388 irq_handler_t irq_handler,
2389 struct scsi_host_template *sht)
2391 struct device *dev = host->dev;
2392 struct pci_dev *pdev = to_pci_dev(dev);
2393 const char *drv_name = dev_driver_string(host->dev);
2394 int legacy_mode = 0, rc;
2396 rc = ata_host_start(host);
2400 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2403 /* TODO: What if one channel is in native mode ... */
2404 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2405 mask = (1 << 2) | (1 << 0);
2406 if ((tmp8 & mask) != mask)
2408 #if defined(CONFIG_NO_ATA_LEGACY)
2409 /* Some platforms with PCI limits cannot address compat
2410 port space. In that case we punt if their firmware has
2411 left a device in compatibility mode */
2413 printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n");
2419 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2422 if (!legacy_mode && pdev->irq) {
2423 rc = devm_request_irq(dev, pdev->irq, irq_handler,
2424 IRQF_SHARED, drv_name, host);
2428 ata_port_desc(host->ports[0], "irq %d", pdev->irq);
2429 ata_port_desc(host->ports[1], "irq %d", pdev->irq);
2430 } else if (legacy_mode) {
2431 if (!ata_port_is_dummy(host->ports[0])) {
2432 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2433 irq_handler, IRQF_SHARED,
2438 ata_port_desc(host->ports[0], "irq %d",
2439 ATA_PRIMARY_IRQ(pdev));
2442 if (!ata_port_is_dummy(host->ports[1])) {
2443 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2444 irq_handler, IRQF_SHARED,
2449 ata_port_desc(host->ports[1], "irq %d",
2450 ATA_SECONDARY_IRQ(pdev));
2454 rc = ata_host_register(host, sht);
2457 devres_remove_group(dev, NULL);
2459 devres_release_group(dev, NULL);
2463 EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
2465 static const struct ata_port_info *ata_sff_find_valid_pi(
2466 const struct ata_port_info * const *ppi)
2470 /* look up the first valid port_info */
2471 for (i = 0; i < 2 && ppi[i]; i++)
2472 if (ppi[i]->port_ops != &ata_dummy_port_ops)
2479 * ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller
2480 * @pdev: Controller to be initialized
2481 * @ppi: array of port_info, must be enough for two ports
2482 * @sht: scsi_host_template to use when registering the host
2483 * @host_priv: host private_data
2484 * @hflag: host flags
2486 * This is a helper function which can be called from a driver's
2487 * xxx_init_one() probe function if the hardware uses traditional
2488 * IDE taskfile registers and is PIO only.
2491 * Nobody makes a single channel controller that appears solely as
2492 * the secondary legacy port on PCI.
2495 * Inherited from PCI layer (may sleep).
2498 * Zero on success, negative on errno-based value on error.
2500 int ata_pci_sff_init_one(struct pci_dev *pdev,
2501 const struct ata_port_info * const *ppi,
2502 struct scsi_host_template *sht, void *host_priv, int hflag)
2504 struct device *dev = &pdev->dev;
2505 const struct ata_port_info *pi;
2506 struct ata_host *host = NULL;
2511 pi = ata_sff_find_valid_pi(ppi);
2513 dev_printk(KERN_ERR, &pdev->dev,
2514 "no valid port_info specified\n");
2518 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2521 rc = pcim_enable_device(pdev);
2525 /* prepare and activate SFF host */
2526 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
2529 host->private_data = host_priv;
2530 host->flags |= hflag;
2532 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
2535 devres_remove_group(&pdev->dev, NULL);
2537 devres_release_group(&pdev->dev, NULL);
2541 EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
2543 #endif /* CONFIG_PCI */
2549 #ifdef CONFIG_ATA_BMDMA
2551 const struct ata_port_operations ata_bmdma_port_ops = {
2552 .inherits = &ata_sff_port_ops,
2554 .error_handler = ata_bmdma_error_handler,
2555 .post_internal_cmd = ata_bmdma_post_internal_cmd,
2557 .qc_prep = ata_bmdma_qc_prep,
2558 .qc_issue = ata_bmdma_qc_issue,
2560 .sff_irq_clear = ata_bmdma_irq_clear,
2561 .bmdma_setup = ata_bmdma_setup,
2562 .bmdma_start = ata_bmdma_start,
2563 .bmdma_stop = ata_bmdma_stop,
2564 .bmdma_status = ata_bmdma_status,
2566 .port_start = ata_bmdma_port_start,
2568 EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
2570 const struct ata_port_operations ata_bmdma32_port_ops = {
2571 .inherits = &ata_bmdma_port_ops,
2573 .sff_data_xfer = ata_sff_data_xfer32,
2574 .port_start = ata_bmdma_port_start32,
2576 EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
2579 * ata_bmdma_fill_sg - Fill PCI IDE PRD table
2580 * @qc: Metadata associated with taskfile to be transferred
2582 * Fill PCI IDE PRD (scatter-gather) table with segments
2583 * associated with the current disk command.
2586 * spin_lock_irqsave(host lock)
2589 static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc)
2591 struct ata_port *ap = qc->ap;
2592 struct ata_bmdma_prd *prd = ap->bmdma_prd;
2593 struct scatterlist *sg;
2594 unsigned int si, pi;
2597 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2601 /* determine if physical DMA addr spans 64K boundary.
2602 * Note h/w doesn't support 64-bit, so we unconditionally
2603 * truncate dma_addr_t to u32.
2605 addr = (u32) sg_dma_address(sg);
2606 sg_len = sg_dma_len(sg);
2609 offset = addr & 0xffff;
2611 if ((offset + sg_len) > 0x10000)
2612 len = 0x10000 - offset;
2614 prd[pi].addr = cpu_to_le32(addr);
2615 prd[pi].flags_len = cpu_to_le32(len & 0xffff);
2616 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
2624 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2628 * ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table
2629 * @qc: Metadata associated with taskfile to be transferred
2631 * Fill PCI IDE PRD (scatter-gather) table with segments
2632 * associated with the current disk command. Perform the fill
2633 * so that we avoid writing any length 64K records for
2634 * controllers that don't follow the spec.
2637 * spin_lock_irqsave(host lock)
2640 static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc)
2642 struct ata_port *ap = qc->ap;
2643 struct ata_bmdma_prd *prd = ap->bmdma_prd;
2644 struct scatterlist *sg;
2645 unsigned int si, pi;
2648 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2650 u32 sg_len, len, blen;
2652 /* determine if physical DMA addr spans 64K boundary.
2653 * Note h/w doesn't support 64-bit, so we unconditionally
2654 * truncate dma_addr_t to u32.
2656 addr = (u32) sg_dma_address(sg);
2657 sg_len = sg_dma_len(sg);
2660 offset = addr & 0xffff;
2662 if ((offset + sg_len) > 0x10000)
2663 len = 0x10000 - offset;
2665 blen = len & 0xffff;
2666 prd[pi].addr = cpu_to_le32(addr);
2668 /* Some PATA chipsets like the CS5530 can't
2669 cope with 0x0000 meaning 64K as the spec
2671 prd[pi].flags_len = cpu_to_le32(0x8000);
2673 prd[++pi].addr = cpu_to_le32(addr + 0x8000);
2675 prd[pi].flags_len = cpu_to_le32(blen);
2676 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
2684 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2688 * ata_bmdma_qc_prep - Prepare taskfile for submission
2689 * @qc: Metadata associated with taskfile to be prepared
2691 * Prepare ATA taskfile for submission.
2694 * spin_lock_irqsave(host lock)
2696 void ata_bmdma_qc_prep(struct ata_queued_cmd *qc)
2698 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2701 ata_bmdma_fill_sg(qc);
2703 EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep);
2706 * ata_bmdma_dumb_qc_prep - Prepare taskfile for submission
2707 * @qc: Metadata associated with taskfile to be prepared
2709 * Prepare ATA taskfile for submission.
2712 * spin_lock_irqsave(host lock)
2714 void ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc)
2716 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2719 ata_bmdma_fill_sg_dumb(qc);
2721 EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep);
2724 * ata_bmdma_qc_issue - issue taskfile to a BMDMA controller
2725 * @qc: command to issue to device
2727 * This function issues a PIO, NODATA or DMA command to a
2728 * SFF/BMDMA controller. PIO and NODATA are handled by
2729 * ata_sff_qc_issue().
2732 * spin_lock_irqsave(host lock)
2735 * Zero on success, AC_ERR_* mask on failure
2737 unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc)
2739 struct ata_port *ap = qc->ap;
2741 /* defer PIO handling to sff_qc_issue */
2742 if (!ata_is_dma(qc->tf.protocol))
2743 return ata_sff_qc_issue(qc);
2745 /* select the device */
2746 ata_dev_select(ap, qc->dev->devno, 1, 0);
2748 /* start the command */
2749 switch (qc->tf.protocol) {
2751 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2753 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2754 ap->ops->bmdma_setup(qc); /* set up bmdma */
2755 ap->ops->bmdma_start(qc); /* initiate bmdma */
2756 ap->hsm_task_state = HSM_ST_LAST;
2759 case ATAPI_PROT_DMA:
2760 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2762 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2763 ap->ops->bmdma_setup(qc); /* set up bmdma */
2764 ap->hsm_task_state = HSM_ST_FIRST;
2766 /* send cdb by polling if no cdb interrupt */
2767 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
2768 ata_sff_queue_pio_task(ap, 0);
2773 return AC_ERR_SYSTEM;
2778 EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue);
2781 * ata_bmdma_port_intr - Handle BMDMA port interrupt
2782 * @ap: Port on which interrupt arrived (possibly...)
2783 * @qc: Taskfile currently active in engine
2785 * Handle port interrupt for given queued command.
2788 * spin_lock_irqsave(host lock)
2791 * One if interrupt was handled, zero if not (shared irq).
2793 unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
2795 struct ata_eh_info *ehi = &ap->link.eh_info;
2797 bool bmdma_stopped = false;
2798 unsigned int handled;
2800 if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) {
2801 /* check status of DMA engine */
2802 host_stat = ap->ops->bmdma_status(ap);
2803 VPRINTK("ata%u: host_stat 0x%X\n", ap->print_id, host_stat);
2805 /* if it's not our irq... */
2806 if (!(host_stat & ATA_DMA_INTR))
2807 return ata_sff_idle_irq(ap);
2809 /* before we do anything else, clear DMA-Start bit */
2810 ap->ops->bmdma_stop(qc);
2811 bmdma_stopped = true;
2813 if (unlikely(host_stat & ATA_DMA_ERR)) {
2814 /* error when transfering data to/from memory */
2815 qc->err_mask |= AC_ERR_HOST_BUS;
2816 ap->hsm_task_state = HSM_ST_ERR;
2820 handled = __ata_sff_port_intr(ap, qc, bmdma_stopped);
2822 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
2823 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
2827 EXPORT_SYMBOL_GPL(ata_bmdma_port_intr);
2830 * ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler
2831 * @irq: irq line (unused)
2832 * @dev_instance: pointer to our ata_host information structure
2834 * Default interrupt handler for PCI IDE devices. Calls
2835 * ata_bmdma_port_intr() for each port that is not disabled.
2838 * Obtains host lock during operation.
2841 * IRQ_NONE or IRQ_HANDLED.
2843 irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance)
2845 return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr);
2847 EXPORT_SYMBOL_GPL(ata_bmdma_interrupt);
2850 * ata_bmdma_error_handler - Stock error handler for BMDMA controller
2851 * @ap: port to handle error for
2853 * Stock error handler for BMDMA controller. It can handle both
2854 * PATA and SATA controllers. Most BMDMA controllers should be
2855 * able to use this EH as-is or with some added handling before
2859 * Kernel thread context (may sleep)
2861 void ata_bmdma_error_handler(struct ata_port *ap)
2863 struct ata_queued_cmd *qc;
2864 unsigned long flags;
2867 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2868 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2871 /* reset PIO HSM and stop DMA engine */
2872 spin_lock_irqsave(ap->lock, flags);
2874 if (qc && ata_is_dma(qc->tf.protocol)) {
2877 host_stat = ap->ops->bmdma_status(ap);
2879 /* BMDMA controllers indicate host bus error by
2880 * setting DMA_ERR bit and timing out. As it wasn't
2881 * really a timeout event, adjust error mask and
2882 * cancel frozen state.
2884 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
2885 qc->err_mask = AC_ERR_HOST_BUS;
2889 ap->ops->bmdma_stop(qc);
2891 /* if we're gonna thaw, make sure IRQ is clear */
2893 ap->ops->sff_check_status(ap);
2894 if (ap->ops->sff_irq_clear)
2895 ap->ops->sff_irq_clear(ap);
2899 spin_unlock_irqrestore(ap->lock, flags);
2902 ata_eh_thaw_port(ap);
2904 ata_sff_error_handler(ap);
2906 EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
2909 * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA
2910 * @qc: internal command to clean up
2913 * Kernel thread context (may sleep)
2915 void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
2917 struct ata_port *ap = qc->ap;
2918 unsigned long flags;
2920 if (ata_is_dma(qc->tf.protocol)) {
2921 spin_lock_irqsave(ap->lock, flags);
2922 ap->ops->bmdma_stop(qc);
2923 spin_unlock_irqrestore(ap->lock, flags);
2926 EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
2929 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
2930 * @ap: Port associated with this ATA transaction.
2932 * Clear interrupt and error flags in DMA status register.
2934 * May be used as the irq_clear() entry in ata_port_operations.
2937 * spin_lock_irqsave(host lock)
2939 void ata_bmdma_irq_clear(struct ata_port *ap)
2941 void __iomem *mmio = ap->ioaddr.bmdma_addr;
2946 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
2948 EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
2951 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
2952 * @qc: Info associated with this ATA transaction.
2955 * spin_lock_irqsave(host lock)
2957 void ata_bmdma_setup(struct ata_queued_cmd *qc)
2959 struct ata_port *ap = qc->ap;
2960 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
2963 /* load PRD table addr. */
2964 mb(); /* make sure PRD table writes are visible to controller */
2965 iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2967 /* specify data direction, triple-check start bit is clear */
2968 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2969 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
2971 dmactl |= ATA_DMA_WR;
2972 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2974 /* issue r/w command */
2975 ap->ops->sff_exec_command(ap, &qc->tf);
2977 EXPORT_SYMBOL_GPL(ata_bmdma_setup);
2980 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
2981 * @qc: Info associated with this ATA transaction.
2984 * spin_lock_irqsave(host lock)
2986 void ata_bmdma_start(struct ata_queued_cmd *qc)
2988 struct ata_port *ap = qc->ap;
2991 /* start host DMA transaction */
2992 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2993 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2995 /* Strictly, one may wish to issue an ioread8() here, to
2996 * flush the mmio write. However, control also passes
2997 * to the hardware at this point, and it will interrupt
2998 * us when we are to resume control. So, in effect,
2999 * we don't care when the mmio write flushes.
3000 * Further, a read of the DMA status register _immediately_
3001 * following the write may not be what certain flaky hardware
3002 * is expected, so I think it is best to not add a readb()
3003 * without first all the MMIO ATA cards/mobos.
3004 * Or maybe I'm just being paranoid.
3006 * FIXME: The posting of this write means I/O starts are
3007 * unneccessarily delayed for MMIO
3010 EXPORT_SYMBOL_GPL(ata_bmdma_start);
3013 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
3014 * @qc: Command we are ending DMA for
3016 * Clears the ATA_DMA_START flag in the dma control register
3018 * May be used as the bmdma_stop() entry in ata_port_operations.
3021 * spin_lock_irqsave(host lock)
3023 void ata_bmdma_stop(struct ata_queued_cmd *qc)
3025 struct ata_port *ap = qc->ap;
3026 void __iomem *mmio = ap->ioaddr.bmdma_addr;
3028 /* clear start/stop bit */
3029 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
3030 mmio + ATA_DMA_CMD);
3032 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
3033 ata_sff_dma_pause(ap);
3035 EXPORT_SYMBOL_GPL(ata_bmdma_stop);
3038 * ata_bmdma_status - Read PCI IDE BMDMA status
3039 * @ap: Port associated with this ATA transaction.
3041 * Read and return BMDMA status register.
3043 * May be used as the bmdma_status() entry in ata_port_operations.
3046 * spin_lock_irqsave(host lock)
3048 u8 ata_bmdma_status(struct ata_port *ap)
3050 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
3052 EXPORT_SYMBOL_GPL(ata_bmdma_status);
3056 * ata_bmdma_port_start - Set port up for bmdma.
3057 * @ap: Port to initialize
3059 * Called just after data structures for each port are
3060 * initialized. Allocates space for PRD table.
3062 * May be used as the port_start() entry in ata_port_operations.
3065 * Inherited from caller.
3067 int ata_bmdma_port_start(struct ata_port *ap)
3069 if (ap->mwdma_mask || ap->udma_mask) {
3071 dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ,
3072 &ap->bmdma_prd_dma, GFP_KERNEL);
3079 EXPORT_SYMBOL_GPL(ata_bmdma_port_start);
3082 * ata_bmdma_port_start32 - Set port up for dma.
3083 * @ap: Port to initialize
3085 * Called just after data structures for each port are
3086 * initialized. Enables 32bit PIO and allocates space for PRD
3089 * May be used as the port_start() entry in ata_port_operations for
3090 * devices that are capable of 32bit PIO.
3093 * Inherited from caller.
3095 int ata_bmdma_port_start32(struct ata_port *ap)
3097 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
3098 return ata_bmdma_port_start(ap);
3100 EXPORT_SYMBOL_GPL(ata_bmdma_port_start32);
3105 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
3108 * Some PCI ATA devices report simplex mode but in fact can be told to
3109 * enter non simplex mode. This implements the necessary logic to
3110 * perform the task on such devices. Calling it on other devices will
3111 * have -undefined- behaviour.
3113 int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
3115 unsigned long bmdma = pci_resource_start(pdev, 4);
3121 simplex = inb(bmdma + 0x02);
3122 outb(simplex & 0x60, bmdma + 0x02);
3123 simplex = inb(bmdma + 0x02);
3128 EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
3130 static void ata_bmdma_nodma(struct ata_host *host, const char *reason)
3134 dev_printk(KERN_ERR, host->dev, "BMDMA: %s, falling back to PIO\n",
3137 for (i = 0; i < 2; i++) {
3138 host->ports[i]->mwdma_mask = 0;
3139 host->ports[i]->udma_mask = 0;
3144 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
3145 * @host: target ATA host
3147 * Acquire PCI BMDMA resources and initialize @host accordingly.
3150 * Inherited from calling layer (may sleep).
3152 void ata_pci_bmdma_init(struct ata_host *host)
3154 struct device *gdev = host->dev;
3155 struct pci_dev *pdev = to_pci_dev(gdev);
3158 /* No BAR4 allocation: No DMA */
3159 if (pci_resource_start(pdev, 4) == 0) {
3160 ata_bmdma_nodma(host, "BAR4 is zero");
3165 * Some controllers require BMDMA region to be initialized
3166 * even if DMA is not in use to clear IRQ status via
3167 * ->sff_irq_clear method. Try to initialize bmdma_addr
3168 * regardless of dma masks.
3170 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
3172 ata_bmdma_nodma(host, "failed to set dma mask");
3174 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
3176 ata_bmdma_nodma(host,
3177 "failed to set consistent dma mask");
3180 /* request and iomap DMA region */
3181 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
3183 ata_bmdma_nodma(host, "failed to request/iomap BAR4");
3186 host->iomap = pcim_iomap_table(pdev);
3188 for (i = 0; i < 2; i++) {
3189 struct ata_port *ap = host->ports[i];
3190 void __iomem *bmdma = host->iomap[4] + 8 * i;
3192 if (ata_port_is_dummy(ap))
3195 ap->ioaddr.bmdma_addr = bmdma;
3196 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
3197 (ioread8(bmdma + 2) & 0x80))
3198 host->flags |= ATA_HOST_SIMPLEX;
3200 ata_port_desc(ap, "bmdma 0x%llx",
3201 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
3204 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
3207 * ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host
3208 * @pdev: target PCI device
3209 * @ppi: array of port_info, must be enough for two ports
3210 * @r_host: out argument for the initialized ATA host
3212 * Helper to allocate BMDMA ATA host for @pdev, acquire all PCI
3213 * resources and initialize it accordingly in one go.
3216 * Inherited from calling layer (may sleep).
3219 * 0 on success, -errno otherwise.
3221 int ata_pci_bmdma_prepare_host(struct pci_dev *pdev,
3222 const struct ata_port_info * const * ppi,
3223 struct ata_host **r_host)
3227 rc = ata_pci_sff_prepare_host(pdev, ppi, r_host);
3231 ata_pci_bmdma_init(*r_host);
3234 EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host);
3237 * ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller
3238 * @pdev: Controller to be initialized
3239 * @ppi: array of port_info, must be enough for two ports
3240 * @sht: scsi_host_template to use when registering the host
3241 * @host_priv: host private_data
3242 * @hflags: host flags
3244 * This function is similar to ata_pci_sff_init_one() but also
3245 * takes care of BMDMA initialization.
3248 * Inherited from PCI layer (may sleep).
3251 * Zero on success, negative on errno-based value on error.
3253 int ata_pci_bmdma_init_one(struct pci_dev *pdev,
3254 const struct ata_port_info * const * ppi,
3255 struct scsi_host_template *sht, void *host_priv,
3258 struct device *dev = &pdev->dev;
3259 const struct ata_port_info *pi;
3260 struct ata_host *host = NULL;
3265 pi = ata_sff_find_valid_pi(ppi);
3267 dev_printk(KERN_ERR, &pdev->dev,
3268 "no valid port_info specified\n");
3272 if (!devres_open_group(dev, NULL, GFP_KERNEL))
3275 rc = pcim_enable_device(pdev);
3279 /* prepare and activate BMDMA host */
3280 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
3283 host->private_data = host_priv;
3284 host->flags |= hflags;
3286 pci_set_master(pdev);
3287 rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
3290 devres_remove_group(&pdev->dev, NULL);
3292 devres_release_group(&pdev->dev, NULL);
3296 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one);
3298 #endif /* CONFIG_PCI */
3299 #endif /* CONFIG_ATA_BMDMA */
3302 * ata_sff_port_init - Initialize SFF/BMDMA ATA port
3303 * @ap: Port to initialize
3305 * Called on port allocation to initialize SFF/BMDMA specific
3311 void ata_sff_port_init(struct ata_port *ap)
3313 INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task);
3314 ap->ctl = ATA_DEVCTL_OBS;
3315 ap->last_ctl = 0xFF;
3318 int __init ata_sff_init(void)
3320 ata_sff_wq = alloc_workqueue("ata_sff", WQ_RESCUER, WQ_MAX_ACTIVE);
3327 void __exit ata_sff_exit(void)
3329 destroy_workqueue(ata_sff_wq);