2 * File: drivers/ata/pata_bf54x.c
3 * Author: Sonic Zhang <sonic.zhang@analog.com>
6 * Description: PATA Driver for blackfin 54x
9 * Copyright 2007 Analog Devices Inc.
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, see the file COPYING, or write
25 * to the Free Software Foundation, Inc.,
26 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/init.h>
33 #include <linux/blkdev.h>
34 #include <linux/delay.h>
35 #include <linux/device.h>
36 #include <scsi/scsi_host.h>
37 #include <linux/libata.h>
38 #include <linux/platform_device.h>
41 #include <asm/portmux.h>
43 #define DRV_NAME "pata-bf54x"
44 #define DRV_VERSION "0.9"
46 #define ATA_REG_CTRL 0x0E
47 #define ATA_REG_ALTSTATUS ATA_REG_CTRL
49 /* These are the offset of the controller's registers */
50 #define ATAPI_OFFSET_CONTROL 0x00
51 #define ATAPI_OFFSET_STATUS 0x04
52 #define ATAPI_OFFSET_DEV_ADDR 0x08
53 #define ATAPI_OFFSET_DEV_TXBUF 0x0c
54 #define ATAPI_OFFSET_DEV_RXBUF 0x10
55 #define ATAPI_OFFSET_INT_MASK 0x14
56 #define ATAPI_OFFSET_INT_STATUS 0x18
57 #define ATAPI_OFFSET_XFER_LEN 0x1c
58 #define ATAPI_OFFSET_LINE_STATUS 0x20
59 #define ATAPI_OFFSET_SM_STATE 0x24
60 #define ATAPI_OFFSET_TERMINATE 0x28
61 #define ATAPI_OFFSET_PIO_TFRCNT 0x2c
62 #define ATAPI_OFFSET_DMA_TFRCNT 0x30
63 #define ATAPI_OFFSET_UMAIN_TFRCNT 0x34
64 #define ATAPI_OFFSET_UDMAOUT_TFRCNT 0x38
65 #define ATAPI_OFFSET_REG_TIM_0 0x40
66 #define ATAPI_OFFSET_PIO_TIM_0 0x44
67 #define ATAPI_OFFSET_PIO_TIM_1 0x48
68 #define ATAPI_OFFSET_MULTI_TIM_0 0x50
69 #define ATAPI_OFFSET_MULTI_TIM_1 0x54
70 #define ATAPI_OFFSET_MULTI_TIM_2 0x58
71 #define ATAPI_OFFSET_ULTRA_TIM_0 0x60
72 #define ATAPI_OFFSET_ULTRA_TIM_1 0x64
73 #define ATAPI_OFFSET_ULTRA_TIM_2 0x68
74 #define ATAPI_OFFSET_ULTRA_TIM_3 0x6c
77 #define ATAPI_GET_CONTROL(base)\
78 bfin_read16(base + ATAPI_OFFSET_CONTROL)
79 #define ATAPI_SET_CONTROL(base, val)\
80 bfin_write16(base + ATAPI_OFFSET_CONTROL, val)
81 #define ATAPI_GET_STATUS(base)\
82 bfin_read16(base + ATAPI_OFFSET_STATUS)
83 #define ATAPI_GET_DEV_ADDR(base)\
84 bfin_read16(base + ATAPI_OFFSET_DEV_ADDR)
85 #define ATAPI_SET_DEV_ADDR(base, val)\
86 bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val)
87 #define ATAPI_GET_DEV_TXBUF(base)\
88 bfin_read16(base + ATAPI_OFFSET_DEV_TXBUF)
89 #define ATAPI_SET_DEV_TXBUF(base, val)\
90 bfin_write16(base + ATAPI_OFFSET_DEV_TXBUF, val)
91 #define ATAPI_GET_DEV_RXBUF(base)\
92 bfin_read16(base + ATAPI_OFFSET_DEV_RXBUF)
93 #define ATAPI_SET_DEV_RXBUF(base, val)\
94 bfin_write16(base + ATAPI_OFFSET_DEV_RXBUF, val)
95 #define ATAPI_GET_INT_MASK(base)\
96 bfin_read16(base + ATAPI_OFFSET_INT_MASK)
97 #define ATAPI_SET_INT_MASK(base, val)\
98 bfin_write16(base + ATAPI_OFFSET_INT_MASK, val)
99 #define ATAPI_GET_INT_STATUS(base)\
100 bfin_read16(base + ATAPI_OFFSET_INT_STATUS)
101 #define ATAPI_SET_INT_STATUS(base, val)\
102 bfin_write16(base + ATAPI_OFFSET_INT_STATUS, val)
103 #define ATAPI_GET_XFER_LEN(base)\
104 bfin_read16(base + ATAPI_OFFSET_XFER_LEN)
105 #define ATAPI_SET_XFER_LEN(base, val)\
106 bfin_write16(base + ATAPI_OFFSET_XFER_LEN, val)
107 #define ATAPI_GET_LINE_STATUS(base)\
108 bfin_read16(base + ATAPI_OFFSET_LINE_STATUS)
109 #define ATAPI_GET_SM_STATE(base)\
110 bfin_read16(base + ATAPI_OFFSET_SM_STATE)
111 #define ATAPI_GET_TERMINATE(base)\
112 bfin_read16(base + ATAPI_OFFSET_TERMINATE)
113 #define ATAPI_SET_TERMINATE(base, val)\
114 bfin_write16(base + ATAPI_OFFSET_TERMINATE, val)
115 #define ATAPI_GET_PIO_TFRCNT(base)\
116 bfin_read16(base + ATAPI_OFFSET_PIO_TFRCNT)
117 #define ATAPI_GET_DMA_TFRCNT(base)\
118 bfin_read16(base + ATAPI_OFFSET_DMA_TFRCNT)
119 #define ATAPI_GET_UMAIN_TFRCNT(base)\
120 bfin_read16(base + ATAPI_OFFSET_UMAIN_TFRCNT)
121 #define ATAPI_GET_UDMAOUT_TFRCNT(base)\
122 bfin_read16(base + ATAPI_OFFSET_UDMAOUT_TFRCNT)
123 #define ATAPI_GET_REG_TIM_0(base)\
124 bfin_read16(base + ATAPI_OFFSET_REG_TIM_0)
125 #define ATAPI_SET_REG_TIM_0(base, val)\
126 bfin_write16(base + ATAPI_OFFSET_REG_TIM_0, val)
127 #define ATAPI_GET_PIO_TIM_0(base)\
128 bfin_read16(base + ATAPI_OFFSET_PIO_TIM_0)
129 #define ATAPI_SET_PIO_TIM_0(base, val)\
130 bfin_write16(base + ATAPI_OFFSET_PIO_TIM_0, val)
131 #define ATAPI_GET_PIO_TIM_1(base)\
132 bfin_read16(base + ATAPI_OFFSET_PIO_TIM_1)
133 #define ATAPI_SET_PIO_TIM_1(base, val)\
134 bfin_write16(base + ATAPI_OFFSET_PIO_TIM_1, val)
135 #define ATAPI_GET_MULTI_TIM_0(base)\
136 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_0)
137 #define ATAPI_SET_MULTI_TIM_0(base, val)\
138 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_0, val)
139 #define ATAPI_GET_MULTI_TIM_1(base)\
140 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_1)
141 #define ATAPI_SET_MULTI_TIM_1(base, val)\
142 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_1, val)
143 #define ATAPI_GET_MULTI_TIM_2(base)\
144 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_2)
145 #define ATAPI_SET_MULTI_TIM_2(base, val)\
146 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_2, val)
147 #define ATAPI_GET_ULTRA_TIM_0(base)\
148 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_0)
149 #define ATAPI_SET_ULTRA_TIM_0(base, val)\
150 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_0, val)
151 #define ATAPI_GET_ULTRA_TIM_1(base)\
152 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_1)
153 #define ATAPI_SET_ULTRA_TIM_1(base, val)\
154 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_1, val)
155 #define ATAPI_GET_ULTRA_TIM_2(base)\
156 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_2)
157 #define ATAPI_SET_ULTRA_TIM_2(base, val)\
158 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_2, val)
159 #define ATAPI_GET_ULTRA_TIM_3(base)\
160 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_3)
161 #define ATAPI_SET_ULTRA_TIM_3(base, val)\
162 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_3, val)
165 * PIO Mode - Frequency compatibility
167 /* mode: 0 1 2 3 4 */
168 static const u32 pio_fsclk[] =
169 { 33333333, 33333333, 33333333, 33333333, 33333333 };
172 * MDMA Mode - Frequency compatibility
175 static const u32 mdma_fsclk[] = { 33333333, 33333333, 33333333 };
178 * UDMA Mode - Frequency compatibility
180 * UDMA5 - 100 MB/s - SCLK = 133 MHz
181 * UDMA4 - 66 MB/s - SCLK >= 80 MHz
182 * UDMA3 - 44.4 MB/s - SCLK >= 50 MHz
183 * UDMA2 - 33 MB/s - SCLK >= 40 MHz
185 /* mode: 0 1 2 3 4 5 */
186 static const u32 udma_fsclk[] =
187 { 33333333, 33333333, 40000000, 50000000, 80000000, 133333333 };
190 * Register transfer timing table
192 /* mode: 0 1 2 3 4 */
194 static const u32 reg_t0min[] = { 600, 383, 330, 180, 120 };
195 /* DIOR/DIOW to end cycle */
196 static const u32 reg_t2min[] = { 290, 290, 290, 70, 25 };
197 /* DIOR/DIOW asserted pulse width */
198 static const u32 reg_teocmin[] = { 290, 290, 290, 80, 70 };
203 /* mode: 0 1 2 3 4 */
205 static const u32 pio_t0min[] = { 600, 383, 240, 180, 120 };
206 /* Address valid to DIOR/DIORW */
207 static const u32 pio_t1min[] = { 70, 50, 30, 30, 25 };
208 /* DIOR/DIOW to end cycle */
209 static const u32 pio_t2min[] = { 165, 125, 100, 80, 70 };
210 /* DIOR/DIOW asserted pulse width */
211 static const u32 pio_teocmin[] = { 165, 125, 100, 70, 25 };
213 static const u32 pio_t4min[] = { 30, 20, 15, 10, 10 };
215 /* ******************************************************************
216 * Multiword DMA timing table
217 * ******************************************************************
221 static const u32 mdma_t0min[] = { 480, 150, 120 };
222 /* DIOR/DIOW asserted pulse width */
223 static const u32 mdma_tdmin[] = { 215, 80, 70 };
224 /* DMACK to read data released */
225 static const u32 mdma_thmin[] = { 20, 15, 10 };
226 /* DIOR/DIOW to DMACK hold */
227 static const u32 mdma_tjmin[] = { 20, 5, 5 };
228 /* DIOR negated pulse width */
229 static const u32 mdma_tkrmin[] = { 50, 50, 25 };
230 /* DIOR negated pulse width */
231 static const u32 mdma_tkwmin[] = { 215, 50, 25 };
232 /* CS[1:0] valid to DIOR/DIOW */
233 static const u32 mdma_tmmin[] = { 50, 30, 25 };
234 /* DMACK to read data released */
235 static const u32 mdma_tzmax[] = { 20, 25, 25 };
238 * Ultra DMA timing table
240 /* mode: 0 1 2 3 4 5 */
241 static const u32 udma_tcycmin[] = { 112, 73, 54, 39, 25, 17 };
242 static const u32 udma_tdvsmin[] = { 70, 48, 31, 20, 7, 5 };
243 static const u32 udma_tenvmax[] = { 70, 70, 70, 55, 55, 50 };
244 static const u32 udma_trpmin[] = { 160, 125, 100, 100, 100, 85 };
245 static const u32 udma_tmin[] = { 5, 5, 5, 5, 3, 3 };
248 static const u32 udma_tmlimin = 20;
249 static const u32 udma_tzahmin = 20;
250 static const u32 udma_tenvmin = 20;
251 static const u32 udma_tackmin = 20;
252 static const u32 udma_tssmin = 50;
256 * Function: num_clocks_min
259 * calculate number of SCLK cycles to meet minimum timing
261 static unsigned short num_clocks_min(unsigned long tmin,
265 unsigned short result;
267 tmp = tmin * (fsclk/1000/1000) / 1000;
268 result = (unsigned short)tmp;
269 if ((tmp*1000*1000) < (tmin*(fsclk/1000))) {
277 * bfin_set_piomode - Initialize host controller PATA PIO timings
278 * @ap: Port whose timings we are configuring
281 * Set PIO mode for device.
284 * None (inherited from caller).
287 static void bfin_set_piomode(struct ata_port *ap, struct ata_device *adev)
289 int mode = adev->pio_mode - XFER_PIO_0;
290 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
291 unsigned int fsclk = get_sclk();
292 unsigned short teoc_reg, t2_reg, teoc_pio;
293 unsigned short t4_reg, t2_pio, t1_reg;
294 unsigned short n0, n6, t6min = 5;
296 /* the most restrictive timing value is t6 and tc, the DIOW - data hold
297 * If one SCLK pulse is longer than this minimum value then register
298 * transfers cannot be supported at this frequency.
300 n6 = num_clocks_min(t6min, fsclk);
301 if (mode >= 0 && mode <= 4 && n6 >= 1) {
302 dev_dbg(adev->link->ap->dev, "set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
303 /* calculate the timing values for register transfers. */
304 while (mode > 0 && pio_fsclk[mode] > fsclk)
307 /* DIOR/DIOW to end cycle time */
308 t2_reg = num_clocks_min(reg_t2min[mode], fsclk);
309 /* DIOR/DIOW asserted pulse width */
310 teoc_reg = num_clocks_min(reg_teocmin[mode], fsclk);
312 n0 = num_clocks_min(reg_t0min[mode], fsclk);
314 /* increase t2 until we meed the minimum cycle length */
315 if (t2_reg + teoc_reg < n0)
316 t2_reg = n0 - teoc_reg;
318 /* calculate the timing values for pio transfers. */
320 /* DIOR/DIOW to end cycle time */
321 t2_pio = num_clocks_min(pio_t2min[mode], fsclk);
322 /* DIOR/DIOW asserted pulse width */
323 teoc_pio = num_clocks_min(pio_teocmin[mode], fsclk);
325 n0 = num_clocks_min(pio_t0min[mode], fsclk);
327 /* increase t2 until we meed the minimum cycle length */
328 if (t2_pio + teoc_pio < n0)
329 t2_pio = n0 - teoc_pio;
331 /* Address valid to DIOR/DIORW */
332 t1_reg = num_clocks_min(pio_t1min[mode], fsclk);
335 t4_reg = num_clocks_min(pio_t4min[mode], fsclk);
337 ATAPI_SET_REG_TIM_0(base, (teoc_reg<<8 | t2_reg));
338 ATAPI_SET_PIO_TIM_0(base, (t4_reg<<12 | t2_pio<<4 | t1_reg));
339 ATAPI_SET_PIO_TIM_1(base, teoc_pio);
341 ATAPI_SET_CONTROL(base,
342 ATAPI_GET_CONTROL(base) | IORDY_EN);
344 ATAPI_SET_CONTROL(base,
345 ATAPI_GET_CONTROL(base) & ~IORDY_EN);
348 /* Disable host ATAPI PIO interrupts */
349 ATAPI_SET_INT_MASK(base, ATAPI_GET_INT_MASK(base)
350 & ~(PIO_DONE_MASK | HOST_TERM_XFER_MASK));
356 * bfin_set_dmamode - Initialize host controller PATA DMA timings
357 * @ap: Port whose timings we are configuring
360 * Set UDMA mode for device.
363 * None (inherited from caller).
366 static void bfin_set_dmamode(struct ata_port *ap, struct ata_device *adev)
369 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
370 unsigned long fsclk = get_sclk();
371 unsigned short tenv, tack, tcyc_tdvs, tdvs, tmli, tss, trp, tzah;
372 unsigned short tm, td, tkr, tkw, teoc, th;
373 unsigned short n0, nf, tfmin = 5;
374 unsigned short nmin, tcyc;
376 mode = adev->dma_mode - XFER_UDMA_0;
377 if (mode >= 0 && mode <= 5) {
378 dev_dbg(adev->link->ap->dev, "set udmamode: mode=%d\n", mode);
379 /* the most restrictive timing value is t6 and tc,
380 * the DIOW - data hold. If one SCLK pulse is longer
381 * than this minimum value then register
382 * transfers cannot be supported at this frequency.
384 while (mode > 0 && udma_fsclk[mode] > fsclk)
387 nmin = num_clocks_min(udma_tmin[mode], fsclk);
389 /* calculate the timing values for Ultra DMA. */
390 tdvs = num_clocks_min(udma_tdvsmin[mode], fsclk);
391 tcyc = num_clocks_min(udma_tcycmin[mode], fsclk);
394 /* increase tcyc - tdvs (tcyc_tdvs) until we meed
395 * the minimum cycle length
397 if (tdvs + tcyc_tdvs < tcyc)
398 tcyc_tdvs = tcyc - tdvs;
400 /* Mow assign the values required for the timing
409 tack = num_clocks_min(udma_tackmin, fsclk);
410 tss = num_clocks_min(udma_tssmin, fsclk);
411 tmli = num_clocks_min(udma_tmlimin, fsclk);
412 tzah = num_clocks_min(udma_tzahmin, fsclk);
413 trp = num_clocks_min(udma_trpmin[mode], fsclk);
414 tenv = num_clocks_min(udma_tenvmin, fsclk);
415 if (tenv <= udma_tenvmax[mode]) {
416 ATAPI_SET_ULTRA_TIM_0(base, (tenv<<8 | tack));
417 ATAPI_SET_ULTRA_TIM_1(base,
418 (tcyc_tdvs<<8 | tdvs));
419 ATAPI_SET_ULTRA_TIM_2(base, (tmli<<8 | tss));
420 ATAPI_SET_ULTRA_TIM_3(base, (trp<<8 | tzah));
425 mode = adev->dma_mode - XFER_MW_DMA_0;
426 if (mode >= 0 && mode <= 2) {
427 dev_dbg(adev->link->ap->dev, "set mdmamode: mode=%d\n", mode);
428 /* the most restrictive timing value is tf, the DMACK to
429 * read data released. If one SCLK pulse is longer than
430 * this maximum value then the MDMA mode
431 * cannot be supported at this frequency.
433 while (mode > 0 && mdma_fsclk[mode] > fsclk)
436 nf = num_clocks_min(tfmin, fsclk);
438 /* calculate the timing values for Multi-word DMA. */
440 /* DIOR/DIOW asserted pulse width */
441 td = num_clocks_min(mdma_tdmin[mode], fsclk);
443 /* DIOR negated pulse width */
444 tkw = num_clocks_min(mdma_tkwmin[mode], fsclk);
447 n0 = num_clocks_min(mdma_t0min[mode], fsclk);
449 /* increase tk until we meed the minimum cycle length */
453 /* DIOR negated pulse width - read */
454 tkr = num_clocks_min(mdma_tkrmin[mode], fsclk);
455 /* CS{1:0] valid to DIOR/DIOW */
456 tm = num_clocks_min(mdma_tmmin[mode], fsclk);
457 /* DIOR/DIOW to DMACK hold */
458 teoc = num_clocks_min(mdma_tjmin[mode], fsclk);
460 th = num_clocks_min(mdma_thmin[mode], fsclk);
462 ATAPI_SET_MULTI_TIM_0(base, (tm<<8 | td));
463 ATAPI_SET_MULTI_TIM_1(base, (tkr<<8 | tkw));
464 ATAPI_SET_MULTI_TIM_2(base, (teoc<<8 | th));
473 * Function: wait_complete
475 * Description: Waits the interrupt from device
478 static inline void wait_complete(void __iomem *base, unsigned short mask)
480 unsigned short status;
483 #define PATA_BF54X_WAIT_TIMEOUT 10000
485 for (i = 0; i < PATA_BF54X_WAIT_TIMEOUT; i++) {
486 status = ATAPI_GET_INT_STATUS(base) & mask;
491 ATAPI_SET_INT_STATUS(base, mask);
496 * Function: write_atapi_register
498 * Description: Writes to ATA Device Resgister
502 static void write_atapi_register(void __iomem *base,
503 unsigned long ata_reg, unsigned short value)
505 /* Program the ATA_DEV_TXBUF register with write data (to be
506 * written into the device).
508 ATAPI_SET_DEV_TXBUF(base, value);
510 /* Program the ATA_DEV_ADDR register with address of the
511 * device register (0x01 to 0x0F).
513 ATAPI_SET_DEV_ADDR(base, ata_reg);
515 /* Program the ATA_CTRL register with dir set to write (1)
517 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
519 /* ensure PIO DMA is not set */
520 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
522 /* and start the transfer */
523 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
525 /* Wait for the interrupt to indicate the end of the transfer.
526 * (We need to wait on and clear rhe ATA_DEV_INT interrupt status)
528 wait_complete(base, PIO_DONE_INT);
533 * Function: read_atapi_register
535 *Description: Reads from ATA Device Resgister
539 static unsigned short read_atapi_register(void __iomem *base,
540 unsigned long ata_reg)
542 /* Program the ATA_DEV_ADDR register with address of the
543 * device register (0x01 to 0x0F).
545 ATAPI_SET_DEV_ADDR(base, ata_reg);
547 /* Program the ATA_CTRL register with dir set to read (0) and
549 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
551 /* ensure PIO DMA is not set */
552 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
554 /* and start the transfer */
555 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
557 /* Wait for the interrupt to indicate the end of the transfer.
558 * (PIO_DONE interrupt is set and it doesn't seem to matter
559 * that we don't clear it)
561 wait_complete(base, PIO_DONE_INT);
563 /* Read the ATA_DEV_RXBUF register with write data (to be
564 * written into the device).
566 return ATAPI_GET_DEV_RXBUF(base);
571 * Function: write_atapi_register_data
573 * Description: Writes to ATA Device Resgister
577 static void write_atapi_data(void __iomem *base,
578 int len, unsigned short *buf)
582 /* Set transfer length to 1 */
583 ATAPI_SET_XFER_LEN(base, 1);
585 /* Program the ATA_DEV_ADDR register with address of the
588 ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
590 /* Program the ATA_CTRL register with dir set to write (1)
592 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
594 /* ensure PIO DMA is not set */
595 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
597 for (i = 0; i < len; i++) {
598 /* Program the ATA_DEV_TXBUF register with write data (to be
599 * written into the device).
601 ATAPI_SET_DEV_TXBUF(base, buf[i]);
603 /* and start the transfer */
604 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
606 /* Wait for the interrupt to indicate the end of the transfer.
607 * (We need to wait on and clear rhe ATA_DEV_INT
610 wait_complete(base, PIO_DONE_INT);
616 * Function: read_atapi_register_data
618 * Description: Reads from ATA Device Resgister
622 static void read_atapi_data(void __iomem *base,
623 int len, unsigned short *buf)
627 /* Set transfer length to 1 */
628 ATAPI_SET_XFER_LEN(base, 1);
630 /* Program the ATA_DEV_ADDR register with address of the
633 ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
635 /* Program the ATA_CTRL register with dir set to read (0) and
637 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
639 /* ensure PIO DMA is not set */
640 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
642 for (i = 0; i < len; i++) {
643 /* and start the transfer */
644 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
646 /* Wait for the interrupt to indicate the end of the transfer.
647 * (PIO_DONE interrupt is set and it doesn't seem to matter
648 * that we don't clear it)
650 wait_complete(base, PIO_DONE_INT);
652 /* Read the ATA_DEV_RXBUF register with write data (to be
653 * written into the device).
655 buf[i] = ATAPI_GET_DEV_RXBUF(base);
660 * bfin_tf_load - send taskfile registers to host controller
661 * @ap: Port to which output is sent
662 * @tf: ATA taskfile register set
664 * Note: Original code is ata_sff_tf_load().
667 static void bfin_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
669 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
670 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
672 if (tf->ctl != ap->last_ctl) {
673 write_atapi_register(base, ATA_REG_CTRL, tf->ctl);
674 ap->last_ctl = tf->ctl;
679 if (tf->flags & ATA_TFLAG_LBA48) {
680 write_atapi_register(base, ATA_REG_FEATURE,
682 write_atapi_register(base, ATA_REG_NSECT,
684 write_atapi_register(base, ATA_REG_LBAL, tf->hob_lbal);
685 write_atapi_register(base, ATA_REG_LBAM, tf->hob_lbam);
686 write_atapi_register(base, ATA_REG_LBAH, tf->hob_lbah);
687 dev_dbg(ap->dev, "hob: feat 0x%X nsect 0x%X, lba 0x%X "
696 write_atapi_register(base, ATA_REG_FEATURE, tf->feature);
697 write_atapi_register(base, ATA_REG_NSECT, tf->nsect);
698 write_atapi_register(base, ATA_REG_LBAL, tf->lbal);
699 write_atapi_register(base, ATA_REG_LBAM, tf->lbam);
700 write_atapi_register(base, ATA_REG_LBAH, tf->lbah);
701 dev_dbg(ap->dev, "feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
709 if (tf->flags & ATA_TFLAG_DEVICE) {
710 write_atapi_register(base, ATA_REG_DEVICE, tf->device);
711 dev_dbg(ap->dev, "device 0x%X\n", tf->device);
718 * bfin_check_status - Read device status reg & clear interrupt
719 * @ap: port where the device is
721 * Note: Original code is ata_check_status().
724 static u8 bfin_check_status(struct ata_port *ap)
726 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
727 return read_atapi_register(base, ATA_REG_STATUS);
731 * bfin_tf_read - input device's ATA taskfile shadow registers
732 * @ap: Port from which input is read
733 * @tf: ATA taskfile register set for storing input
735 * Note: Original code is ata_sff_tf_read().
738 static void bfin_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
740 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
742 tf->command = bfin_check_status(ap);
743 tf->feature = read_atapi_register(base, ATA_REG_ERR);
744 tf->nsect = read_atapi_register(base, ATA_REG_NSECT);
745 tf->lbal = read_atapi_register(base, ATA_REG_LBAL);
746 tf->lbam = read_atapi_register(base, ATA_REG_LBAM);
747 tf->lbah = read_atapi_register(base, ATA_REG_LBAH);
748 tf->device = read_atapi_register(base, ATA_REG_DEVICE);
750 if (tf->flags & ATA_TFLAG_LBA48) {
751 write_atapi_register(base, ATA_REG_CTRL, tf->ctl | ATA_HOB);
752 tf->hob_feature = read_atapi_register(base, ATA_REG_ERR);
753 tf->hob_nsect = read_atapi_register(base, ATA_REG_NSECT);
754 tf->hob_lbal = read_atapi_register(base, ATA_REG_LBAL);
755 tf->hob_lbam = read_atapi_register(base, ATA_REG_LBAM);
756 tf->hob_lbah = read_atapi_register(base, ATA_REG_LBAH);
761 * bfin_exec_command - issue ATA command to host controller
762 * @ap: port to which command is being issued
763 * @tf: ATA taskfile register set
765 * Note: Original code is ata_sff_exec_command().
768 static void bfin_exec_command(struct ata_port *ap,
769 const struct ata_taskfile *tf)
771 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
772 dev_dbg(ap->dev, "ata%u: cmd 0x%X\n", ap->print_id, tf->command);
774 write_atapi_register(base, ATA_REG_CMD, tf->command);
779 * bfin_check_altstatus - Read device alternate status reg
780 * @ap: port where the device is
783 static u8 bfin_check_altstatus(struct ata_port *ap)
785 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
786 return read_atapi_register(base, ATA_REG_ALTSTATUS);
790 * bfin_dev_select - Select device 0/1 on ATA bus
791 * @ap: ATA channel to manipulate
792 * @device: ATA device (numbered from zero) to select
794 * Note: Original code is ata_sff_dev_select().
797 static void bfin_dev_select(struct ata_port *ap, unsigned int device)
799 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
803 tmp = ATA_DEVICE_OBS;
805 tmp = ATA_DEVICE_OBS | ATA_DEV1;
807 write_atapi_register(base, ATA_REG_DEVICE, tmp);
812 * bfin_set_devctl - Write device control reg
813 * @ap: port where the device is
814 * @ctl: value to write
817 static void bfin_set_devctl(struct ata_port *ap, u8 ctl)
819 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
820 write_atapi_register(base, ATA_REG_CTRL, ctl);
824 * bfin_bmdma_setup - Set up IDE DMA transaction
825 * @qc: Info associated with this ATA transaction.
827 * Note: Original code is ata_bmdma_setup().
830 static void bfin_bmdma_setup(struct ata_queued_cmd *qc)
832 unsigned short config = WDSIZE_16;
833 struct scatterlist *sg;
836 dev_dbg(qc->ap->dev, "in atapi dma setup\n");
837 /* Program the ATA_CTRL register with dir */
838 if (qc->tf.flags & ATA_TFLAG_WRITE) {
839 /* fill the ATAPI DMA controller */
840 set_dma_config(CH_ATAPI_TX, config);
841 set_dma_x_modify(CH_ATAPI_TX, 2);
842 for_each_sg(qc->sg, sg, qc->n_elem, si) {
843 set_dma_start_addr(CH_ATAPI_TX, sg_dma_address(sg));
844 set_dma_x_count(CH_ATAPI_TX, sg_dma_len(sg) >> 1);
848 /* fill the ATAPI DMA controller */
849 set_dma_config(CH_ATAPI_RX, config);
850 set_dma_x_modify(CH_ATAPI_RX, 2);
851 for_each_sg(qc->sg, sg, qc->n_elem, si) {
852 set_dma_start_addr(CH_ATAPI_RX, sg_dma_address(sg));
853 set_dma_x_count(CH_ATAPI_RX, sg_dma_len(sg) >> 1);
859 * bfin_bmdma_start - Start an IDE DMA transaction
860 * @qc: Info associated with this ATA transaction.
862 * Note: Original code is ata_bmdma_start().
865 static void bfin_bmdma_start(struct ata_queued_cmd *qc)
867 struct ata_port *ap = qc->ap;
868 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
869 struct scatterlist *sg;
872 dev_dbg(qc->ap->dev, "in atapi dma start\n");
873 if (!(ap->udma_mask || ap->mwdma_mask))
876 /* start ATAPI DMA controller*/
877 if (qc->tf.flags & ATA_TFLAG_WRITE) {
879 * On blackfin arch, uncacheable memory is not
880 * allocated with flag GFP_DMA. DMA buffer from
881 * common kenel code should be flushed if WB
882 * data cache is enabled. Otherwise, this loop
883 * is an empty loop and optimized out.
885 for_each_sg(qc->sg, sg, qc->n_elem, si) {
886 flush_dcache_range(sg_dma_address(sg),
887 sg_dma_address(sg) + sg_dma_len(sg));
889 enable_dma(CH_ATAPI_TX);
890 dev_dbg(qc->ap->dev, "enable udma write\n");
892 /* Send ATA DMA write command */
893 bfin_exec_command(ap, &qc->tf);
895 /* set ATA DMA write direction */
896 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base)
899 enable_dma(CH_ATAPI_RX);
900 dev_dbg(qc->ap->dev, "enable udma read\n");
902 /* Send ATA DMA read command */
903 bfin_exec_command(ap, &qc->tf);
905 /* set ATA DMA read direction */
906 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base)
910 /* Reset all transfer count */
911 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | TFRCNT_RST);
913 /* Set ATAPI state machine contorl in terminate sequence */
914 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | END_ON_TERM);
916 /* Set transfer length to buffer len */
917 for_each_sg(qc->sg, sg, qc->n_elem, si) {
918 ATAPI_SET_XFER_LEN(base, (sg_dma_len(sg) >> 1));
921 /* Enable ATA DMA operation*/
923 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base)
926 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base)
931 * bfin_bmdma_stop - Stop IDE DMA transfer
932 * @qc: Command we are ending DMA for
935 static void bfin_bmdma_stop(struct ata_queued_cmd *qc)
937 struct ata_port *ap = qc->ap;
938 struct scatterlist *sg;
941 dev_dbg(qc->ap->dev, "in atapi dma stop\n");
942 if (!(ap->udma_mask || ap->mwdma_mask))
945 /* stop ATAPI DMA controller*/
946 if (qc->tf.flags & ATA_TFLAG_WRITE)
947 disable_dma(CH_ATAPI_TX);
949 disable_dma(CH_ATAPI_RX);
950 if (ap->hsm_task_state & HSM_ST_LAST) {
952 * On blackfin arch, uncacheable memory is not
953 * allocated with flag GFP_DMA. DMA buffer from
954 * common kenel code should be invalidated if
955 * data cache is enabled. Otherwise, this loop
956 * is an empty loop and optimized out.
958 for_each_sg(qc->sg, sg, qc->n_elem, si) {
959 invalidate_dcache_range(
969 * bfin_devchk - PATA device presence detection
970 * @ap: ATA channel to examine
971 * @device: Device to examine (starting at zero)
973 * Note: Original code is ata_devchk().
976 static unsigned int bfin_devchk(struct ata_port *ap,
979 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
982 bfin_dev_select(ap, device);
984 write_atapi_register(base, ATA_REG_NSECT, 0x55);
985 write_atapi_register(base, ATA_REG_LBAL, 0xaa);
987 write_atapi_register(base, ATA_REG_NSECT, 0xaa);
988 write_atapi_register(base, ATA_REG_LBAL, 0x55);
990 write_atapi_register(base, ATA_REG_NSECT, 0x55);
991 write_atapi_register(base, ATA_REG_LBAL, 0xaa);
993 nsect = read_atapi_register(base, ATA_REG_NSECT);
994 lbal = read_atapi_register(base, ATA_REG_LBAL);
996 if ((nsect == 0x55) && (lbal == 0xaa))
997 return 1; /* we found a device */
999 return 0; /* nothing found */
1003 * bfin_bus_post_reset - PATA device post reset
1005 * Note: Original code is ata_bus_post_reset().
1008 static void bfin_bus_post_reset(struct ata_port *ap, unsigned int devmask)
1010 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1011 unsigned int dev0 = devmask & (1 << 0);
1012 unsigned int dev1 = devmask & (1 << 1);
1013 unsigned long deadline;
1015 /* if device 0 was found in ata_devchk, wait for its
1019 ata_sff_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1021 /* if device 1 was found in ata_devchk, wait for
1022 * register access, then wait for BSY to clear
1024 deadline = ata_deadline(jiffies, ATA_TMOUT_BOOT);
1028 bfin_dev_select(ap, 1);
1029 nsect = read_atapi_register(base, ATA_REG_NSECT);
1030 lbal = read_atapi_register(base, ATA_REG_LBAL);
1031 if ((nsect == 1) && (lbal == 1))
1033 if (time_after(jiffies, deadline)) {
1037 ata_msleep(ap, 50); /* give drive a breather */
1040 ata_sff_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1042 /* is all this really necessary? */
1043 bfin_dev_select(ap, 0);
1045 bfin_dev_select(ap, 1);
1047 bfin_dev_select(ap, 0);
1051 * bfin_bus_softreset - PATA device software reset
1053 * Note: Original code is ata_bus_softreset().
1056 static unsigned int bfin_bus_softreset(struct ata_port *ap,
1057 unsigned int devmask)
1059 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1061 /* software reset. causes dev0 to be selected */
1062 write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
1064 write_atapi_register(base, ATA_REG_CTRL, ap->ctl | ATA_SRST);
1066 write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
1068 /* spec mandates ">= 2ms" before checking status.
1069 * We wait 150ms, because that was the magic delay used for
1070 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1071 * between when the ATA command register is written, and then
1072 * status is checked. Because waiting for "a while" before
1073 * checking status is fine, post SRST, we perform this magic
1074 * delay here as well.
1076 * Old drivers/ide uses the 2mS rule and then waits for ready
1078 ata_msleep(ap, 150);
1080 /* Before we perform post reset processing we want to see if
1081 * the bus shows 0xFF because the odd clown forgets the D7
1082 * pulldown resistor.
1084 if (bfin_check_status(ap) == 0xFF)
1087 bfin_bus_post_reset(ap, devmask);
1093 * bfin_softreset - reset host port via ATA SRST
1094 * @ap: port to reset
1095 * @classes: resulting classes of attached devices
1097 * Note: Original code is ata_sff_softreset().
1100 static int bfin_softreset(struct ata_link *link, unsigned int *classes,
1101 unsigned long deadline)
1103 struct ata_port *ap = link->ap;
1104 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1105 unsigned int devmask = 0, err_mask;
1108 /* determine if device 0/1 are present */
1109 if (bfin_devchk(ap, 0))
1110 devmask |= (1 << 0);
1111 if (slave_possible && bfin_devchk(ap, 1))
1112 devmask |= (1 << 1);
1114 /* select device 0 again */
1115 bfin_dev_select(ap, 0);
1117 /* issue bus reset */
1118 err_mask = bfin_bus_softreset(ap, devmask);
1120 ata_port_err(ap, "SRST failed (err_mask=0x%x)\n",
1125 /* determine by signature whether we have ATA or ATAPI devices */
1126 classes[0] = ata_sff_dev_classify(&ap->link.device[0],
1127 devmask & (1 << 0), &err);
1128 if (slave_possible && err != 0x81)
1129 classes[1] = ata_sff_dev_classify(&ap->link.device[1],
1130 devmask & (1 << 1), &err);
1136 * bfin_bmdma_status - Read IDE DMA status
1137 * @ap: Port associated with this ATA transaction.
1140 static unsigned char bfin_bmdma_status(struct ata_port *ap)
1142 unsigned char host_stat = 0;
1143 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1145 if (ATAPI_GET_STATUS(base) & (MULTI_XFER_ON | ULTRA_XFER_ON))
1146 host_stat |= ATA_DMA_ACTIVE;
1147 if (ATAPI_GET_INT_STATUS(base) & ATAPI_DEV_INT)
1148 host_stat |= ATA_DMA_INTR;
1150 dev_dbg(ap->dev, "ATAPI: host_stat=0x%x\n", host_stat);
1156 * bfin_data_xfer - Transfer data by PIO
1157 * @adev: device for this I/O
1159 * @buflen: buffer length
1160 * @write_data: read/write
1162 * Note: Original code is ata_sff_data_xfer().
1165 static unsigned int bfin_data_xfer(struct ata_device *dev, unsigned char *buf,
1166 unsigned int buflen, int rw)
1168 struct ata_port *ap = dev->link->ap;
1169 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1170 unsigned int words = buflen >> 1;
1171 unsigned short *buf16 = (u16 *)buf;
1173 /* Transfer multiple of 2 bytes */
1175 read_atapi_data(base, words, buf16);
1177 write_atapi_data(base, words, buf16);
1179 /* Transfer trailing 1 byte, if any. */
1180 if (unlikely(buflen & 0x01)) {
1181 unsigned short align_buf[1] = { 0 };
1182 unsigned char *trailing_buf = buf + buflen - 1;
1185 read_atapi_data(base, 1, align_buf);
1186 memcpy(trailing_buf, align_buf, 1);
1188 memcpy(align_buf, trailing_buf, 1);
1189 write_atapi_data(base, 1, align_buf);
1198 * bfin_irq_clear - Clear ATAPI interrupt.
1199 * @ap: Port associated with this ATA transaction.
1201 * Note: Original code is ata_bmdma_irq_clear().
1204 static void bfin_irq_clear(struct ata_port *ap)
1206 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1208 dev_dbg(ap->dev, "in atapi irq clear\n");
1209 ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT
1210 | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT
1211 | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT);
1215 * bfin_thaw - Thaw DMA controller port
1218 * Note: Original code is ata_sff_thaw().
1221 void bfin_thaw(struct ata_port *ap)
1223 dev_dbg(ap->dev, "in atapi dma thaw\n");
1224 bfin_check_status(ap);
1229 * bfin_postreset - standard postreset callback
1230 * @ap: the target ata_port
1231 * @classes: classes of attached devices
1233 * Note: Original code is ata_sff_postreset().
1236 static void bfin_postreset(struct ata_link *link, unsigned int *classes)
1238 struct ata_port *ap = link->ap;
1239 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1241 /* re-enable interrupts */
1244 /* is double-select really necessary? */
1245 if (classes[0] != ATA_DEV_NONE)
1246 bfin_dev_select(ap, 1);
1247 if (classes[1] != ATA_DEV_NONE)
1248 bfin_dev_select(ap, 0);
1250 /* bail out if no device is present */
1251 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
1255 /* set up device control */
1256 write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
1259 static void bfin_port_stop(struct ata_port *ap)
1261 dev_dbg(ap->dev, "in atapi port stop\n");
1262 if (ap->udma_mask != 0 || ap->mwdma_mask != 0) {
1263 free_dma(CH_ATAPI_RX);
1264 free_dma(CH_ATAPI_TX);
1268 static int bfin_port_start(struct ata_port *ap)
1270 dev_dbg(ap->dev, "in atapi port start\n");
1271 if (!(ap->udma_mask || ap->mwdma_mask))
1274 if (request_dma(CH_ATAPI_RX, "BFIN ATAPI RX DMA") >= 0) {
1275 if (request_dma(CH_ATAPI_TX,
1276 "BFIN ATAPI TX DMA") >= 0)
1279 free_dma(CH_ATAPI_RX);
1284 dev_err(ap->dev, "Unable to request ATAPI DMA!"
1285 " Continue in PIO mode.\n");
1290 static unsigned int bfin_ata_host_intr(struct ata_port *ap,
1291 struct ata_queued_cmd *qc)
1293 struct ata_eh_info *ehi = &ap->link.eh_info;
1294 u8 status, host_stat = 0;
1296 VPRINTK("ata%u: protocol %d task_state %d\n",
1297 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1299 /* Check whether we are expecting interrupt in this state */
1300 switch (ap->hsm_task_state) {
1302 /* Some pre-ATAPI-4 devices assert INTRQ
1303 * at this state when ready to receive CDB.
1306 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1307 * The flag was turned on only for atapi devices.
1308 * No need to check is_atapi_taskfile(&qc->tf) again.
1310 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1314 if (qc->tf.protocol == ATA_PROT_DMA ||
1315 qc->tf.protocol == ATAPI_PROT_DMA) {
1316 /* check status of DMA engine */
1317 host_stat = ap->ops->bmdma_status(ap);
1318 VPRINTK("ata%u: host_stat 0x%X\n",
1319 ap->print_id, host_stat);
1321 /* if it's not our irq... */
1322 if (!(host_stat & ATA_DMA_INTR))
1325 /* before we do anything else, clear DMA-Start bit */
1326 ap->ops->bmdma_stop(qc);
1328 if (unlikely(host_stat & ATA_DMA_ERR)) {
1329 /* error when transferring data to/from memory */
1330 qc->err_mask |= AC_ERR_HOST_BUS;
1331 ap->hsm_task_state = HSM_ST_ERR;
1341 /* check altstatus */
1342 status = ap->ops->sff_check_altstatus(ap);
1343 if (status & ATA_BUSY)
1346 /* check main status, clearing INTRQ */
1347 status = ap->ops->sff_check_status(ap);
1348 if (unlikely(status & ATA_BUSY))
1351 /* ack bmdma irq events */
1352 ap->ops->sff_irq_clear(ap);
1354 ata_sff_hsm_move(ap, qc, status, 0);
1356 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
1357 qc->tf.protocol == ATAPI_PROT_DMA))
1358 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
1361 return 1; /* irq handled */
1364 ap->stats.idle_irq++;
1367 if ((ap->stats.idle_irq % 1000) == 0) {
1368 ap->ops->irq_ack(ap, 0); /* debug trap */
1369 ata_port_warn(ap, "irq trap\n");
1373 return 0; /* irq not handled */
1376 static irqreturn_t bfin_ata_interrupt(int irq, void *dev_instance)
1378 struct ata_host *host = dev_instance;
1380 unsigned int handled = 0;
1381 unsigned long flags;
1383 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1384 spin_lock_irqsave(&host->lock, flags);
1386 for (i = 0; i < host->n_ports; i++) {
1387 struct ata_port *ap = host->ports[i];
1388 struct ata_queued_cmd *qc;
1390 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1391 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1392 handled |= bfin_ata_host_intr(ap, qc);
1395 spin_unlock_irqrestore(&host->lock, flags);
1397 return IRQ_RETVAL(handled);
1401 static struct scsi_host_template bfin_sht = {
1402 ATA_BASE_SHT(DRV_NAME),
1403 .sg_tablesize = SG_NONE,
1404 .dma_boundary = ATA_DMA_BOUNDARY,
1407 static struct ata_port_operations bfin_pata_ops = {
1408 .inherits = &ata_bmdma_port_ops,
1410 .set_piomode = bfin_set_piomode,
1411 .set_dmamode = bfin_set_dmamode,
1413 .sff_tf_load = bfin_tf_load,
1414 .sff_tf_read = bfin_tf_read,
1415 .sff_exec_command = bfin_exec_command,
1416 .sff_check_status = bfin_check_status,
1417 .sff_check_altstatus = bfin_check_altstatus,
1418 .sff_dev_select = bfin_dev_select,
1419 .sff_set_devctl = bfin_set_devctl,
1421 .bmdma_setup = bfin_bmdma_setup,
1422 .bmdma_start = bfin_bmdma_start,
1423 .bmdma_stop = bfin_bmdma_stop,
1424 .bmdma_status = bfin_bmdma_status,
1425 .sff_data_xfer = bfin_data_xfer,
1427 .qc_prep = ata_noop_qc_prep,
1430 .softreset = bfin_softreset,
1431 .postreset = bfin_postreset,
1433 .sff_irq_clear = bfin_irq_clear,
1435 .port_start = bfin_port_start,
1436 .port_stop = bfin_port_stop,
1439 static struct ata_port_info bfin_port_info[] = {
1441 .flags = ATA_FLAG_SLAVE_POSS,
1442 .pio_mask = ATA_PIO4,
1445 .port_ops = &bfin_pata_ops,
1450 * bfin_reset_controller - initialize BF54x ATAPI controller.
1453 static int bfin_reset_controller(struct ata_host *host)
1455 void __iomem *base = (void __iomem *)host->ports[0]->ioaddr.ctl_addr;
1457 unsigned short status;
1459 /* Disable all ATAPI interrupts */
1460 ATAPI_SET_INT_MASK(base, 0);
1463 /* Assert the RESET signal 25us*/
1464 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | DEV_RST);
1467 /* Negate the RESET signal for 2ms*/
1468 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) & ~DEV_RST);
1471 /* Wait on Busy flag to clear */
1474 status = read_atapi_register(base, ATA_REG_STATUS);
1475 } while (--count && (status & ATA_BUSY));
1477 /* Enable only ATAPI Device interrupt */
1478 ATAPI_SET_INT_MASK(base, 1);
1485 * atapi_io_port - define atapi peripheral port pins.
1487 static unsigned short atapi_io_port[] = {
1520 * bfin_atapi_probe - attach a bfin atapi interface
1521 * @pdev: platform device
1523 * Register a bfin atapi interface.
1526 * Platform devices are expected to contain 2 resources per port:
1528 * - I/O Base (IORESOURCE_IO)
1529 * - IRQ (IORESOURCE_IRQ)
1532 static int __devinit bfin_atapi_probe(struct platform_device *pdev)
1535 struct resource *res;
1536 struct ata_host *host;
1537 unsigned int fsclk = get_sclk();
1539 const struct ata_port_info *ppi[] =
1540 { &bfin_port_info[board_idx], NULL };
1543 * Simple resource validation ..
1545 if (unlikely(pdev->num_resources != 2)) {
1546 dev_err(&pdev->dev, "invalid number of resources\n");
1551 * Get the register base first
1553 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1557 while (bfin_port_info[board_idx].udma_mask > 0 &&
1558 udma_fsclk[udma_mode] > fsclk) {
1560 bfin_port_info[board_idx].udma_mask >>= 1;
1564 * Now that that's out of the way, wire up the port..
1566 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1);
1570 host->ports[0]->ioaddr.ctl_addr = (void *)res->start;
1572 if (peripheral_request_list(atapi_io_port, "atapi-io-port")) {
1573 dev_err(&pdev->dev, "Requesting Peripherals failed\n");
1577 if (bfin_reset_controller(host)) {
1578 peripheral_free_list(atapi_io_port);
1579 dev_err(&pdev->dev, "Fail to reset ATAPI device\n");
1583 if (ata_host_activate(host, platform_get_irq(pdev, 0),
1584 bfin_ata_interrupt, IRQF_SHARED, &bfin_sht) != 0) {
1585 peripheral_free_list(atapi_io_port);
1586 dev_err(&pdev->dev, "Fail to attach ATAPI device\n");
1590 dev_set_drvdata(&pdev->dev, host);
1596 * bfin_atapi_remove - unplug a bfin atapi interface
1597 * @pdev: platform device
1599 * A bfin atapi device has been unplugged. Perform the needed
1600 * cleanup. Also called on module unload for any active devices.
1602 static int __devexit bfin_atapi_remove(struct platform_device *pdev)
1604 struct device *dev = &pdev->dev;
1605 struct ata_host *host = dev_get_drvdata(dev);
1607 ata_host_detach(host);
1608 dev_set_drvdata(&pdev->dev, NULL);
1610 peripheral_free_list(atapi_io_port);
1616 static int bfin_atapi_suspend(struct platform_device *pdev, pm_message_t state)
1618 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1620 return ata_host_suspend(host, state);
1625 static int bfin_atapi_resume(struct platform_device *pdev)
1627 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1631 ret = bfin_reset_controller(host);
1633 printk(KERN_ERR DRV_NAME ": Error during HW init\n");
1636 ata_host_resume(host);
1642 #define bfin_atapi_suspend NULL
1643 #define bfin_atapi_resume NULL
1646 static struct platform_driver bfin_atapi_driver = {
1647 .probe = bfin_atapi_probe,
1648 .remove = __devexit_p(bfin_atapi_remove),
1649 .suspend = bfin_atapi_suspend,
1650 .resume = bfin_atapi_resume,
1653 .owner = THIS_MODULE,
1657 #define ATAPI_MODE_SIZE 10
1658 static char bfin_atapi_mode[ATAPI_MODE_SIZE];
1660 static int __init bfin_atapi_init(void)
1662 pr_info("register bfin atapi driver\n");
1664 switch(bfin_atapi_mode[0]) {
1670 bfin_port_info[0].mwdma_mask = ATA_MWDMA2;
1673 bfin_port_info[0].udma_mask = ATA_UDMA5;
1676 return platform_driver_register(&bfin_atapi_driver);
1679 static void __exit bfin_atapi_exit(void)
1681 platform_driver_unregister(&bfin_atapi_driver);
1684 module_init(bfin_atapi_init);
1685 module_exit(bfin_atapi_exit);
1689 * udma/UDMA (default)
1692 module_param_string(bfin_atapi_mode, bfin_atapi_mode, ATAPI_MODE_SIZE, 0);
1694 MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
1695 MODULE_DESCRIPTION("PATA driver for blackfin 54x ATAPI controller");
1696 MODULE_LICENSE("GPL");
1697 MODULE_VERSION(DRV_VERSION);
1698 MODULE_ALIAS("platform:" DRV_NAME);