2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
4 * This driver is heavily based upon:
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
14 * Look into engine reset on timeout errors. Should not be required.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/blkdev.h>
22 #include <linux/delay.h>
23 #include <scsi/scsi_host.h>
24 #include <linux/libata.h>
26 #define DRV_NAME "pata_hpt37x"
27 #define DRV_VERSION "0.6.15"
37 struct hpt_clock const *clocks[4];
40 /* key for bus clock timings
42 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
43 * DMA. cycles = value + 1
44 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
45 * DMA. cycles = value + 1
46 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
48 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
50 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
51 * during task file register access.
52 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
54 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
58 * 30 PIO_MST enable. if set, the chip is in bus master mode during
63 static struct hpt_clock hpt37x_timings_33[] = {
64 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
65 { XFER_UDMA_5, 0x12446231 },
66 { XFER_UDMA_4, 0x12446231 },
67 { XFER_UDMA_3, 0x126c6231 },
68 { XFER_UDMA_2, 0x12486231 },
69 { XFER_UDMA_1, 0x124c6233 },
70 { XFER_UDMA_0, 0x12506297 },
72 { XFER_MW_DMA_2, 0x22406c31 },
73 { XFER_MW_DMA_1, 0x22406c33 },
74 { XFER_MW_DMA_0, 0x22406c97 },
76 { XFER_PIO_4, 0x06414e31 },
77 { XFER_PIO_3, 0x06414e42 },
78 { XFER_PIO_2, 0x06414e53 },
79 { XFER_PIO_1, 0x06814e93 },
80 { XFER_PIO_0, 0x06814ea7 }
83 static struct hpt_clock hpt37x_timings_50[] = {
84 { XFER_UDMA_6, 0x12848242 },
85 { XFER_UDMA_5, 0x12848242 },
86 { XFER_UDMA_4, 0x12ac8242 },
87 { XFER_UDMA_3, 0x128c8242 },
88 { XFER_UDMA_2, 0x120c8242 },
89 { XFER_UDMA_1, 0x12148254 },
90 { XFER_UDMA_0, 0x121882ea },
92 { XFER_MW_DMA_2, 0x22808242 },
93 { XFER_MW_DMA_1, 0x22808254 },
94 { XFER_MW_DMA_0, 0x228082ea },
96 { XFER_PIO_4, 0x0a81f442 },
97 { XFER_PIO_3, 0x0a81f443 },
98 { XFER_PIO_2, 0x0a81f454 },
99 { XFER_PIO_1, 0x0ac1f465 },
100 { XFER_PIO_0, 0x0ac1f48a }
103 static struct hpt_clock hpt37x_timings_66[] = {
104 { XFER_UDMA_6, 0x1c869c62 },
105 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
106 { XFER_UDMA_4, 0x1c8a9c62 },
107 { XFER_UDMA_3, 0x1c8e9c62 },
108 { XFER_UDMA_2, 0x1c929c62 },
109 { XFER_UDMA_1, 0x1c9a9c62 },
110 { XFER_UDMA_0, 0x1c829c62 },
112 { XFER_MW_DMA_2, 0x2c829c62 },
113 { XFER_MW_DMA_1, 0x2c829c66 },
114 { XFER_MW_DMA_0, 0x2c829d2e },
116 { XFER_PIO_4, 0x0c829c62 },
117 { XFER_PIO_3, 0x0c829c84 },
118 { XFER_PIO_2, 0x0c829ca6 },
119 { XFER_PIO_1, 0x0d029d26 },
120 { XFER_PIO_0, 0x0d029d5e }
124 static const struct hpt_chip hpt370 = {
135 static const struct hpt_chip hpt370a = {
146 static const struct hpt_chip hpt372 = {
157 static const struct hpt_chip hpt302 = {
168 static const struct hpt_chip hpt371 = {
179 static const struct hpt_chip hpt372a = {
190 static const struct hpt_chip hpt374 = {
202 * hpt37x_find_mode - reset the hpt37x bus
204 * @speed: transfer mode
206 * Return the 32bit register programming information for this channel
207 * that matches the speed provided.
210 static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
212 struct hpt_clock *clocks = ap->host->private_data;
214 while(clocks->xfer_speed) {
215 if (clocks->xfer_speed == speed)
216 return clocks->timing;
220 return 0xffffffffU; /* silence compiler warning */
223 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
225 unsigned char model_num[ATA_ID_PROD_LEN + 1];
228 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
230 while (list[i] != NULL) {
231 if (!strcmp(list[i], model_num)) {
232 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
241 static const char *bad_ata33[] = {
242 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
243 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
244 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
246 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
247 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
248 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
252 static const char *bad_ata100_5[] = {
272 * hpt370_filter - mode selection filter
275 * Block UDMA on devices that cause trouble with this controller.
278 static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
280 if (adev->class == ATA_DEV_ATA) {
281 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
282 mask &= ~ATA_MASK_UDMA;
283 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
284 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
286 return ata_bmdma_mode_filter(adev, mask);
290 * hpt370a_filter - mode selection filter
293 * Block UDMA on devices that cause trouble with this controller.
296 static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
298 if (adev->class == ATA_DEV_ATA) {
299 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
300 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
302 return ata_bmdma_mode_filter(adev, mask);
306 * hpt37x_cable_detect - Detect the cable type
307 * @ap: ATA port to detect on
309 * Return the cable type attached to this port
312 static int hpt37x_cable_detect(struct ata_port *ap)
314 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
317 pci_read_config_byte(pdev, 0x5B, &scr2);
318 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
320 udelay(10); /* debounce */
322 /* Cable register now active */
323 pci_read_config_byte(pdev, 0x5A, &ata66);
325 pci_write_config_byte(pdev, 0x5B, scr2);
327 if (ata66 & (2 >> ap->port_no))
328 return ATA_CBL_PATA40;
330 return ATA_CBL_PATA80;
334 * hpt374_fn1_cable_detect - Detect the cable type
335 * @ap: ATA port to detect on
337 * Return the cable type attached to this port
340 static int hpt374_fn1_cable_detect(struct ata_port *ap)
342 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
343 unsigned int mcrbase = 0x50 + 4 * ap->port_no;
347 /* Do the extra channel work */
348 pci_read_config_word(pdev, mcrbase + 2, &mcr3);
349 /* Set bit 15 of 0x52 to enable TCBLID as input */
350 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);
351 pci_read_config_byte(pdev, 0x5A, &ata66);
352 /* Reset TCBLID/FCBLID to output */
353 pci_write_config_word(pdev, mcrbase + 2, mcr3);
355 if (ata66 & (2 >> ap->port_no))
356 return ATA_CBL_PATA40;
358 return ATA_CBL_PATA80;
362 * hpt37x_pre_reset - reset the hpt37x bus
363 * @link: ATA link to reset
364 * @deadline: deadline jiffies for the operation
366 * Perform the initial reset handling for the HPT37x.
369 static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
371 struct ata_port *ap = link->ap;
372 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
373 static const struct pci_bits hpt37x_enable_bits[] = {
374 { 0x50, 1, 0x04, 0x04 },
375 { 0x54, 1, 0x04, 0x04 }
377 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
380 /* Reset the state machine */
381 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
384 return ata_sff_prereset(link, deadline);
387 static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev,
390 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
392 u32 reg, timing, mask;
395 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
396 addr2 = 0x51 + 4 * ap->port_no;
398 /* Fast interrupt prediction disable, hold off interrupt disable */
399 pci_read_config_byte(pdev, addr2, &fast);
402 pci_write_config_byte(pdev, addr2, fast);
404 /* Determine timing mask and find matching mode entry */
405 if (mode < XFER_MW_DMA_0)
407 else if (mode < XFER_UDMA_0)
412 timing = hpt37x_find_mode(ap, mode);
414 pci_read_config_dword(pdev, addr1, ®);
415 reg = (reg & ~mask) | (timing & mask);
416 pci_write_config_dword(pdev, addr1, reg);
419 * hpt370_set_piomode - PIO setup
421 * @adev: device on the interface
423 * Perform PIO mode setup.
426 static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
428 hpt370_set_mode(ap, adev, adev->pio_mode);
432 * hpt370_set_dmamode - DMA timing setup
434 * @adev: Device being configured
436 * Set up the channel for MWDMA or UDMA modes.
439 static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
441 hpt370_set_mode(ap, adev, adev->dma_mode);
445 * hpt370_bmdma_end - DMA engine stop
448 * Work around the HPT370 DMA engine.
451 static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
453 struct ata_port *ap = qc->ap;
454 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
455 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
456 u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
459 if (dma_stat & ATA_DMA_ACTIVE) {
461 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
463 if (dma_stat & ATA_DMA_ACTIVE) {
464 /* Clear the engine */
465 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
468 dma_cmd = ioread8(bmdma + ATA_DMA_CMD);
469 iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD);
471 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
472 iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR,
473 bmdma + ATA_DMA_STATUS);
474 /* Clear the engine */
475 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
481 static void hpt372_set_mode(struct ata_port *ap, struct ata_device *adev,
484 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
486 u32 reg, timing, mask;
489 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
490 addr2 = 0x51 + 4 * ap->port_no;
492 /* Fast interrupt prediction disable, hold off interrupt disable */
493 pci_read_config_byte(pdev, addr2, &fast);
495 pci_write_config_byte(pdev, addr2, fast);
497 /* Determine timing mask and find matching mode entry */
498 if (mode < XFER_MW_DMA_0)
500 else if (mode < XFER_UDMA_0)
505 timing = hpt37x_find_mode(ap, mode);
507 pci_read_config_dword(pdev, addr1, ®);
508 reg = (reg & ~mask) | (timing & mask);
509 pci_write_config_dword(pdev, addr1, reg);
513 * hpt372_set_piomode - PIO setup
515 * @adev: device on the interface
517 * Perform PIO mode setup.
520 static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
522 hpt372_set_mode(ap, adev, adev->pio_mode);
526 * hpt372_set_dmamode - DMA timing setup
528 * @adev: Device being configured
530 * Set up the channel for MWDMA or UDMA modes.
533 static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
535 hpt372_set_mode(ap, adev, adev->dma_mode);
539 * hpt37x_bmdma_end - DMA engine stop
542 * Clean up after the HPT372 and later DMA engine
545 static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
547 struct ata_port *ap = qc->ap;
548 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
549 int mscreg = 0x50 + 4 * ap->port_no;
550 u8 bwsr_stat, msc_stat;
552 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
553 pci_read_config_byte(pdev, mscreg, &msc_stat);
554 if (bwsr_stat & (1 << ap->port_no))
555 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
560 static struct scsi_host_template hpt37x_sht = {
561 ATA_BMDMA_SHT(DRV_NAME),
565 * Configuration for HPT370
568 static struct ata_port_operations hpt370_port_ops = {
569 .inherits = &ata_bmdma_port_ops,
571 .bmdma_stop = hpt370_bmdma_stop,
573 .mode_filter = hpt370_filter,
574 .cable_detect = hpt37x_cable_detect,
575 .set_piomode = hpt370_set_piomode,
576 .set_dmamode = hpt370_set_dmamode,
577 .prereset = hpt37x_pre_reset,
581 * Configuration for HPT370A. Close to 370 but less filters
584 static struct ata_port_operations hpt370a_port_ops = {
585 .inherits = &hpt370_port_ops,
586 .mode_filter = hpt370a_filter,
590 * Configuration for HPT372, HPT371, HPT302. Slightly different PIO
591 * and DMA mode setting functionality.
594 static struct ata_port_operations hpt372_port_ops = {
595 .inherits = &ata_bmdma_port_ops,
597 .bmdma_stop = hpt37x_bmdma_stop,
599 .cable_detect = hpt37x_cable_detect,
600 .set_piomode = hpt372_set_piomode,
601 .set_dmamode = hpt372_set_dmamode,
602 .prereset = hpt37x_pre_reset,
606 * Configuration for HPT374. Mode setting works like 372 and friends
607 * but we have a different cable detection procedure for function 1.
610 static struct ata_port_operations hpt374_fn1_port_ops = {
611 .inherits = &hpt372_port_ops,
612 .cable_detect = hpt374_fn1_cable_detect,
613 .prereset = hpt37x_pre_reset,
617 * hpt37x_clock_slot - Turn timing to PC clock entry
618 * @freq: Reported frequency timing
621 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
625 static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
627 unsigned int f = (base * freq) / 192; /* Mhz */
629 return 0; /* 33Mhz slot */
631 return 1; /* 40Mhz slot */
633 return 2; /* 50Mhz slot */
634 return 3; /* 60Mhz slot */
638 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
641 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
645 static int hpt37x_calibrate_dpll(struct pci_dev *dev)
651 for(tries = 0; tries < 0x5000; tries++) {
653 pci_read_config_byte(dev, 0x5b, ®5b);
655 /* See if it stays set */
656 for(tries = 0; tries < 0x1000; tries ++) {
657 pci_read_config_byte(dev, 0x5b, ®5b);
659 if ((reg5b & 0x80) == 0)
662 /* Turn off tuning, we have the DPLL set */
663 pci_read_config_dword(dev, 0x5c, ®5c);
664 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
668 /* Never went stable */
672 static u32 hpt374_read_freq(struct pci_dev *pdev)
675 unsigned long io_base = pci_resource_start(pdev, 4);
676 if (PCI_FUNC(pdev->devfn) & 1) {
677 struct pci_dev *pdev_0;
679 pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
680 /* Someone hot plugged the controller on us ? */
683 io_base = pci_resource_start(pdev_0, 4);
684 freq = inl(io_base + 0x90);
687 freq = inl(io_base + 0x90);
692 * hpt37x_init_one - Initialise an HPT37X/302
694 * @id: Entry in match table
696 * Initialise an HPT37x device. There are some interesting complications
697 * here. Firstly the chip may report 366 and be one of several variants.
698 * Secondly all the timings depend on the clock for the chip which we must
701 * This is the known chip mappings. It may be missing a couple of later
704 * Chip version PCI Rev Notes
705 * HPT366 4 (HPT366) 0 Other driver
706 * HPT366 4 (HPT366) 1 Other driver
707 * HPT368 4 (HPT366) 2 Other driver
708 * HPT370 4 (HPT366) 3 UDMA100
709 * HPT370A 4 (HPT366) 4 UDMA100
710 * HPT372 4 (HPT366) 5 UDMA133 (1)
711 * HPT372N 4 (HPT366) 6 Other driver
712 * HPT372A 5 (HPT372) 1 UDMA133 (1)
713 * HPT372N 5 (HPT372) 2 Other driver
714 * HPT302 6 (HPT302) 1 UDMA133
715 * HPT302N 6 (HPT302) 2 Other driver
716 * HPT371 7 (HPT371) * UDMA133
717 * HPT374 8 (HPT374) * UDMA133 4 channel
718 * HPT372N 9 (HPT372N) * Other driver
720 * (1) UDMA133 support depends on the bus clock
723 static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
725 /* HPT370 - UDMA100 */
726 static const struct ata_port_info info_hpt370 = {
727 .flags = ATA_FLAG_SLAVE_POSS,
728 .pio_mask = ATA_PIO4,
729 .mwdma_mask = ATA_MWDMA2,
730 .udma_mask = ATA_UDMA5,
731 .port_ops = &hpt370_port_ops
733 /* HPT370A - UDMA100 */
734 static const struct ata_port_info info_hpt370a = {
735 .flags = ATA_FLAG_SLAVE_POSS,
736 .pio_mask = ATA_PIO4,
737 .mwdma_mask = ATA_MWDMA2,
738 .udma_mask = ATA_UDMA5,
739 .port_ops = &hpt370a_port_ops
741 /* HPT370 - UDMA100 */
742 static const struct ata_port_info info_hpt370_33 = {
743 .flags = ATA_FLAG_SLAVE_POSS,
744 .pio_mask = ATA_PIO4,
745 .mwdma_mask = ATA_MWDMA2,
746 .udma_mask = ATA_UDMA5,
747 .port_ops = &hpt370_port_ops
749 /* HPT370A - UDMA100 */
750 static const struct ata_port_info info_hpt370a_33 = {
751 .flags = ATA_FLAG_SLAVE_POSS,
752 .pio_mask = ATA_PIO4,
753 .mwdma_mask = ATA_MWDMA2,
754 .udma_mask = ATA_UDMA5,
755 .port_ops = &hpt370a_port_ops
757 /* HPT371, 372 and friends - UDMA133 */
758 static const struct ata_port_info info_hpt372 = {
759 .flags = ATA_FLAG_SLAVE_POSS,
760 .pio_mask = ATA_PIO4,
761 .mwdma_mask = ATA_MWDMA2,
762 .udma_mask = ATA_UDMA6,
763 .port_ops = &hpt372_port_ops
765 /* HPT374 - UDMA100, function 1 uses different prereset method */
766 static const struct ata_port_info info_hpt374_fn0 = {
767 .flags = ATA_FLAG_SLAVE_POSS,
768 .pio_mask = ATA_PIO4,
769 .mwdma_mask = ATA_MWDMA2,
770 .udma_mask = ATA_UDMA5,
771 .port_ops = &hpt372_port_ops
773 static const struct ata_port_info info_hpt374_fn1 = {
774 .flags = ATA_FLAG_SLAVE_POSS,
775 .pio_mask = ATA_PIO4,
776 .mwdma_mask = ATA_MWDMA2,
777 .udma_mask = ATA_UDMA5,
778 .port_ops = &hpt374_fn1_port_ops
781 static const int MHz[4] = { 33, 40, 50, 66 };
782 void *private_data = NULL;
783 const struct ata_port_info *ppi[] = { NULL, NULL };
784 u8 rev = dev->revision;
790 unsigned long iobase = pci_resource_start(dev, 4);
792 const struct hpt_chip *chip_table;
796 rc = pcim_enable_device(dev);
800 if (dev->device == PCI_DEVICE_ID_TTI_HPT366) {
801 /* May be a later chip in disguise. Check */
802 /* Older chips are in the HPT366 driver. Ignore them */
805 /* N series chips have their own driver. Ignore */
811 ppi[0] = &info_hpt370;
812 chip_table = &hpt370;
816 ppi[0] = &info_hpt370a;
817 chip_table = &hpt370a;
821 ppi[0] = &info_hpt372;
822 chip_table = &hpt372;
825 printk(KERN_ERR "pata_hpt37x: Unknown HPT366 "
826 "subtype, please report (%d).\n", rev);
830 switch(dev->device) {
831 case PCI_DEVICE_ID_TTI_HPT372:
832 /* 372N if rev >= 2*/
835 ppi[0] = &info_hpt372;
836 chip_table = &hpt372a;
838 case PCI_DEVICE_ID_TTI_HPT302:
839 /* 302N if rev > 1 */
842 ppi[0] = &info_hpt372;
844 chip_table = &hpt302;
846 case PCI_DEVICE_ID_TTI_HPT371:
849 ppi[0] = &info_hpt372;
850 chip_table = &hpt371;
851 /* Single channel device, master is not present
852 but the BIOS (or us for non x86) must mark it
854 pci_read_config_byte(dev, 0x50, &mcr1);
856 pci_write_config_byte(dev, 0x50, mcr1);
858 case PCI_DEVICE_ID_TTI_HPT374:
859 chip_table = &hpt374;
860 if (!(PCI_FUNC(dev->devfn) & 1))
861 *ppi = &info_hpt374_fn0;
863 *ppi = &info_hpt374_fn1;
866 printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device);
870 /* Ok so this is a chip we support */
872 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
873 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
874 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
875 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
877 pci_read_config_byte(dev, 0x5A, &irqmask);
879 pci_write_config_byte(dev, 0x5a, irqmask);
882 * default to pci clock. make sure MA15/16 are set to output
883 * to prevent drives having problems with 40-pin cables. Needed
884 * for some drives such as IBM-DTLA which will not enter ready
885 * state on reset when PDIAG is a input.
888 pci_write_config_byte(dev, 0x5b, 0x23);
891 * HighPoint does this for HPT372A.
892 * NOTE: This register is only writeable via I/O space.
894 if (chip_table == &hpt372a)
895 outb(0x0e, iobase + 0x9c);
897 /* Some devices do not let this value be accessed via PCI space
898 according to the old driver. In addition we must use the value
899 from FN 0 on the HPT374 */
901 if (chip_table == &hpt374) {
902 freq = hpt374_read_freq(dev);
906 freq = inl(iobase + 0x90);
908 if ((freq >> 12) != 0xABCDE) {
913 printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n");
915 /* This is the process the HPT371 BIOS is reported to use */
916 for(i = 0; i < 128; i++) {
917 pci_read_config_byte(dev, 0x78, &sr);
926 * Turn the frequency check into a band and then find a timing
930 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
931 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
933 * We need to try PLL mode instead
935 * For non UDMA133 capable devices we should
936 * use a 50MHz DPLL by choice
938 unsigned int f_low, f_high;
942 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;
944 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
949 /* Select the DPLL clock. */
950 pci_write_config_byte(dev, 0x5b, 0x21);
951 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
953 for(adjust = 0; adjust < 8; adjust++) {
954 if (hpt37x_calibrate_dpll(dev))
956 /* See if it'll settle at a fractionally different clock */
958 f_low -= adjust >> 1;
960 f_high += adjust >> 1;
961 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
964 printk(KERN_ERR "pata_hpt37x: DPLL did not stabilize!\n");
968 private_data = (void *)hpt37x_timings_66;
970 private_data = (void *)hpt37x_timings_50;
972 printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using %dMHz DPLL.\n",
973 MHz[clock_slot], MHz[dpll]);
975 private_data = (void *)chip_table->clocks[clock_slot];
977 * Perform a final fixup. Note that we will have used the
978 * DPLL on the HPT372 which means we don't have to worry
979 * about lack of UDMA133 support on lower clocks
982 if (clock_slot < 2 && ppi[0] == &info_hpt370)
983 ppi[0] = &info_hpt370_33;
984 if (clock_slot < 2 && ppi[0] == &info_hpt370a)
985 ppi[0] = &info_hpt370a_33;
986 printk(KERN_INFO "pata_hpt37x: %s using %dMHz bus clock.\n",
987 chip_table->name, MHz[clock_slot]);
990 /* Now kick off ATA set up */
991 return ata_pci_sff_init_one(dev, ppi, &hpt37x_sht, private_data);
994 static const struct pci_device_id hpt37x[] = {
995 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
996 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
997 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
998 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
999 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1004 static struct pci_driver hpt37x_pci_driver = {
1007 .probe = hpt37x_init_one,
1008 .remove = ata_pci_remove_one
1011 static int __init hpt37x_init(void)
1013 return pci_register_driver(&hpt37x_pci_driver);
1016 static void __exit hpt37x_exit(void)
1018 pci_unregister_driver(&hpt37x_pci_driver);
1021 MODULE_AUTHOR("Alan Cox");
1022 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1023 MODULE_LICENSE("GPL");
1024 MODULE_DEVICE_TABLE(pci, hpt37x);
1025 MODULE_VERSION(DRV_VERSION);
1027 module_init(hpt37x_init);
1028 module_exit(hpt37x_exit);