2 * Libata driver for the highpoint 372N and 302N UDMA66 ATA controllers.
4 * This driver is heavily based upon:
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
15 * Work out best PLL policy
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <scsi/scsi_host.h>
25 #include <linux/libata.h>
27 #define DRV_NAME "pata_hpt3x2n"
28 #define DRV_VERSION "0.3.7"
31 HPT_PCI_FAST = (1 << 31),
43 struct hpt_clock *clocks[3];
46 /* key for bus clock timings
48 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
49 * DMA. cycles = value + 1
50 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
51 * DMA. cycles = value + 1
52 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
54 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
56 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
57 * during task file register access.
58 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
60 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
64 * 30 PIO_MST enable. if set, the chip is in bus master mode during
69 /* 66MHz DPLL clocks */
71 static struct hpt_clock hpt3x2n_clocks[] = {
72 { XFER_UDMA_7, 0x1c869c62 },
73 { XFER_UDMA_6, 0x1c869c62 },
74 { XFER_UDMA_5, 0x1c8a9c62 },
75 { XFER_UDMA_4, 0x1c8a9c62 },
76 { XFER_UDMA_3, 0x1c8e9c62 },
77 { XFER_UDMA_2, 0x1c929c62 },
78 { XFER_UDMA_1, 0x1c9a9c62 },
79 { XFER_UDMA_0, 0x1c829c62 },
81 { XFER_MW_DMA_2, 0x2c829c62 },
82 { XFER_MW_DMA_1, 0x2c829c66 },
83 { XFER_MW_DMA_0, 0x2c829d2e },
85 { XFER_PIO_4, 0x0c829c62 },
86 { XFER_PIO_3, 0x0c829c84 },
87 { XFER_PIO_2, 0x0c829ca6 },
88 { XFER_PIO_1, 0x0d029d26 },
89 { XFER_PIO_0, 0x0d029d5e },
93 * hpt3x2n_find_mode - reset the hpt3x2n bus
95 * @speed: transfer mode
97 * Return the 32bit register programming information for this channel
98 * that matches the speed provided. For the moment the clocks table
99 * is hard coded but easy to change. This will be needed if we use
103 static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
105 struct hpt_clock *clocks = hpt3x2n_clocks;
107 while(clocks->xfer_speed) {
108 if (clocks->xfer_speed == speed)
109 return clocks->timing;
113 return 0xffffffffU; /* silence compiler warning */
117 * hpt3x2n_cable_detect - Detect the cable type
118 * @ap: ATA port to detect on
120 * Return the cable type attached to this port
123 static int hpt3x2n_cable_detect(struct ata_port *ap)
126 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
128 pci_read_config_byte(pdev, 0x5B, &scr2);
129 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
131 udelay(10); /* debounce */
133 /* Cable register now active */
134 pci_read_config_byte(pdev, 0x5A, &ata66);
136 pci_write_config_byte(pdev, 0x5B, scr2);
138 if (ata66 & (2 >> ap->port_no))
139 return ATA_CBL_PATA40;
141 return ATA_CBL_PATA80;
145 * hpt3x2n_pre_reset - reset the hpt3x2n bus
146 * @link: ATA link to reset
147 * @deadline: deadline jiffies for the operation
149 * Perform the initial reset handling for the 3x2n series controllers.
150 * Reset the hardware and state machine,
153 static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline)
155 struct ata_port *ap = link->ap;
156 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
157 /* Reset the state machine */
158 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
161 return ata_sff_prereset(link, deadline);
165 * hpt3x2n_set_piomode - PIO setup
167 * @adev: device on the interface
169 * Perform PIO mode setup.
172 static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
174 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
180 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
181 addr2 = 0x51 + 4 * ap->port_no;
183 /* Fast interrupt prediction disable, hold off interrupt disable */
184 pci_read_config_byte(pdev, addr2, &fast);
186 pci_write_config_byte(pdev, addr2, fast);
188 pci_read_config_dword(pdev, addr1, ®);
189 mode = hpt3x2n_find_mode(ap, adev->pio_mode);
190 mode &= 0xCFC3FFFF; /* Leave DMA bits alone */
191 reg &= ~0xCFC3FFFF; /* Strip timing bits */
192 pci_write_config_dword(pdev, addr1, reg | mode);
196 * hpt3x2n_set_dmamode - DMA timing setup
198 * @adev: Device being configured
200 * Set up the channel for MWDMA or UDMA modes. Much the same as with
201 * PIO, load the mode number and then set MWDMA or UDMA flag.
204 static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
206 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
211 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
212 addr2 = 0x51 + 4 * ap->port_no;
214 /* Fast interrupt prediction disable, hold off interrupt disable */
215 pci_read_config_byte(pdev, addr2, &fast);
217 pci_write_config_byte(pdev, addr2, fast);
219 mask = adev->dma_mode < XFER_UDMA_0 ? 0x31C001FF : 0x303C0000;
221 pci_read_config_dword(pdev, addr1, ®);
222 mode = hpt3x2n_find_mode(ap, adev->dma_mode);
225 pci_write_config_dword(pdev, addr1, reg | mode);
229 * hpt3x2n_bmdma_end - DMA engine stop
232 * Clean up after the HPT3x2n and later DMA engine
235 static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
237 struct ata_port *ap = qc->ap;
238 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
239 int mscreg = 0x50 + 2 * ap->port_no;
240 u8 bwsr_stat, msc_stat;
242 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
243 pci_read_config_byte(pdev, mscreg, &msc_stat);
244 if (bwsr_stat & (1 << ap->port_no))
245 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
250 * hpt3x2n_set_clock - clock control
252 * @source: 0x21 or 0x23 for PLL or PCI sourced clock
254 * Switch the ATA bus clock between the PLL and PCI clock sources
255 * while correctly isolating the bus and resetting internal logic
257 * We must use the DPLL for
259 * - second channel UDMA7 (SATA ports) or higher
262 * or we will underclock the device and get reduced performance.
265 static void hpt3x2n_set_clock(struct ata_port *ap, int source)
267 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
269 /* Tristate the bus */
270 iowrite8(0x80, bmdma+0x73);
271 iowrite8(0x80, bmdma+0x77);
273 /* Switch clock and reset channels */
274 iowrite8(source, bmdma+0x7B);
275 iowrite8(0xC0, bmdma+0x79);
277 /* Reset state machines */
278 iowrite8(0x37, bmdma+0x70);
279 iowrite8(0x37, bmdma+0x74);
282 iowrite8(0x00, bmdma+0x79);
284 /* Reconnect channels to bus */
285 iowrite8(0x00, bmdma+0x73);
286 iowrite8(0x00, bmdma+0x77);
289 /* Check if our partner interface is busy */
291 static int hpt3x2n_pair_idle(struct ata_port *ap)
293 struct ata_host *host = ap->host;
294 struct ata_port *pair = host->ports[ap->port_no ^ 1];
296 if (pair->hsm_task_state == HSM_ST_IDLE)
301 static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
303 long flags = (long)ap->host->private_data;
304 /* See if we should use the DPLL */
306 return USE_DPLL; /* Needed for write */
308 return USE_DPLL; /* Needed at 66Mhz */
312 static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
314 struct ata_taskfile *tf = &qc->tf;
315 struct ata_port *ap = qc->ap;
316 int flags = (long)ap->host->private_data;
318 if (hpt3x2n_pair_idle(ap)) {
319 int dpll = hpt3x2n_use_dpll(ap, (tf->flags & ATA_TFLAG_WRITE));
320 if ((flags & USE_DPLL) != dpll) {
322 hpt3x2n_set_clock(ap, 0x21);
324 hpt3x2n_set_clock(ap, 0x23);
327 return ata_sff_qc_issue(qc);
330 static struct scsi_host_template hpt3x2n_sht = {
331 ATA_BMDMA_SHT(DRV_NAME),
335 * Configuration for HPT3x2n.
338 static struct ata_port_operations hpt3x2n_port_ops = {
339 .inherits = &ata_bmdma_port_ops,
341 .bmdma_stop = hpt3x2n_bmdma_stop,
342 .qc_issue = hpt3x2n_qc_issue,
344 .cable_detect = hpt3x2n_cable_detect,
345 .set_piomode = hpt3x2n_set_piomode,
346 .set_dmamode = hpt3x2n_set_dmamode,
347 .prereset = hpt3x2n_pre_reset,
351 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop
354 * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
358 static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
364 for(tries = 0; tries < 0x5000; tries++) {
366 pci_read_config_byte(dev, 0x5b, ®5b);
368 /* See if it stays set */
369 for(tries = 0; tries < 0x1000; tries ++) {
370 pci_read_config_byte(dev, 0x5b, ®5b);
372 if ((reg5b & 0x80) == 0)
375 /* Turn off tuning, we have the DPLL set */
376 pci_read_config_dword(dev, 0x5c, ®5c);
377 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
381 /* Never went stable */
385 static int hpt3x2n_pci_clock(struct pci_dev *pdev)
389 unsigned long iobase = pci_resource_start(pdev, 4);
391 fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */
392 if ((fcnt >> 12) != 0xABCDE) {
393 printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n");
394 return 33; /* Not BIOS set */
398 freq = (fcnt * 77) / 192;
411 * hpt3x2n_init_one - Initialise an HPT37X/302
413 * @id: Entry in match table
415 * Initialise an HPT3x2n device. There are some interesting complications
416 * here. Firstly the chip may report 366 and be one of several variants.
417 * Secondly all the timings depend on the clock for the chip which we must
420 * This is the known chip mappings. It may be missing a couple of later
423 * Chip version PCI Rev Notes
424 * HPT372 4 (HPT366) 5 Other driver
425 * HPT372N 4 (HPT366) 6 UDMA133
426 * HPT372 5 (HPT372) 1 Other driver
427 * HPT372N 5 (HPT372) 2 UDMA133
428 * HPT302 6 (HPT302) * Other driver
429 * HPT302N 6 (HPT302) > 1 UDMA133
430 * HPT371 7 (HPT371) * Other driver
431 * HPT371N 7 (HPT371) > 1 UDMA133
432 * HPT374 8 (HPT374) * Other driver
433 * HPT372N 9 (HPT372N) * UDMA133
435 * (1) UDMA133 support depends on the bus clock
437 * To pin down HPT371N
440 static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
442 /* HPT372N and friends - UDMA133 */
443 static const struct ata_port_info info = {
444 .flags = ATA_FLAG_SLAVE_POSS,
445 .pio_mask = ATA_PIO4,
446 .mwdma_mask = ATA_MWDMA2,
447 .udma_mask = ATA_UDMA6,
448 .port_ops = &hpt3x2n_port_ops
450 const struct ata_port_info *ppi[] = { &info, NULL };
451 u8 rev = dev->revision;
453 unsigned int pci_mhz;
454 unsigned int f_low, f_high;
456 unsigned long iobase = pci_resource_start(dev, 4);
460 rc = pcim_enable_device(dev);
464 switch(dev->device) {
465 case PCI_DEVICE_ID_TTI_HPT366:
469 case PCI_DEVICE_ID_TTI_HPT371:
472 /* 371N if rev > 1 */
474 case PCI_DEVICE_ID_TTI_HPT372:
475 /* 372N if rev >= 2*/
479 case PCI_DEVICE_ID_TTI_HPT302:
483 case PCI_DEVICE_ID_TTI_HPT372N:
486 printk(KERN_ERR "pata_hpt3x2n: PCI table is bogus please report (%d).\n", dev->device);
490 /* Ok so this is a chip we support */
492 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
493 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
494 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
495 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
497 pci_read_config_byte(dev, 0x5A, &irqmask);
499 pci_write_config_byte(dev, 0x5a, irqmask);
502 * HPT371 chips physically have only one channel, the secondary one,
503 * but the primary channel registers do exist! Go figure...
504 * So, we manually disable the non-existing channel here
505 * (if the BIOS hasn't done this already).
507 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
509 pci_read_config_byte(dev, 0x50, &mcr1);
511 pci_write_config_byte(dev, 0x50, mcr1);
514 /* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
515 50 for UDMA100. Right now we always use 66 */
517 pci_mhz = hpt3x2n_pci_clock(dev);
519 f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */
520 f_high = f_low + 2; /* Tolerance */
522 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
524 pci_write_config_byte(dev, 0x5B, 0x21);
526 /* Unlike the 37x we don't try jiggling the frequency */
527 for(adjust = 0; adjust < 8; adjust++) {
528 if (hpt3xn_calibrate_dpll(dev))
530 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
533 printk(KERN_ERR "pata_hpt3x2n: DPLL did not stabilize!\n");
537 printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using 66MHz DPLL.\n",
539 /* Set our private data up. We only need a few flags so we use
542 hpriv = (void *)PCI66;
544 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
545 * the MISC. register to stretch the UltraDMA Tss timing.
546 * NOTE: This register is only writeable via I/O space.
548 if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
549 outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
552 /* Now kick off ATA set up */
553 return ata_pci_sff_init_one(dev, ppi, &hpt3x2n_sht, hpriv);
556 static const struct pci_device_id hpt3x2n[] = {
557 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
558 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
559 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
560 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
561 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },
566 static struct pci_driver hpt3x2n_pci_driver = {
569 .probe = hpt3x2n_init_one,
570 .remove = ata_pci_remove_one
573 static int __init hpt3x2n_init(void)
575 return pci_register_driver(&hpt3x2n_pci_driver);
578 static void __exit hpt3x2n_exit(void)
580 pci_unregister_driver(&hpt3x2n_pci_driver);
583 MODULE_AUTHOR("Alan Cox");
584 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3x2n/30x");
585 MODULE_LICENSE("GPL");
586 MODULE_DEVICE_TABLE(pci, hpt3x2n);
587 MODULE_VERSION(DRV_VERSION);
589 module_init(hpt3x2n_init);
590 module_exit(hpt3x2n_exit);