2 * Libata driver for the highpoint 372N and 302N UDMA66 ATA controllers.
4 * This driver is heavily based upon:
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
15 * Work out best PLL policy
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <scsi/scsi_host.h>
25 #include <linux/libata.h>
27 #define DRV_NAME "pata_hpt3x2n"
28 #define DRV_VERSION "0.3.10"
31 HPT_PCI_FAST = (1 << 31),
43 struct hpt_clock *clocks[3];
46 /* key for bus clock timings
48 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
50 * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
52 * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
54 * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
56 * 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
57 * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
58 * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
59 * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
63 * 30 PIO_MST enable. If set, the chip is in bus master mode during
65 * 31 FIFO enable. Only for PIO.
68 /* 66MHz DPLL clocks */
70 static struct hpt_clock hpt3x2n_clocks[] = {
71 { XFER_UDMA_7, 0x1c869c62 },
72 { XFER_UDMA_6, 0x1c869c62 },
73 { XFER_UDMA_5, 0x1c8a9c62 },
74 { XFER_UDMA_4, 0x1c8a9c62 },
75 { XFER_UDMA_3, 0x1c8e9c62 },
76 { XFER_UDMA_2, 0x1c929c62 },
77 { XFER_UDMA_1, 0x1c9a9c62 },
78 { XFER_UDMA_0, 0x1c829c62 },
80 { XFER_MW_DMA_2, 0x2c829c62 },
81 { XFER_MW_DMA_1, 0x2c829c66 },
82 { XFER_MW_DMA_0, 0x2c829d2e },
84 { XFER_PIO_4, 0x0c829c62 },
85 { XFER_PIO_3, 0x0c829c84 },
86 { XFER_PIO_2, 0x0c829ca6 },
87 { XFER_PIO_1, 0x0d029d26 },
88 { XFER_PIO_0, 0x0d029d5e },
92 * hpt3x2n_find_mode - reset the hpt3x2n bus
94 * @speed: transfer mode
96 * Return the 32bit register programming information for this channel
97 * that matches the speed provided. For the moment the clocks table
98 * is hard coded but easy to change. This will be needed if we use
102 static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
104 struct hpt_clock *clocks = hpt3x2n_clocks;
106 while(clocks->xfer_speed) {
107 if (clocks->xfer_speed == speed)
108 return clocks->timing;
112 return 0xffffffffU; /* silence compiler warning */
116 * hpt3x2n_cable_detect - Detect the cable type
117 * @ap: ATA port to detect on
119 * Return the cable type attached to this port
122 static int hpt3x2n_cable_detect(struct ata_port *ap)
125 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
127 pci_read_config_byte(pdev, 0x5B, &scr2);
128 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
130 udelay(10); /* debounce */
132 /* Cable register now active */
133 pci_read_config_byte(pdev, 0x5A, &ata66);
135 pci_write_config_byte(pdev, 0x5B, scr2);
137 if (ata66 & (2 >> ap->port_no))
138 return ATA_CBL_PATA40;
140 return ATA_CBL_PATA80;
144 * hpt3x2n_pre_reset - reset the hpt3x2n bus
145 * @link: ATA link to reset
146 * @deadline: deadline jiffies for the operation
148 * Perform the initial reset handling for the 3x2n series controllers.
149 * Reset the hardware and state machine,
152 static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline)
154 struct ata_port *ap = link->ap;
155 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
156 /* Reset the state machine */
157 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
160 return ata_sff_prereset(link, deadline);
163 static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev,
166 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
168 u32 reg, timing, mask;
171 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
172 addr2 = 0x51 + 4 * ap->port_no;
174 /* Fast interrupt prediction disable, hold off interrupt disable */
175 pci_read_config_byte(pdev, addr2, &fast);
177 pci_write_config_byte(pdev, addr2, fast);
179 /* Determine timing mask and find matching mode entry */
180 if (mode < XFER_MW_DMA_0)
182 else if (mode < XFER_UDMA_0)
187 timing = hpt3x2n_find_mode(ap, mode);
189 pci_read_config_dword(pdev, addr1, ®);
190 reg = (reg & ~mask) | (timing & mask);
191 pci_write_config_dword(pdev, addr1, reg);
195 * hpt3x2n_set_piomode - PIO setup
197 * @adev: device on the interface
199 * Perform PIO mode setup.
202 static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
204 hpt3x2n_set_mode(ap, adev, adev->pio_mode);
208 * hpt3x2n_set_dmamode - DMA timing setup
210 * @adev: Device being configured
212 * Set up the channel for MWDMA or UDMA modes.
215 static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
217 hpt3x2n_set_mode(ap, adev, adev->dma_mode);
221 * hpt3x2n_bmdma_end - DMA engine stop
224 * Clean up after the HPT3x2n and later DMA engine
227 static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
229 struct ata_port *ap = qc->ap;
230 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
231 int mscreg = 0x50 + 2 * ap->port_no;
232 u8 bwsr_stat, msc_stat;
234 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
235 pci_read_config_byte(pdev, mscreg, &msc_stat);
236 if (bwsr_stat & (1 << ap->port_no))
237 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
242 * hpt3x2n_set_clock - clock control
244 * @source: 0x21 or 0x23 for PLL or PCI sourced clock
246 * Switch the ATA bus clock between the PLL and PCI clock sources
247 * while correctly isolating the bus and resetting internal logic
249 * We must use the DPLL for
251 * - second channel UDMA7 (SATA ports) or higher
254 * or we will underclock the device and get reduced performance.
257 static void hpt3x2n_set_clock(struct ata_port *ap, int source)
259 void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8;
261 /* Tristate the bus */
262 iowrite8(0x80, bmdma+0x73);
263 iowrite8(0x80, bmdma+0x77);
265 /* Switch clock and reset channels */
266 iowrite8(source, bmdma+0x7B);
267 iowrite8(0xC0, bmdma+0x79);
269 /* Reset state machines, avoid enabling the disabled channels */
270 iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70);
271 iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74);
274 iowrite8(0x00, bmdma+0x79);
276 /* Reconnect channels to bus */
277 iowrite8(0x00, bmdma+0x73);
278 iowrite8(0x00, bmdma+0x77);
281 static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
283 long flags = (long)ap->host->private_data;
285 /* See if we should use the DPLL */
287 return USE_DPLL; /* Needed for write */
289 return USE_DPLL; /* Needed at 66Mhz */
293 static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc)
295 struct ata_port *ap = qc->ap;
296 struct ata_port *alt = ap->host->ports[ap->port_no ^ 1];
297 int rc, flags = (long)ap->host->private_data;
298 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
300 /* First apply the usual rules */
301 rc = ata_std_qc_defer(qc);
305 if ((flags & USE_DPLL) != dpll && alt->qc_active)
306 return ATA_DEFER_PORT;
310 static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
312 struct ata_port *ap = qc->ap;
313 int flags = (long)ap->host->private_data;
314 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
316 if ((flags & USE_DPLL) != dpll) {
319 ap->host->private_data = (void *)(long)flags;
321 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23);
323 return ata_bmdma_qc_issue(qc);
326 static struct scsi_host_template hpt3x2n_sht = {
327 ATA_BMDMA_SHT(DRV_NAME),
331 * Configuration for HPT3x2n.
334 static struct ata_port_operations hpt3x2n_port_ops = {
335 .inherits = &ata_bmdma_port_ops,
337 .bmdma_stop = hpt3x2n_bmdma_stop,
339 .qc_defer = hpt3x2n_qc_defer,
340 .qc_issue = hpt3x2n_qc_issue,
342 .cable_detect = hpt3x2n_cable_detect,
343 .set_piomode = hpt3x2n_set_piomode,
344 .set_dmamode = hpt3x2n_set_dmamode,
345 .prereset = hpt3x2n_pre_reset,
349 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop
352 * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
356 static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
362 for(tries = 0; tries < 0x5000; tries++) {
364 pci_read_config_byte(dev, 0x5b, ®5b);
366 /* See if it stays set */
367 for(tries = 0; tries < 0x1000; tries ++) {
368 pci_read_config_byte(dev, 0x5b, ®5b);
370 if ((reg5b & 0x80) == 0)
373 /* Turn off tuning, we have the DPLL set */
374 pci_read_config_dword(dev, 0x5c, ®5c);
375 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
379 /* Never went stable */
383 static int hpt3x2n_pci_clock(struct pci_dev *pdev)
387 unsigned long iobase = pci_resource_start(pdev, 4);
389 fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */
390 if ((fcnt >> 12) != 0xABCDE) {
391 printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n");
392 return 33; /* Not BIOS set */
396 freq = (fcnt * 77) / 192;
409 * hpt3x2n_init_one - Initialise an HPT37X/302
411 * @id: Entry in match table
413 * Initialise an HPT3x2n device. There are some interesting complications
414 * here. Firstly the chip may report 366 and be one of several variants.
415 * Secondly all the timings depend on the clock for the chip which we must
418 * This is the known chip mappings. It may be missing a couple of later
421 * Chip version PCI Rev Notes
422 * HPT372 4 (HPT366) 5 Other driver
423 * HPT372N 4 (HPT366) 6 UDMA133
424 * HPT372 5 (HPT372) 1 Other driver
425 * HPT372N 5 (HPT372) 2 UDMA133
426 * HPT302 6 (HPT302) * Other driver
427 * HPT302N 6 (HPT302) > 1 UDMA133
428 * HPT371 7 (HPT371) * Other driver
429 * HPT371N 7 (HPT371) > 1 UDMA133
430 * HPT374 8 (HPT374) * Other driver
431 * HPT372N 9 (HPT372N) * UDMA133
433 * (1) UDMA133 support depends on the bus clock
435 * To pin down HPT371N
438 static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
440 /* HPT372N and friends - UDMA133 */
441 static const struct ata_port_info info = {
442 .flags = ATA_FLAG_SLAVE_POSS,
443 .pio_mask = ATA_PIO4,
444 .mwdma_mask = ATA_MWDMA2,
445 .udma_mask = ATA_UDMA6,
446 .port_ops = &hpt3x2n_port_ops
448 const struct ata_port_info *ppi[] = { &info, NULL };
449 u8 rev = dev->revision;
451 unsigned int pci_mhz;
452 unsigned int f_low, f_high;
454 unsigned long iobase = pci_resource_start(dev, 4);
455 void *hpriv = (void *)USE_DPLL;
458 rc = pcim_enable_device(dev);
462 switch(dev->device) {
463 case PCI_DEVICE_ID_TTI_HPT366:
467 case PCI_DEVICE_ID_TTI_HPT371:
470 /* 371N if rev > 1 */
472 case PCI_DEVICE_ID_TTI_HPT372:
473 /* 372N if rev >= 2*/
477 case PCI_DEVICE_ID_TTI_HPT302:
481 case PCI_DEVICE_ID_TTI_HPT372N:
484 printk(KERN_ERR "pata_hpt3x2n: PCI table is bogus please report (%d).\n", dev->device);
488 /* Ok so this is a chip we support */
490 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
491 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
492 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
493 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
495 pci_read_config_byte(dev, 0x5A, &irqmask);
497 pci_write_config_byte(dev, 0x5a, irqmask);
500 * HPT371 chips physically have only one channel, the secondary one,
501 * but the primary channel registers do exist! Go figure...
502 * So, we manually disable the non-existing channel here
503 * (if the BIOS hasn't done this already).
505 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
507 pci_read_config_byte(dev, 0x50, &mcr1);
509 pci_write_config_byte(dev, 0x50, mcr1);
512 /* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
513 50 for UDMA100. Right now we always use 66 */
515 pci_mhz = hpt3x2n_pci_clock(dev);
517 f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */
518 f_high = f_low + 2; /* Tolerance */
520 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
522 pci_write_config_byte(dev, 0x5B, 0x21);
524 /* Unlike the 37x we don't try jiggling the frequency */
525 for(adjust = 0; adjust < 8; adjust++) {
526 if (hpt3xn_calibrate_dpll(dev))
528 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
531 printk(KERN_ERR "pata_hpt3x2n: DPLL did not stabilize!\n");
535 printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using 66MHz DPLL.\n",
537 /* Set our private data up. We only need a few flags so we use
540 hpriv = (void *)(PCI66 | USE_DPLL);
543 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
544 * the MISC. register to stretch the UltraDMA Tss timing.
545 * NOTE: This register is only writeable via I/O space.
547 if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
548 outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
550 /* Now kick off ATA set up */
551 return ata_pci_sff_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0);
554 static const struct pci_device_id hpt3x2n[] = {
555 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
556 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
557 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
558 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
559 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },
564 static struct pci_driver hpt3x2n_pci_driver = {
567 .probe = hpt3x2n_init_one,
568 .remove = ata_pci_remove_one
571 static int __init hpt3x2n_init(void)
573 return pci_register_driver(&hpt3x2n_pci_driver);
576 static void __exit hpt3x2n_exit(void)
578 pci_unregister_driver(&hpt3x2n_pci_driver);
581 MODULE_AUTHOR("Alan Cox");
582 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3x2n/30x");
583 MODULE_LICENSE("GPL");
584 MODULE_DEVICE_TABLE(pci, hpt3x2n);
585 MODULE_VERSION(DRV_VERSION);
587 module_init(hpt3x2n_init);
588 module_exit(hpt3x2n_exit);