2 * pata-legacy.c - Legacy port PATA/SATA controller driver.
3 * Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; see the file COPYING. If not, write to
17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
19 * An ATA driver for the legacy ATA ports.
22 * Opti 82C465/82C611 support: Data sheets at opti-inc.com
24 * Promise 20230/20620:
25 * http://www.ryston.cz/petr/vlb/pdc20230b.html
26 * http://www.ryston.cz/petr/vlb/pdc20230c.html
27 * http://www.ryston.cz/petr/vlb/pdc20630.html
29 * Unsupported but docs exist:
30 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
33 * This driver handles legacy (that is "ISA/VLB side") IDE ports found
34 * on PC class systems. There are three hybrid devices that are exceptions
35 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
36 * the MPIIX where the tuning is PCI side but the IDE is "ISA side".
38 * Specific support is included for the ht6560a/ht6560b/opti82c611a/
39 * opti82c465mv/promise 20230c/20630
41 * Use the autospeed and pio_mask options with:
42 * Appian ADI/2 aka CLPD7220 or AIC25VL01.
43 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
44 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
45 * Winbond W83759A, Promise PDC20230-B
47 * For now use autospeed and pio_mask as above with the W83759A. This may
51 * Merge existing pata_qdi driver
55 #include <linux/kernel.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/init.h>
59 #include <linux/blkdev.h>
60 #include <linux/delay.h>
61 #include <scsi/scsi_host.h>
62 #include <linux/ata.h>
63 #include <linux/libata.h>
64 #include <linux/platform_device.h>
66 #define DRV_NAME "pata_legacy"
67 #define DRV_VERSION "0.5.5"
72 module_param(all, int, 0444);
73 MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");
80 struct platform_device *platform_dev;
94 QDI6580DP = 9, /* Dual channel mode is different */
100 struct legacy_probe {
105 enum controller type;
106 unsigned long private;
109 struct legacy_controller {
111 struct ata_port_operations *ops;
112 unsigned int pio_mask;
114 int (*setup)(struct legacy_probe *probe, struct legacy_data *data);
117 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
119 static struct legacy_probe probe_list[NR_HOST];
120 static struct legacy_data legacy_data[NR_HOST];
121 static struct ata_host *legacy_host[NR_HOST];
122 static int nr_legacy_host;
125 static int probe_all; /* Set to check all ISA port ranges */
126 static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */
127 static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */
128 static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */
129 static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */
130 static int qdi; /* Set to probe QDI controllers */
131 static int autospeed; /* Chip present which snoops speed changes */
132 static int pio_mask = 0x1F; /* PIO range for autospeed devices */
133 static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */
136 * legacy_probe_add - Add interface to probe list
137 * @port: Controller port
139 * @type: Controller type
140 * @private: Controller specific info
142 * Add an entry into the probe list for ATA controllers. This is used
143 * to add the default ISA slots and then to build up the table
144 * further according to other ISA/VLB/Weird device scans
146 * An I/O port list is used to keep ordering stable and sane, as we
147 * don't have any good way to talk about ordering otherwise
150 static int legacy_probe_add(unsigned long port, unsigned int irq,
151 enum controller type, unsigned long private)
153 struct legacy_probe *lp = &probe_list[0];
155 struct legacy_probe *free = NULL;
157 for (i = 0; i < NR_HOST; i++) {
158 if (lp->port == 0 && free == NULL)
160 /* Matching port, or the correct slot for ordering */
161 if (lp->port == port || legacy_port[i] == port) {
168 printk(KERN_ERR "pata_legacy: Too many interfaces.\n");
171 /* Fill in the entry for later probing */
175 free->private = private;
181 * legacy_set_mode - mode setting
183 * @unused: Device that failed when error is returned
185 * Use a non standard set_mode function. We don't want to be tuned.
187 * The BIOS configured everything. Our job is not to fiddle. Just use
188 * whatever PIO the hardware is using and leave it at that. When we
189 * get some kind of nice user driven API for control then we can
190 * expand on this as per hdparm in the base kernel.
193 static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)
195 struct ata_device *dev;
197 ata_link_for_each_dev(dev, link) {
198 if (ata_dev_enabled(dev)) {
199 ata_dev_printk(dev, KERN_INFO,
200 "configured for PIO\n");
201 dev->pio_mode = XFER_PIO_0;
202 dev->xfer_mode = XFER_PIO_0;
203 dev->xfer_shift = ATA_SHIFT_PIO;
204 dev->flags |= ATA_DFLAG_PIO;
210 static struct scsi_host_template legacy_sht = {
211 .module = THIS_MODULE,
213 .ioctl = ata_scsi_ioctl,
214 .queuecommand = ata_scsi_queuecmd,
215 .can_queue = ATA_DEF_QUEUE,
216 .this_id = ATA_SHT_THIS_ID,
217 .sg_tablesize = LIBATA_MAX_PRD,
218 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
219 .emulated = ATA_SHT_EMULATED,
220 .use_clustering = ATA_SHT_USE_CLUSTERING,
221 .proc_name = DRV_NAME,
222 .dma_boundary = ATA_DMA_BOUNDARY,
223 .slave_configure = ata_scsi_slave_config,
224 .slave_destroy = ata_scsi_slave_destroy,
225 .bios_param = ata_std_bios_param,
229 * These ops are used if the user indicates the hardware
230 * snoops the commands to decide on the mode and handles the
231 * mode selection "magically" itself. Several legacy controllers
232 * do this. The mode range can be set if it is not 0x1F by setting
236 static struct ata_port_operations simple_port_ops = {
237 .tf_load = ata_tf_load,
238 .tf_read = ata_tf_read,
239 .check_status = ata_check_status,
240 .exec_command = ata_exec_command,
241 .dev_select = ata_std_dev_select,
243 .freeze = ata_bmdma_freeze,
244 .thaw = ata_bmdma_thaw,
245 .error_handler = ata_bmdma_error_handler,
246 .post_internal_cmd = ata_bmdma_post_internal_cmd,
247 .cable_detect = ata_cable_40wire,
249 .qc_prep = ata_qc_prep,
250 .qc_issue = ata_qc_issue_prot,
252 .data_xfer = ata_data_xfer_noirq,
254 .irq_handler = ata_interrupt,
255 .irq_clear = ata_bmdma_irq_clear,
256 .irq_on = ata_irq_on,
258 .port_start = ata_sff_port_start,
261 static struct ata_port_operations legacy_port_ops = {
262 .set_mode = legacy_set_mode,
264 .tf_load = ata_tf_load,
265 .tf_read = ata_tf_read,
266 .check_status = ata_check_status,
267 .exec_command = ata_exec_command,
268 .dev_select = ata_std_dev_select,
269 .cable_detect = ata_cable_40wire,
271 .freeze = ata_bmdma_freeze,
272 .thaw = ata_bmdma_thaw,
273 .error_handler = ata_bmdma_error_handler,
274 .post_internal_cmd = ata_bmdma_post_internal_cmd,
276 .qc_prep = ata_qc_prep,
277 .qc_issue = ata_qc_issue_prot,
279 .data_xfer = ata_data_xfer_noirq,
281 .irq_handler = ata_interrupt,
282 .irq_clear = ata_bmdma_irq_clear,
283 .irq_on = ata_irq_on,
285 .port_start = ata_sff_port_start,
289 * Promise 20230C and 20620 support
291 * This controller supports PIO0 to PIO2. We set PIO timings
292 * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA
293 * support is weird being DMA to controller and PIO'd to the host
297 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
300 int pio = adev->pio_mode - XFER_PIO_0;
304 /* Safe as UP only. Force I/Os to occur together */
306 local_irq_save(flags);
308 /* Unlock the control interface */
311 outb(inb(0x1F2) | 0x80, 0x1F2);
318 while ((inb(0x1F2) & 0x80) && --tries);
320 local_irq_restore(flags);
322 outb(inb(0x1F4) & 0x07, 0x1F4);
325 rt &= 0x07 << (3 * adev->devno);
327 rt |= (1 + 3 * pio) << (3 * adev->devno);
330 outb(inb(0x1F2) | 0x01, 0x1F2);
336 static unsigned int pdc_data_xfer_vlb(struct ata_device *dev,
337 unsigned char *buf, unsigned int buflen, int rw)
339 if (ata_id_has_dword_io(dev->id)) {
340 struct ata_port *ap = dev->link->ap;
341 int slop = buflen & 3;
344 local_irq_save(flags);
346 /* Perform the 32bit I/O synchronization sequence */
347 ioread8(ap->ioaddr.nsect_addr);
348 ioread8(ap->ioaddr.nsect_addr);
349 ioread8(ap->ioaddr.nsect_addr);
353 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
355 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
357 if (unlikely(slop)) {
360 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
361 memcpy(buf + buflen - slop, &pad, slop);
363 memcpy(&pad, buf + buflen - slop, slop);
364 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
368 local_irq_restore(flags);
370 buflen = ata_data_xfer_noirq(dev, buf, buflen, rw);
375 static struct ata_port_operations pdc20230_port_ops = {
376 .set_piomode = pdc20230_set_piomode,
378 .tf_load = ata_tf_load,
379 .tf_read = ata_tf_read,
380 .check_status = ata_check_status,
381 .exec_command = ata_exec_command,
382 .dev_select = ata_std_dev_select,
384 .freeze = ata_bmdma_freeze,
385 .thaw = ata_bmdma_thaw,
386 .error_handler = ata_bmdma_error_handler,
387 .post_internal_cmd = ata_bmdma_post_internal_cmd,
388 .cable_detect = ata_cable_40wire,
390 .qc_prep = ata_qc_prep,
391 .qc_issue = ata_qc_issue_prot,
393 .data_xfer = pdc_data_xfer_vlb,
395 .irq_handler = ata_interrupt,
396 .irq_clear = ata_bmdma_irq_clear,
397 .irq_on = ata_irq_on,
399 .port_start = ata_sff_port_start,
403 * Holtek 6560A support
405 * This controller supports PIO0 to PIO2 (no IORDY even though higher
406 * timings can be loaded).
409 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
414 /* Get the timing data in cycles. For now play safe at 50Mhz */
415 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
417 active = FIT(t.active, 2, 15);
418 recover = FIT(t.recover, 4, 15);
425 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
426 ioread8(ap->ioaddr.status_addr);
429 static struct ata_port_operations ht6560a_port_ops = {
430 .set_piomode = ht6560a_set_piomode,
432 .tf_load = ata_tf_load,
433 .tf_read = ata_tf_read,
434 .check_status = ata_check_status,
435 .exec_command = ata_exec_command,
436 .dev_select = ata_std_dev_select,
438 .freeze = ata_bmdma_freeze,
439 .thaw = ata_bmdma_thaw,
440 .error_handler = ata_bmdma_error_handler,
441 .post_internal_cmd = ata_bmdma_post_internal_cmd,
442 .cable_detect = ata_cable_40wire,
444 .qc_prep = ata_qc_prep,
445 .qc_issue = ata_qc_issue_prot,
447 .data_xfer = ata_data_xfer, /* Check vlb/noirq */
449 .irq_handler = ata_interrupt,
450 .irq_clear = ata_bmdma_irq_clear,
451 .irq_on = ata_irq_on,
453 .port_start = ata_sff_port_start,
457 * Holtek 6560B support
459 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO
460 * setting unless we see an ATAPI device in which case we force it off.
462 * FIXME: need to implement 2nd channel support.
465 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
470 /* Get the timing data in cycles. For now play safe at 50Mhz */
471 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
473 active = FIT(t.active, 2, 15);
474 recover = FIT(t.recover, 2, 16);
482 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
484 if (adev->class != ATA_DEV_ATA) {
485 u8 rconf = inb(0x3E6);
491 ioread8(ap->ioaddr.status_addr);
494 static struct ata_port_operations ht6560b_port_ops = {
495 .set_piomode = ht6560b_set_piomode,
497 .tf_load = ata_tf_load,
498 .tf_read = ata_tf_read,
499 .check_status = ata_check_status,
500 .exec_command = ata_exec_command,
501 .dev_select = ata_std_dev_select,
503 .freeze = ata_bmdma_freeze,
504 .thaw = ata_bmdma_thaw,
505 .error_handler = ata_bmdma_error_handler,
506 .post_internal_cmd = ata_bmdma_post_internal_cmd,
507 .cable_detect = ata_cable_40wire,
509 .qc_prep = ata_qc_prep,
510 .qc_issue = ata_qc_issue_prot,
512 .data_xfer = ata_data_xfer, /* FIXME: Check 32bit and noirq */
514 .irq_handler = ata_interrupt,
515 .irq_clear = ata_bmdma_irq_clear,
516 .irq_on = ata_irq_on,
518 .port_start = ata_sff_port_start,
522 * Opti core chipset helpers
526 * opti_syscfg - read OPTI chipset configuration
527 * @reg: Configuration register to read
529 * Returns the value of an OPTI system board configuration register.
532 static u8 opti_syscfg(u8 reg)
537 /* Uniprocessor chipset and must force cycles adjancent */
538 local_irq_save(flags);
541 local_irq_restore(flags);
548 * This controller supports PIO0 to PIO3.
551 static void opti82c611a_set_piomode(struct ata_port *ap,
552 struct ata_device *adev)
554 u8 active, recover, setup;
556 struct ata_device *pair = ata_dev_pair(adev);
558 int khz[4] = { 50000, 40000, 33000, 25000 };
561 /* Enter configuration mode */
562 ioread16(ap->ioaddr.error_addr);
563 ioread16(ap->ioaddr.error_addr);
564 iowrite8(3, ap->ioaddr.nsect_addr);
566 /* Read VLB clock strapping */
567 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
569 /* Get the timing data in cycles */
570 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
572 /* Setup timing is shared */
574 struct ata_timing tp;
575 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
577 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
580 active = FIT(t.active, 2, 17) - 2;
581 recover = FIT(t.recover, 1, 16) - 1;
582 setup = FIT(t.setup, 1, 4) - 1;
584 /* Select the right timing bank for write timing */
585 rc = ioread8(ap->ioaddr.lbal_addr);
587 rc |= (adev->devno << 7);
588 iowrite8(rc, ap->ioaddr.lbal_addr);
590 /* Write the timings */
591 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
593 /* Select the right bank for read timings, also
594 load the shared timings for address */
595 rc = ioread8(ap->ioaddr.device_addr);
597 rc |= adev->devno; /* Index select */
598 rc |= (setup << 4) | 0x04;
599 iowrite8(rc, ap->ioaddr.device_addr);
601 /* Load the read timings */
602 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
604 /* Ensure the timing register mode is right */
605 rc = ioread8(ap->ioaddr.lbal_addr);
608 iowrite8(rc, ap->ioaddr.lbal_addr);
610 /* Exit command mode */
611 iowrite8(0x83, ap->ioaddr.nsect_addr);
615 static struct ata_port_operations opti82c611a_port_ops = {
616 .set_piomode = opti82c611a_set_piomode,
618 .tf_load = ata_tf_load,
619 .tf_read = ata_tf_read,
620 .check_status = ata_check_status,
621 .exec_command = ata_exec_command,
622 .dev_select = ata_std_dev_select,
624 .freeze = ata_bmdma_freeze,
625 .thaw = ata_bmdma_thaw,
626 .error_handler = ata_bmdma_error_handler,
627 .post_internal_cmd = ata_bmdma_post_internal_cmd,
628 .cable_detect = ata_cable_40wire,
630 .qc_prep = ata_qc_prep,
631 .qc_issue = ata_qc_issue_prot,
633 .data_xfer = ata_data_xfer,
635 .irq_handler = ata_interrupt,
636 .irq_clear = ata_bmdma_irq_clear,
637 .irq_on = ata_irq_on,
639 .port_start = ata_sff_port_start,
645 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB
646 * version is dual channel but doesn't have a lot of unique registers.
649 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
651 u8 active, recover, setup;
653 struct ata_device *pair = ata_dev_pair(adev);
655 int khz[4] = { 50000, 40000, 33000, 25000 };
660 sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */
662 /* Enter configuration mode */
663 ioread16(ap->ioaddr.error_addr);
664 ioread16(ap->ioaddr.error_addr);
665 iowrite8(3, ap->ioaddr.nsect_addr);
667 /* Read VLB clock strapping */
668 clock = 1000000000 / khz[sysclk];
670 /* Get the timing data in cycles */
671 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
673 /* Setup timing is shared */
675 struct ata_timing tp;
676 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
678 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
681 active = FIT(t.active, 2, 17) - 2;
682 recover = FIT(t.recover, 1, 16) - 1;
683 setup = FIT(t.setup, 1, 4) - 1;
685 /* Select the right timing bank for write timing */
686 rc = ioread8(ap->ioaddr.lbal_addr);
688 rc |= (adev->devno << 7);
689 iowrite8(rc, ap->ioaddr.lbal_addr);
691 /* Write the timings */
692 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
694 /* Select the right bank for read timings, also
695 load the shared timings for address */
696 rc = ioread8(ap->ioaddr.device_addr);
698 rc |= adev->devno; /* Index select */
699 rc |= (setup << 4) | 0x04;
700 iowrite8(rc, ap->ioaddr.device_addr);
702 /* Load the read timings */
703 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
705 /* Ensure the timing register mode is right */
706 rc = ioread8(ap->ioaddr.lbal_addr);
709 iowrite8(rc, ap->ioaddr.lbal_addr);
711 /* Exit command mode */
712 iowrite8(0x83, ap->ioaddr.nsect_addr);
714 /* We need to know this for quad device on the MVB */
715 ap->host->private_data = ap;
719 * opt82c465mv_qc_issue_prot - command issue
720 * @qc: command pending
722 * Called when the libata layer is about to issue a command. We wrap
723 * this interface so that we can load the correct ATA timings. The
724 * MVB has a single set of timing registers and these are shared
725 * across channels. As there are two registers we really ought to
726 * track the last two used values as a sort of register window. For
727 * now we just reload on a channel switch. On the single channel
728 * setup this condition never fires so we do nothing extra.
730 * FIXME: dual channel needs ->serialize support
733 static unsigned int opti82c46x_qc_issue_prot(struct ata_queued_cmd *qc)
735 struct ata_port *ap = qc->ap;
736 struct ata_device *adev = qc->dev;
738 /* If timings are set and for the wrong channel (2nd test is
739 due to a libata shortcoming and will eventually go I hope) */
740 if (ap->host->private_data != ap->host
741 && ap->host->private_data != NULL)
742 opti82c46x_set_piomode(ap, adev);
744 return ata_qc_issue_prot(qc);
747 static struct ata_port_operations opti82c46x_port_ops = {
748 .set_piomode = opti82c46x_set_piomode,
750 .tf_load = ata_tf_load,
751 .tf_read = ata_tf_read,
752 .check_status = ata_check_status,
753 .exec_command = ata_exec_command,
754 .dev_select = ata_std_dev_select,
756 .freeze = ata_bmdma_freeze,
757 .thaw = ata_bmdma_thaw,
758 .error_handler = ata_bmdma_error_handler,
759 .post_internal_cmd = ata_bmdma_post_internal_cmd,
760 .cable_detect = ata_cable_40wire,
762 .qc_prep = ata_qc_prep,
763 .qc_issue = opti82c46x_qc_issue_prot,
765 .data_xfer = ata_data_xfer,
767 .irq_handler = ata_interrupt,
768 .irq_clear = ata_bmdma_irq_clear,
769 .irq_on = ata_irq_on,
771 .port_start = ata_sff_port_start,
774 static void qdi6500_set_piomode(struct ata_port *ap, struct ata_device *adev)
777 struct legacy_data *qdi = ap->host->private_data;
778 int active, recovery;
781 /* Get the timing data in cycles */
782 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
785 active = 8 - FIT(t.active, 1, 8);
786 recovery = 18 - FIT(t.recover, 3, 18);
788 active = 9 - FIT(t.active, 2, 9);
789 recovery = 15 - FIT(t.recover, 0, 15);
791 timing = (recovery << 4) | active | 0x08;
793 qdi->clock[adev->devno] = timing;
795 outb(timing, qdi->timing);
799 * qdi6580dp_set_piomode - PIO setup for dual channel
802 * @irq: interrupt line
804 * In dual channel mode the 6580 has one clock per channel and we have
805 * to software clockswitch in qc_issue_prot.
808 static void qdi6580dp_set_piomode(struct ata_port *ap, struct ata_device *adev)
811 struct legacy_data *qdi = ap->host->private_data;
812 int active, recovery;
815 /* Get the timing data in cycles */
816 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
819 active = 8 - FIT(t.active, 1, 8);
820 recovery = 18 - FIT(t.recover, 3, 18);
822 active = 9 - FIT(t.active, 2, 9);
823 recovery = 15 - FIT(t.recover, 0, 15);
825 timing = (recovery << 4) | active | 0x08;
827 qdi->clock[adev->devno] = timing;
829 outb(timing, qdi->timing + 2 * ap->port_no);
831 if (adev->class != ATA_DEV_ATA)
832 outb(0x5F, qdi->timing + 3);
836 * qdi6580_set_piomode - PIO setup for single channel
840 * In single channel mode the 6580 has one clock per device and we can
841 * avoid the requirement to clock switch. We also have to load the timing
842 * into the right clock according to whether we are master or slave.
845 static void qdi6580_set_piomode(struct ata_port *ap, struct ata_device *adev)
848 struct legacy_data *qdi = ap->host->private_data;
849 int active, recovery;
852 /* Get the timing data in cycles */
853 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
856 active = 8 - FIT(t.active, 1, 8);
857 recovery = 18 - FIT(t.recover, 3, 18);
859 active = 9 - FIT(t.active, 2, 9);
860 recovery = 15 - FIT(t.recover, 0, 15);
862 timing = (recovery << 4) | active | 0x08;
863 qdi->clock[adev->devno] = timing;
864 outb(timing, qdi->timing + 2 * adev->devno);
866 if (adev->class != ATA_DEV_ATA)
867 outb(0x5F, qdi->timing + 3);
871 * qdi_qc_issue_prot - command issue
872 * @qc: command pending
874 * Called when the libata layer is about to issue a command. We wrap
875 * this interface so that we can load the correct ATA timings.
878 static unsigned int qdi_qc_issue_prot(struct ata_queued_cmd *qc)
880 struct ata_port *ap = qc->ap;
881 struct ata_device *adev = qc->dev;
882 struct legacy_data *qdi = ap->host->private_data;
884 if (qdi->clock[adev->devno] != qdi->last) {
885 if (adev->pio_mode) {
886 qdi->last = qdi->clock[adev->devno];
887 outb(qdi->clock[adev->devno], qdi->timing +
891 return ata_qc_issue_prot(qc);
894 /* For the 6580 can we flip the FIFO on/off at this point ? */
896 static unsigned int qdi_data_xfer(struct ata_device *adev, unsigned char *buf,
897 unsigned int buflen, int rw)
899 struct ata_port *ap = adev->link->ap;
900 int slop = buflen & 3;
902 if (ata_id_has_dword_io(adev->id)) {
904 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
906 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
908 if (unlikely(slop)) {
911 memcpy(&pad, buf + buflen - slop, slop);
912 pad = le32_to_cpu(pad);
913 iowrite32(pad, ap->ioaddr.data_addr);
915 pad = ioread32(ap->ioaddr.data_addr);
916 pad = cpu_to_le32(pad);
917 memcpy(buf + buflen - slop, &pad, slop);
920 return (buflen + 3) & ~3;
922 return ata_data_xfer(adev, buf, buflen, rw);
925 static struct ata_port_operations qdi6500_port_ops = {
926 .set_piomode = qdi6500_set_piomode,
928 .tf_load = ata_tf_load,
929 .tf_read = ata_tf_read,
930 .check_status = ata_check_status,
931 .exec_command = ata_exec_command,
932 .dev_select = ata_std_dev_select,
934 .freeze = ata_bmdma_freeze,
935 .thaw = ata_bmdma_thaw,
936 .error_handler = ata_bmdma_error_handler,
937 .post_internal_cmd = ata_bmdma_post_internal_cmd,
938 .cable_detect = ata_cable_40wire,
940 .qc_prep = ata_qc_prep,
941 .qc_issue = qdi_qc_issue_prot,
943 .data_xfer = qdi_data_xfer,
945 .irq_handler = ata_interrupt,
946 .irq_clear = ata_bmdma_irq_clear,
947 .irq_on = ata_irq_on,
949 .port_start = ata_sff_port_start,
952 static struct ata_port_operations qdi6580_port_ops = {
953 .set_piomode = qdi6580_set_piomode,
955 .tf_load = ata_tf_load,
956 .tf_read = ata_tf_read,
957 .check_status = ata_check_status,
958 .exec_command = ata_exec_command,
959 .dev_select = ata_std_dev_select,
961 .freeze = ata_bmdma_freeze,
962 .thaw = ata_bmdma_thaw,
963 .error_handler = ata_bmdma_error_handler,
964 .post_internal_cmd = ata_bmdma_post_internal_cmd,
965 .cable_detect = ata_cable_40wire,
967 .qc_prep = ata_qc_prep,
968 .qc_issue = ata_qc_issue_prot,
970 .data_xfer = qdi_data_xfer,
972 .irq_handler = ata_interrupt,
973 .irq_clear = ata_bmdma_irq_clear,
974 .irq_on = ata_irq_on,
976 .port_start = ata_sff_port_start,
979 static struct ata_port_operations qdi6580dp_port_ops = {
980 .set_piomode = qdi6580dp_set_piomode,
982 .tf_load = ata_tf_load,
983 .tf_read = ata_tf_read,
984 .check_status = ata_check_status,
985 .exec_command = ata_exec_command,
986 .dev_select = ata_std_dev_select,
988 .freeze = ata_bmdma_freeze,
989 .thaw = ata_bmdma_thaw,
990 .error_handler = ata_bmdma_error_handler,
991 .post_internal_cmd = ata_bmdma_post_internal_cmd,
992 .cable_detect = ata_cable_40wire,
994 .qc_prep = ata_qc_prep,
995 .qc_issue = qdi_qc_issue_prot,
997 .data_xfer = qdi_data_xfer,
999 .irq_handler = ata_interrupt,
1000 .irq_clear = ata_bmdma_irq_clear,
1001 .irq_on = ata_irq_on,
1003 .port_start = ata_sff_port_start,
1006 static struct legacy_controller controllers[] = {
1007 {"BIOS", &legacy_port_ops, 0x1F,
1008 ATA_FLAG_NO_IORDY, NULL },
1009 {"Snooping", &simple_port_ops, 0x1F,
1011 {"PDC20230", &pdc20230_port_ops, 0x7,
1012 ATA_FLAG_NO_IORDY, NULL },
1013 {"HT6560A", &ht6560a_port_ops, 0x07,
1014 ATA_FLAG_NO_IORDY, NULL },
1015 {"HT6560B", &ht6560b_port_ops, 0x1F,
1016 ATA_FLAG_NO_IORDY, NULL },
1017 {"OPTI82C611A", &opti82c611a_port_ops, 0x0F,
1019 {"OPTI82C46X", &opti82c46x_port_ops, 0x0F,
1021 {"QDI6500", &qdi6500_port_ops, 0x07,
1022 ATA_FLAG_NO_IORDY, NULL },
1023 {"QDI6580", &qdi6580_port_ops, 0x1F,
1025 {"QDI6580DP", &qdi6580dp_port_ops, 0x1F,
1030 * probe_chip_type - Discover controller
1031 * @probe: Probe entry to check
1033 * Probe an ATA port and identify the type of controller. We don't
1034 * check if the controller appears to be driveless at this point.
1037 static int probe_chip_type(struct legacy_probe *probe)
1039 int mask = 1 << probe->slot;
1041 if (probe->port == 0x1F0) {
1042 unsigned long flags;
1043 local_irq_save(flags);
1045 outb(inb(0x1F2) | 0x80, 0x1F2);
1053 if ((inb(0x1F2) & 0x80) == 0) {
1054 /* PDC20230c or 20630 ? */
1055 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller"
1059 local_irq_restore(flags);
1065 if (inb(0x1F2) == 0x00)
1066 printk(KERN_INFO "PDC20230-B VLB ATA "
1067 "controller detected.\n");
1068 local_irq_restore(flags);
1071 local_irq_restore(flags);
1078 if (opti82c611a & mask)
1080 if (opti82c46x & mask)
1082 if (autospeed & mask)
1089 * legacy_init_one - attach a legacy interface
1092 * Register an ISA bus IDE interface. Such interfaces are PIO and we
1093 * assume do not support IRQ sharing.
1096 static __init int legacy_init_one(struct legacy_probe *probe)
1098 struct legacy_controller *controller = &controllers[probe->type];
1099 int pio_modes = controller->pio_mask;
1100 unsigned long io = probe->port;
1101 u32 mask = (1 << probe->slot);
1102 struct ata_port_operations *ops = controller->ops;
1103 struct legacy_data *ld = &legacy_data[probe->slot];
1104 struct ata_host *host = NULL;
1105 struct ata_port *ap;
1106 struct platform_device *pdev;
1107 struct ata_device *dev;
1108 void __iomem *io_addr, *ctrl_addr;
1109 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
1112 iordy |= controller->flags;
1114 pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0);
1116 return PTR_ERR(pdev);
1119 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
1120 devm_request_region(&pdev->dev, io + 0x0206, 1,
1121 "pata_legacy") == NULL)
1125 io_addr = devm_ioport_map(&pdev->dev, io, 8);
1126 ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1);
1127 if (!io_addr || !ctrl_addr)
1129 if (controller->setup)
1130 if (controller->setup(probe, ld) < 0)
1132 host = ata_host_alloc(&pdev->dev, 1);
1135 ap = host->ports[0];
1138 ap->pio_mask = pio_modes;
1139 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;
1140 ap->ioaddr.cmd_addr = io_addr;
1141 ap->ioaddr.altstatus_addr = ctrl_addr;
1142 ap->ioaddr.ctl_addr = ctrl_addr;
1143 ata_std_ports(&ap->ioaddr);
1144 ap->private_data = ld;
1146 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206);
1148 ret = ata_host_activate(host, probe->irq, ata_interrupt, 0,
1152 ld->platform_dev = pdev;
1154 /* Nothing found means we drop the port as its probably not there */
1157 ata_link_for_each_dev(dev, &ap->link) {
1158 if (!ata_dev_absent(dev)) {
1159 legacy_host[probe->slot] = host;
1160 ld->platform_dev = pdev;
1166 ata_host_detach(host);
1167 /* FIXME: use devm for this */
1169 release_region(ld->timing, 2);
1170 platform_device_unregister(pdev);
1175 * legacy_check_special_cases - ATA special cases
1176 * @p: PCI device to check
1177 * @master: set this if we find an ATA master
1178 * @master: set this if we find an ATA secondary
1180 * A small number of vendors implemented early PCI ATA interfaces
1181 * on bridge logic without the ATA interface being PCI visible.
1182 * Where we have a matching PCI driver we must skip the relevant
1183 * device here. If we don't know about it then the legacy driver
1184 * is the right driver anyway.
1187 static void legacy_check_special_cases(struct pci_dev *p, int *primary,
1190 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
1191 if (p->vendor == 0x1078 && p->device == 0x0000) {
1192 *primary = *secondary = 1;
1195 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
1196 if (p->vendor == 0x1078 && p->device == 0x0002) {
1197 *primary = *secondary = 1;
1200 /* Intel MPIIX - PIO ATA on non PCI side of bridge */
1201 if (p->vendor == 0x8086 && p->device == 0x1234) {
1203 pci_read_config_word(p, 0x6C, &r);
1205 /* ATA port enabled */
1215 static __init void probe_opti_vlb(void)
1217 /* If an OPTI 82C46X is present find out where the channels are */
1218 static const char *optis[4] = {
1223 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
1225 opti82c46x = 3; /* Assume master and slave first */
1226 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n",
1229 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
1230 ctrl = opti_syscfg(0xAC);
1231 /* Check enabled and this port is the 465MV port. On the
1232 MVB we may have two channels */
1235 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1236 legacy_probe_add(0x170, 15, OPTI46X, 0);
1239 legacy_probe_add(0x170, 15, OPTI46X, 0);
1241 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1243 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1246 static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port)
1248 static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
1249 /* Check card type */
1250 if ((r & 0xF0) == 0xC0) {
1251 /* QD6500: single channel */
1254 release_region(port, 2);
1257 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1260 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
1261 /* QD6580: dual channel */
1262 if (!request_region(port + 2 , 2, "pata_qdi")) {
1263 release_region(port, 2);
1266 res = inb(port + 3);
1267 /* Single channel mode ? */
1269 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1271 else { /* Dual channel mode */
1272 legacy_probe_add(0x1F0, 14, QDI6580DP, port);
1273 /* port + 0x02, r & 0x04 */
1274 legacy_probe_add(0x170, 15, QDI6580DP, port + 2);
1279 static __init void probe_qdi_vlb(void)
1281 unsigned long flags;
1282 static const unsigned long qd_port[2] = { 0x30, 0xB0 };
1286 * Check each possible QD65xx base address
1289 for (i = 0; i < 2; i++) {
1290 unsigned long port = qd_port[i];
1294 if (request_region(port, 2, "pata_qdi")) {
1295 /* Check for a card */
1296 local_irq_save(flags);
1297 /* I have no h/w that needs this delay but it
1298 is present in the historic code */
1307 local_irq_restore(flags);
1311 release_region(port, 2);
1314 /* Passes the presence test */
1317 /* Check port agrees with port set */
1318 if ((r & 2) >> 1 != i) {
1319 release_region(port, 2);
1322 qdi65_identify_port(r, res, port);
1328 * legacy_init - attach legacy interfaces
1330 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
1331 * Right now we do not scan the ide0 and ide1 address but should do so
1332 * for non PCI systems or systems with no PCI IDE legacy mode devices.
1333 * If you fix that note there are special cases to consider like VLB
1334 * drivers and CS5510/20.
1337 static __init int legacy_init(void)
1343 int pci_present = 0;
1344 struct legacy_probe *pl = &probe_list[0];
1347 struct pci_dev *p = NULL;
1349 for_each_pci_dev(p) {
1351 /* Check for any overlap of the system ATA mappings. Native
1352 mode controllers stuck on these addresses or some devices
1353 in 'raid' mode won't be found by the storage class test */
1354 for (r = 0; r < 6; r++) {
1355 if (pci_resource_start(p, r) == 0x1f0)
1357 if (pci_resource_start(p, r) == 0x170)
1360 /* Check for special cases */
1361 legacy_check_special_cases(p, &primary, &secondary);
1363 /* If PCI bus is present then don't probe for tertiary
1368 if (primary == 0 || all)
1369 legacy_probe_add(0x1F0, 14, UNKNOWN, 0);
1370 if (secondary == 0 || all)
1371 legacy_probe_add(0x170, 15, UNKNOWN, 0);
1373 if (probe_all || !pci_present) {
1374 /* ISA/VLB extra ports */
1375 legacy_probe_add(0x1E8, 11, UNKNOWN, 0);
1376 legacy_probe_add(0x168, 10, UNKNOWN, 0);
1377 legacy_probe_add(0x1E0, 8, UNKNOWN, 0);
1378 legacy_probe_add(0x160, 12, UNKNOWN, 0);
1387 for (i = 0; i < NR_HOST; i++, pl++) {
1390 if (pl->type == UNKNOWN)
1391 pl->type = probe_chip_type(pl);
1393 if (legacy_init_one(pl) == 0)
1401 static __exit void legacy_exit(void)
1405 for (i = 0; i < nr_legacy_host; i++) {
1406 struct legacy_data *ld = &legacy_data[i];
1407 ata_host_detach(legacy_host[i]);
1408 platform_device_unregister(ld->platform_dev);
1410 release_region(ld->timing, 2);
1414 MODULE_AUTHOR("Alan Cox");
1415 MODULE_DESCRIPTION("low-level driver for legacy ATA");
1416 MODULE_LICENSE("GPL");
1417 MODULE_VERSION(DRV_VERSION);
1419 module_param(probe_all, int, 0);
1420 module_param(autospeed, int, 0);
1421 module_param(ht6560a, int, 0);
1422 module_param(ht6560b, int, 0);
1423 module_param(opti82c611a, int, 0);
1424 module_param(opti82c46x, int, 0);
1425 module_param(qdi, int, 0);
1426 module_param(pio_mask, int, 0);
1427 module_param(iordy_mask, int, 0);
1429 module_init(legacy_init);
1430 module_exit(legacy_exit);