2 * sata_mv.c - Marvell SATA support
4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
8 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 * --> Develop a low-power-consumption strategy, and implement it.
33 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
35 * --> [Experiment, Marvell value added] Is it possible to use target
36 * mode to cross-connect two Linux boxes with Marvell cards? If so,
37 * creating LibATA target mode support would be very interesting.
39 * Target mode, for those without docs, is the ability to directly
40 * connect two SATA ports.
44 * 80x1-B2 errata PCI#11:
46 * Users of the 6041/6081 Rev.B2 chips (current is C0)
47 * should be careful to insert those cards only onto PCI-X bus #0,
48 * and only in device slots 0..7, not higher. The chips may not
49 * work correctly otherwise (note: this is a pretty rare condition).
52 #include <linux/kernel.h>
53 #include <linux/module.h>
54 #include <linux/pci.h>
55 #include <linux/init.h>
56 #include <linux/blkdev.h>
57 #include <linux/delay.h>
58 #include <linux/interrupt.h>
59 #include <linux/dmapool.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/device.h>
62 #include <linux/clk.h>
63 #include <linux/platform_device.h>
64 #include <linux/ata_platform.h>
65 #include <linux/mbus.h>
66 #include <linux/bitops.h>
67 #include <linux/gfp.h>
68 #include <scsi/scsi_host.h>
69 #include <scsi/scsi_cmnd.h>
70 #include <scsi/scsi_device.h>
71 #include <linux/libata.h>
73 #define DRV_NAME "sata_mv"
74 #define DRV_VERSION "1.28"
82 module_param(msi, int, S_IRUGO);
83 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
86 static int irq_coalescing_io_count;
87 module_param(irq_coalescing_io_count, int, S_IRUGO);
88 MODULE_PARM_DESC(irq_coalescing_io_count,
89 "IRQ coalescing I/O count threshold (0..255)");
91 static int irq_coalescing_usecs;
92 module_param(irq_coalescing_usecs, int, S_IRUGO);
93 MODULE_PARM_DESC(irq_coalescing_usecs,
94 "IRQ coalescing time threshold in usecs");
97 /* BAR's are enumerated in terms of pci_resource_start() terms */
98 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
99 MV_IO_BAR = 2, /* offset 0x18: IO space */
100 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
102 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
103 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
105 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
106 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
107 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
108 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
113 * Per-chip ("all ports") interrupt coalescing feature.
114 * This is only for GEN_II / GEN_IIE hardware.
116 * Coalescing defers the interrupt until either the IO_THRESHOLD
117 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
119 COAL_REG_BASE = 0x18000,
120 IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
121 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
123 IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
124 IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
127 * Registers for the (unused here) transaction coalescing feature:
129 TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
130 TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
132 SATAHC0_REG_BASE = 0x20000,
134 GPIO_PORT_CTL = 0x104f0,
137 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
138 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
139 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
140 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
143 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
145 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
146 * CRPB needs alignment on a 256B boundary. Size == 256B
147 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
149 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
150 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
152 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
154 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
155 MV_PORT_HC_SHIFT = 2,
156 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
157 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
158 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
161 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
163 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING,
165 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
167 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
168 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
170 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
172 CRQB_FLAG_READ = (1 << 0),
174 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
175 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
176 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
177 CRQB_CMD_ADDR_SHIFT = 8,
178 CRQB_CMD_CS = (0x2 << 11),
179 CRQB_CMD_LAST = (1 << 15),
181 CRPB_FLAG_STATUS_SHIFT = 8,
182 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
183 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
185 EPRD_FLAG_END_OF_TBL = (1 << 31),
187 /* PCI interface registers */
189 MV_PCI_COMMAND = 0xc00,
190 MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
191 MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
193 PCI_MAIN_CMD_STS = 0xd30,
194 STOP_PCI_MASTER = (1 << 2),
195 PCI_MASTER_EMPTY = (1 << 3),
196 GLOB_SFT_RST = (1 << 4),
199 MV_PCI_MODE_MASK = 0x30,
201 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
202 MV_PCI_DISC_TIMER = 0xd04,
203 MV_PCI_MSI_TRIGGER = 0xc38,
204 MV_PCI_SERR_MASK = 0xc28,
205 MV_PCI_XBAR_TMOUT = 0x1d04,
206 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
207 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
208 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
209 MV_PCI_ERR_COMMAND = 0x1d50,
211 PCI_IRQ_CAUSE = 0x1d58,
212 PCI_IRQ_MASK = 0x1d5c,
213 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
215 PCIE_IRQ_CAUSE = 0x1900,
216 PCIE_IRQ_MASK = 0x1910,
217 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
219 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
220 PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
221 PCI_HC_MAIN_IRQ_MASK = 0x1d64,
222 SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
223 SOC_HC_MAIN_IRQ_MASK = 0x20024,
224 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
225 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
226 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
227 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
228 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
229 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
231 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
232 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
233 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
234 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
235 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
236 GPIO_INT = (1 << 22),
237 SELF_INT = (1 << 23),
238 TWSI_INT = (1 << 24),
239 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
240 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
241 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
243 /* SATAHC registers */
247 DMA_IRQ = (1 << 0), /* shift by port # */
248 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
249 DEV_IRQ = (1 << 8), /* shift by port # */
252 * Per-HC (Host-Controller) interrupt coalescing feature.
253 * This is present on all chip generations.
255 * Coalescing defers the interrupt until either the IO_THRESHOLD
256 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
258 HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
259 HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
262 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
263 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
264 /* with dev activity LED */
266 /* Shadow block registers */
268 SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
271 SATA_STATUS = 0x300, /* ctrl, err regs follow status */
273 FIS_IRQ_CAUSE = 0x364,
274 FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
276 LTMODE = 0x30c, /* requires read-after-write */
277 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
282 PHY_MODE4 = 0x314, /* requires read-after-write */
283 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
284 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
285 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
286 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
289 SATA_TESTCTL = 0x348,
291 VENDOR_UNIQUE_FIS = 0x35c,
294 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
295 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
297 PHY_MODE9_GEN2 = 0x398,
298 PHY_MODE9_GEN1 = 0x39c,
299 PHYCFG_OFS = 0x3a0, /* only in 65n devices */
306 MV_M2_PREAMP_MASK = 0x7e0,
310 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
311 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
312 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
313 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
314 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
315 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
316 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
318 EDMA_ERR_IRQ_CAUSE = 0x8,
319 EDMA_ERR_IRQ_MASK = 0xc,
320 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
321 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
322 EDMA_ERR_DEV = (1 << 2), /* device error */
323 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
324 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
325 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
326 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
327 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
328 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
329 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
330 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
331 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
332 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
333 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
335 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
336 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
337 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
338 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
339 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
341 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
343 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
344 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
345 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
346 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
347 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
348 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
350 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
352 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
353 EDMA_ERR_OVERRUN_5 = (1 << 5),
354 EDMA_ERR_UNDERRUN_5 = (1 << 6),
356 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
357 EDMA_ERR_LNK_CTRL_RX_1 |
358 EDMA_ERR_LNK_CTRL_RX_3 |
359 EDMA_ERR_LNK_CTRL_TX,
361 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
371 EDMA_ERR_LNK_CTRL_RX_2 |
372 EDMA_ERR_LNK_DATA_RX |
373 EDMA_ERR_LNK_DATA_TX |
374 EDMA_ERR_TRANS_PROTO,
376 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
381 EDMA_ERR_UNDERRUN_5 |
382 EDMA_ERR_SELF_DIS_5 |
388 EDMA_REQ_Q_BASE_HI = 0x10,
389 EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
391 EDMA_REQ_Q_OUT_PTR = 0x18,
392 EDMA_REQ_Q_PTR_SHIFT = 5,
394 EDMA_RSP_Q_BASE_HI = 0x1c,
395 EDMA_RSP_Q_IN_PTR = 0x20,
396 EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
397 EDMA_RSP_Q_PTR_SHIFT = 3,
399 EDMA_CMD = 0x28, /* EDMA command register */
400 EDMA_EN = (1 << 0), /* enable EDMA */
401 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
402 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
404 EDMA_STATUS = 0x30, /* EDMA engine status */
405 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
406 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
408 EDMA_IORDY_TMOUT = 0x34,
411 EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
412 EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
414 BMDMA_CMD = 0x224, /* bmdma command register */
415 BMDMA_STATUS = 0x228, /* bmdma status register */
416 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
417 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
419 /* Host private flags (hp_flags) */
420 MV_HP_FLAG_MSI = (1 << 0),
421 MV_HP_ERRATA_50XXB0 = (1 << 1),
422 MV_HP_ERRATA_50XXB2 = (1 << 2),
423 MV_HP_ERRATA_60X1B2 = (1 << 3),
424 MV_HP_ERRATA_60X1C0 = (1 << 4),
425 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
426 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
427 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
428 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
429 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
430 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
431 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
433 /* Port private flags (pp_flags) */
434 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
435 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
436 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
437 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
438 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
441 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
442 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
443 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
444 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
445 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
447 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
448 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
451 /* DMA boundary 0xffff is required by the s/g splitting
452 * we need on /length/ in mv_fill-sg().
454 MV_DMA_BOUNDARY = 0xffffU,
456 /* mask of register bits containing lower 32 bits
457 * of EDMA request queue DMA address
459 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
461 /* ditto, for response queue */
462 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
476 /* Command ReQuest Block: 32B */
492 /* Command ResPonse Block: 8B */
499 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
508 * We keep a local cache of a few frequently accessed port
509 * registers here, to avoid having to read them (very slow)
510 * when switching between EDMA and non-EDMA modes.
512 struct mv_cached_regs {
519 struct mv_port_priv {
520 struct mv_crqb *crqb;
522 struct mv_crpb *crpb;
524 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
525 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
527 unsigned int req_idx;
528 unsigned int resp_idx;
531 struct mv_cached_regs cached;
532 unsigned int delayed_eh_pmp_map;
535 struct mv_port_signal {
540 struct mv_host_priv {
542 unsigned int board_idx;
544 struct mv_port_signal signal[8];
545 const struct mv_hw_ops *ops;
548 void __iomem *main_irq_cause_addr;
549 void __iomem *main_irq_mask_addr;
550 u32 irq_cause_offset;
554 #if defined(CONFIG_HAVE_CLK)
556 struct clk **port_clks;
559 * These consistent DMA memory pools give us guaranteed
560 * alignment for hardware-accessed data structures,
561 * and less memory waste in accomplishing the alignment.
563 struct dma_pool *crqb_pool;
564 struct dma_pool *crpb_pool;
565 struct dma_pool *sg_tbl_pool;
569 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
571 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
572 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
574 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
576 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
577 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
580 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
581 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
582 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
583 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
584 static int mv_port_start(struct ata_port *ap);
585 static void mv_port_stop(struct ata_port *ap);
586 static int mv_qc_defer(struct ata_queued_cmd *qc);
587 static void mv_qc_prep(struct ata_queued_cmd *qc);
588 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
589 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
590 static int mv_hardreset(struct ata_link *link, unsigned int *class,
591 unsigned long deadline);
592 static void mv_eh_freeze(struct ata_port *ap);
593 static void mv_eh_thaw(struct ata_port *ap);
594 static void mv6_dev_config(struct ata_device *dev);
596 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
598 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
599 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
601 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
603 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
604 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
606 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
608 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
609 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
611 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
613 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
614 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
616 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
618 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
619 void __iomem *mmio, unsigned int n_hc);
620 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
622 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
623 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
624 void __iomem *mmio, unsigned int port);
625 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
626 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
627 unsigned int port_no);
628 static int mv_stop_edma(struct ata_port *ap);
629 static int mv_stop_edma_engine(void __iomem *port_mmio);
630 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
632 static void mv_pmp_select(struct ata_port *ap, int pmp);
633 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
634 unsigned long deadline);
635 static int mv_softreset(struct ata_link *link, unsigned int *class,
636 unsigned long deadline);
637 static void mv_pmp_error_handler(struct ata_port *ap);
638 static void mv_process_crpb_entries(struct ata_port *ap,
639 struct mv_port_priv *pp);
641 static void mv_sff_irq_clear(struct ata_port *ap);
642 static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
643 static void mv_bmdma_setup(struct ata_queued_cmd *qc);
644 static void mv_bmdma_start(struct ata_queued_cmd *qc);
645 static void mv_bmdma_stop(struct ata_queued_cmd *qc);
646 static u8 mv_bmdma_status(struct ata_port *ap);
647 static u8 mv_sff_check_status(struct ata_port *ap);
649 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
650 * because we have to allow room for worst case splitting of
651 * PRDs for 64K boundaries in mv_fill_sg().
653 static struct scsi_host_template mv5_sht = {
654 ATA_BASE_SHT(DRV_NAME),
655 .sg_tablesize = MV_MAX_SG_CT / 2,
656 .dma_boundary = MV_DMA_BOUNDARY,
659 static struct scsi_host_template mv6_sht = {
660 ATA_NCQ_SHT(DRV_NAME),
661 .can_queue = MV_MAX_Q_DEPTH - 1,
662 .sg_tablesize = MV_MAX_SG_CT / 2,
663 .dma_boundary = MV_DMA_BOUNDARY,
666 static struct ata_port_operations mv5_ops = {
667 .inherits = &ata_sff_port_ops,
669 .lost_interrupt = ATA_OP_NULL,
671 .qc_defer = mv_qc_defer,
672 .qc_prep = mv_qc_prep,
673 .qc_issue = mv_qc_issue,
675 .freeze = mv_eh_freeze,
677 .hardreset = mv_hardreset,
679 .scr_read = mv5_scr_read,
680 .scr_write = mv5_scr_write,
682 .port_start = mv_port_start,
683 .port_stop = mv_port_stop,
686 static struct ata_port_operations mv6_ops = {
687 .inherits = &ata_bmdma_port_ops,
689 .lost_interrupt = ATA_OP_NULL,
691 .qc_defer = mv_qc_defer,
692 .qc_prep = mv_qc_prep,
693 .qc_issue = mv_qc_issue,
695 .dev_config = mv6_dev_config,
697 .freeze = mv_eh_freeze,
699 .hardreset = mv_hardreset,
700 .softreset = mv_softreset,
701 .pmp_hardreset = mv_pmp_hardreset,
702 .pmp_softreset = mv_softreset,
703 .error_handler = mv_pmp_error_handler,
705 .scr_read = mv_scr_read,
706 .scr_write = mv_scr_write,
708 .sff_check_status = mv_sff_check_status,
709 .sff_irq_clear = mv_sff_irq_clear,
710 .check_atapi_dma = mv_check_atapi_dma,
711 .bmdma_setup = mv_bmdma_setup,
712 .bmdma_start = mv_bmdma_start,
713 .bmdma_stop = mv_bmdma_stop,
714 .bmdma_status = mv_bmdma_status,
716 .port_start = mv_port_start,
717 .port_stop = mv_port_stop,
720 static struct ata_port_operations mv_iie_ops = {
721 .inherits = &mv6_ops,
722 .dev_config = ATA_OP_NULL,
723 .qc_prep = mv_qc_prep_iie,
726 static const struct ata_port_info mv_port_info[] = {
728 .flags = MV_GEN_I_FLAGS,
729 .pio_mask = ATA_PIO4,
730 .udma_mask = ATA_UDMA6,
731 .port_ops = &mv5_ops,
734 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
735 .pio_mask = ATA_PIO4,
736 .udma_mask = ATA_UDMA6,
737 .port_ops = &mv5_ops,
740 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
741 .pio_mask = ATA_PIO4,
742 .udma_mask = ATA_UDMA6,
743 .port_ops = &mv5_ops,
746 .flags = MV_GEN_II_FLAGS,
747 .pio_mask = ATA_PIO4,
748 .udma_mask = ATA_UDMA6,
749 .port_ops = &mv6_ops,
752 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
753 .pio_mask = ATA_PIO4,
754 .udma_mask = ATA_UDMA6,
755 .port_ops = &mv6_ops,
758 .flags = MV_GEN_IIE_FLAGS,
759 .pio_mask = ATA_PIO4,
760 .udma_mask = ATA_UDMA6,
761 .port_ops = &mv_iie_ops,
764 .flags = MV_GEN_IIE_FLAGS,
765 .pio_mask = ATA_PIO4,
766 .udma_mask = ATA_UDMA6,
767 .port_ops = &mv_iie_ops,
770 .flags = MV_GEN_IIE_FLAGS,
771 .pio_mask = ATA_PIO4,
772 .udma_mask = ATA_UDMA6,
773 .port_ops = &mv_iie_ops,
777 static const struct pci_device_id mv_pci_tbl[] = {
778 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
779 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
780 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
781 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
782 /* RocketRAID 1720/174x have different identifiers */
783 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
784 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
785 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
787 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
788 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
789 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
790 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
791 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
793 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
796 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
798 /* Marvell 7042 support */
799 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
801 /* Highpoint RocketRAID PCIe series */
802 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
803 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
805 { } /* terminate list */
808 static const struct mv_hw_ops mv5xxx_ops = {
809 .phy_errata = mv5_phy_errata,
810 .enable_leds = mv5_enable_leds,
811 .read_preamp = mv5_read_preamp,
812 .reset_hc = mv5_reset_hc,
813 .reset_flash = mv5_reset_flash,
814 .reset_bus = mv5_reset_bus,
817 static const struct mv_hw_ops mv6xxx_ops = {
818 .phy_errata = mv6_phy_errata,
819 .enable_leds = mv6_enable_leds,
820 .read_preamp = mv6_read_preamp,
821 .reset_hc = mv6_reset_hc,
822 .reset_flash = mv6_reset_flash,
823 .reset_bus = mv_reset_pci_bus,
826 static const struct mv_hw_ops mv_soc_ops = {
827 .phy_errata = mv6_phy_errata,
828 .enable_leds = mv_soc_enable_leds,
829 .read_preamp = mv_soc_read_preamp,
830 .reset_hc = mv_soc_reset_hc,
831 .reset_flash = mv_soc_reset_flash,
832 .reset_bus = mv_soc_reset_bus,
835 static const struct mv_hw_ops mv_soc_65n_ops = {
836 .phy_errata = mv_soc_65n_phy_errata,
837 .enable_leds = mv_soc_enable_leds,
838 .reset_hc = mv_soc_reset_hc,
839 .reset_flash = mv_soc_reset_flash,
840 .reset_bus = mv_soc_reset_bus,
847 static inline void writelfl(unsigned long data, void __iomem *addr)
850 (void) readl(addr); /* flush to avoid PCI posted write */
853 static inline unsigned int mv_hc_from_port(unsigned int port)
855 return port >> MV_PORT_HC_SHIFT;
858 static inline unsigned int mv_hardport_from_port(unsigned int port)
860 return port & MV_PORT_MASK;
864 * Consolidate some rather tricky bit shift calculations.
865 * This is hot-path stuff, so not a function.
866 * Simple code, with two return values, so macro rather than inline.
868 * port is the sole input, in range 0..7.
869 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
870 * hardport is the other output, in range 0..3.
872 * Note that port and hardport may be the same variable in some cases.
874 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
876 shift = mv_hc_from_port(port) * HC_SHIFT; \
877 hardport = mv_hardport_from_port(port); \
878 shift += hardport * 2; \
881 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
883 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
886 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
889 return mv_hc_base(base, mv_hc_from_port(port));
892 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
894 return mv_hc_base_from_port(base, port) +
895 MV_SATAHC_ARBTR_REG_SZ +
896 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
899 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
901 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
902 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
904 return hc_mmio + ofs;
907 static inline void __iomem *mv_host_base(struct ata_host *host)
909 struct mv_host_priv *hpriv = host->private_data;
913 static inline void __iomem *mv_ap_base(struct ata_port *ap)
915 return mv_port_base(mv_host_base(ap->host), ap->port_no);
918 static inline int mv_get_hc_count(unsigned long port_flags)
920 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
924 * mv_save_cached_regs - (re-)initialize cached port registers
925 * @ap: the port whose registers we are caching
927 * Initialize the local cache of port registers,
928 * so that reading them over and over again can
929 * be avoided on the hotter paths of this driver.
930 * This saves a few microseconds each time we switch
931 * to/from EDMA mode to perform (eg.) a drive cache flush.
933 static void mv_save_cached_regs(struct ata_port *ap)
935 void __iomem *port_mmio = mv_ap_base(ap);
936 struct mv_port_priv *pp = ap->private_data;
938 pp->cached.fiscfg = readl(port_mmio + FISCFG);
939 pp->cached.ltmode = readl(port_mmio + LTMODE);
940 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
941 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
945 * mv_write_cached_reg - write to a cached port register
946 * @addr: hardware address of the register
947 * @old: pointer to cached value of the register
948 * @new: new value for the register
950 * Write a new value to a cached register,
951 * but only if the value is different from before.
953 static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
959 * Workaround for 88SX60x1-B2 FEr SATA#13:
960 * Read-after-write is needed to prevent generating 64-bit
961 * write cycles on the PCI bus for SATA interface registers
962 * at offsets ending in 0x4 or 0xc.
964 * Looks like a lot of fuss, but it avoids an unnecessary
965 * +1 usec read-after-write delay for unaffected registers.
967 laddr = (long)addr & 0xffff;
968 if (laddr >= 0x300 && laddr <= 0x33c) {
970 if (laddr == 0x4 || laddr == 0xc) {
971 writelfl(new, addr); /* read after write */
975 writel(new, addr); /* unaffected by the errata */
979 static void mv_set_edma_ptrs(void __iomem *port_mmio,
980 struct mv_host_priv *hpriv,
981 struct mv_port_priv *pp)
986 * initialize request queue
988 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
989 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
991 WARN_ON(pp->crqb_dma & 0x3ff);
992 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
993 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
994 port_mmio + EDMA_REQ_Q_IN_PTR);
995 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
998 * initialize response queue
1000 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
1001 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
1003 WARN_ON(pp->crpb_dma & 0xff);
1004 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
1005 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
1006 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
1007 port_mmio + EDMA_RSP_Q_OUT_PTR);
1010 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
1013 * When writing to the main_irq_mask in hardware,
1014 * we must ensure exclusivity between the interrupt coalescing bits
1015 * and the corresponding individual port DONE_IRQ bits.
1017 * Note that this register is really an "IRQ enable" register,
1018 * not an "IRQ mask" register as Marvell's naming might suggest.
1020 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
1021 mask &= ~DONE_IRQ_0_3;
1022 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
1023 mask &= ~DONE_IRQ_4_7;
1024 writelfl(mask, hpriv->main_irq_mask_addr);
1027 static void mv_set_main_irq_mask(struct ata_host *host,
1028 u32 disable_bits, u32 enable_bits)
1030 struct mv_host_priv *hpriv = host->private_data;
1031 u32 old_mask, new_mask;
1033 old_mask = hpriv->main_irq_mask;
1034 new_mask = (old_mask & ~disable_bits) | enable_bits;
1035 if (new_mask != old_mask) {
1036 hpriv->main_irq_mask = new_mask;
1037 mv_write_main_irq_mask(new_mask, hpriv);
1041 static void mv_enable_port_irqs(struct ata_port *ap,
1042 unsigned int port_bits)
1044 unsigned int shift, hardport, port = ap->port_no;
1045 u32 disable_bits, enable_bits;
1047 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1049 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
1050 enable_bits = port_bits << shift;
1051 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
1054 static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
1055 void __iomem *port_mmio,
1056 unsigned int port_irqs)
1058 struct mv_host_priv *hpriv = ap->host->private_data;
1059 int hardport = mv_hardport_from_port(ap->port_no);
1060 void __iomem *hc_mmio = mv_hc_base_from_port(
1061 mv_host_base(ap->host), ap->port_no);
1064 /* clear EDMA event indicators, if any */
1065 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
1067 /* clear pending irq events */
1068 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1069 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
1071 /* clear FIS IRQ Cause */
1072 if (IS_GEN_IIE(hpriv))
1073 writelfl(0, port_mmio + FIS_IRQ_CAUSE);
1075 mv_enable_port_irqs(ap, port_irqs);
1078 static void mv_set_irq_coalescing(struct ata_host *host,
1079 unsigned int count, unsigned int usecs)
1081 struct mv_host_priv *hpriv = host->private_data;
1082 void __iomem *mmio = hpriv->base, *hc_mmio;
1083 u32 coal_enable = 0;
1084 unsigned long flags;
1085 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
1086 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1087 ALL_PORTS_COAL_DONE;
1089 /* Disable IRQ coalescing if either threshold is zero */
1090 if (!usecs || !count) {
1093 /* Respect maximum limits of the hardware */
1094 clks = usecs * COAL_CLOCKS_PER_USEC;
1095 if (clks > MAX_COAL_TIME_THRESHOLD)
1096 clks = MAX_COAL_TIME_THRESHOLD;
1097 if (count > MAX_COAL_IO_COUNT)
1098 count = MAX_COAL_IO_COUNT;
1101 spin_lock_irqsave(&host->lock, flags);
1102 mv_set_main_irq_mask(host, coal_disable, 0);
1104 if (is_dual_hc && !IS_GEN_I(hpriv)) {
1106 * GEN_II/GEN_IIE with dual host controllers:
1107 * one set of global thresholds for the entire chip.
1109 writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
1110 writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
1111 /* clear leftover coal IRQ bit */
1112 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
1114 coal_enable = ALL_PORTS_COAL_DONE;
1115 clks = count = 0; /* force clearing of regular regs below */
1119 * All chips: independent thresholds for each HC on the chip.
1121 hc_mmio = mv_hc_base_from_port(mmio, 0);
1122 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1123 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1124 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1126 coal_enable |= PORTS_0_3_COAL_DONE;
1128 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
1129 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1130 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1131 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1133 coal_enable |= PORTS_4_7_COAL_DONE;
1136 mv_set_main_irq_mask(host, 0, coal_enable);
1137 spin_unlock_irqrestore(&host->lock, flags);
1141 * mv_start_edma - Enable eDMA engine
1142 * @base: port base address
1143 * @pp: port private data
1145 * Verify the local cache of the eDMA state is accurate with a
1149 * Inherited from caller.
1151 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
1152 struct mv_port_priv *pp, u8 protocol)
1154 int want_ncq = (protocol == ATA_PROT_NCQ);
1156 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1157 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1158 if (want_ncq != using_ncq)
1161 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1162 struct mv_host_priv *hpriv = ap->host->private_data;
1164 mv_edma_cfg(ap, want_ncq, 1);
1166 mv_set_edma_ptrs(port_mmio, hpriv, pp);
1167 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
1169 writelfl(EDMA_EN, port_mmio + EDMA_CMD);
1170 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1174 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1176 void __iomem *port_mmio = mv_ap_base(ap);
1177 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1178 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1182 * Wait for the EDMA engine to finish transactions in progress.
1183 * No idea what a good "timeout" value might be, but measurements
1184 * indicate that it often requires hundreds of microseconds
1185 * with two drives in-use. So we use the 15msec value above
1186 * as a rough guess at what even more drives might require.
1188 for (i = 0; i < timeout; ++i) {
1189 u32 edma_stat = readl(port_mmio + EDMA_STATUS);
1190 if ((edma_stat & empty_idle) == empty_idle)
1194 /* ata_port_info(ap, "%s: %u+ usecs\n", __func__, i); */
1198 * mv_stop_edma_engine - Disable eDMA engine
1199 * @port_mmio: io base address
1202 * Inherited from caller.
1204 static int mv_stop_edma_engine(void __iomem *port_mmio)
1208 /* Disable eDMA. The disable bit auto clears. */
1209 writelfl(EDMA_DS, port_mmio + EDMA_CMD);
1211 /* Wait for the chip to confirm eDMA is off. */
1212 for (i = 10000; i > 0; i--) {
1213 u32 reg = readl(port_mmio + EDMA_CMD);
1214 if (!(reg & EDMA_EN))
1221 static int mv_stop_edma(struct ata_port *ap)
1223 void __iomem *port_mmio = mv_ap_base(ap);
1224 struct mv_port_priv *pp = ap->private_data;
1227 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1229 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1230 mv_wait_for_edma_empty_idle(ap);
1231 if (mv_stop_edma_engine(port_mmio)) {
1232 ata_port_err(ap, "Unable to stop eDMA\n");
1235 mv_edma_cfg(ap, 0, 0);
1240 static void mv_dump_mem(void __iomem *start, unsigned bytes)
1243 for (b = 0; b < bytes; ) {
1244 DPRINTK("%p: ", start + b);
1245 for (w = 0; b < bytes && w < 4; w++) {
1246 printk("%08x ", readl(start + b));
1254 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1259 for (b = 0; b < bytes; ) {
1260 DPRINTK("%02x: ", b);
1261 for (w = 0; b < bytes && w < 4; w++) {
1262 (void) pci_read_config_dword(pdev, b, &dw);
1263 printk("%08x ", dw);
1270 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1271 struct pci_dev *pdev)
1274 void __iomem *hc_base = mv_hc_base(mmio_base,
1275 port >> MV_PORT_HC_SHIFT);
1276 void __iomem *port_base;
1277 int start_port, num_ports, p, start_hc, num_hcs, hc;
1280 start_hc = start_port = 0;
1281 num_ports = 8; /* shld be benign for 4 port devs */
1284 start_hc = port >> MV_PORT_HC_SHIFT;
1286 num_ports = num_hcs = 1;
1288 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1289 num_ports > 1 ? num_ports - 1 : start_port);
1292 DPRINTK("PCI config space regs:\n");
1293 mv_dump_pci_cfg(pdev, 0x68);
1295 DPRINTK("PCI regs:\n");
1296 mv_dump_mem(mmio_base+0xc00, 0x3c);
1297 mv_dump_mem(mmio_base+0xd00, 0x34);
1298 mv_dump_mem(mmio_base+0xf00, 0x4);
1299 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1300 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1301 hc_base = mv_hc_base(mmio_base, hc);
1302 DPRINTK("HC regs (HC %i):\n", hc);
1303 mv_dump_mem(hc_base, 0x1c);
1305 for (p = start_port; p < start_port + num_ports; p++) {
1306 port_base = mv_port_base(mmio_base, p);
1307 DPRINTK("EDMA regs (port %i):\n", p);
1308 mv_dump_mem(port_base, 0x54);
1309 DPRINTK("SATA regs (port %i):\n", p);
1310 mv_dump_mem(port_base+0x300, 0x60);
1315 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1319 switch (sc_reg_in) {
1323 ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
1326 ofs = SATA_ACTIVE; /* active is not with the others */
1335 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
1337 unsigned int ofs = mv_scr_offset(sc_reg_in);
1339 if (ofs != 0xffffffffU) {
1340 *val = readl(mv_ap_base(link->ap) + ofs);
1346 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
1348 unsigned int ofs = mv_scr_offset(sc_reg_in);
1350 if (ofs != 0xffffffffU) {
1351 void __iomem *addr = mv_ap_base(link->ap) + ofs;
1352 if (sc_reg_in == SCR_CONTROL) {
1354 * Workaround for 88SX60x1 FEr SATA#26:
1356 * COMRESETs have to take care not to accidentally
1357 * put the drive to sleep when writing SCR_CONTROL.
1358 * Setting bits 12..15 prevents this problem.
1360 * So if we see an outbound COMMRESET, set those bits.
1361 * Ditto for the followup write that clears the reset.
1363 * The proprietary driver does this for
1364 * all chip versions, and so do we.
1366 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
1369 writelfl(val, addr);
1375 static void mv6_dev_config(struct ata_device *adev)
1378 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1380 * Gen-II does not support NCQ over a port multiplier
1381 * (no FIS-based switching).
1383 if (adev->flags & ATA_DFLAG_NCQ) {
1384 if (sata_pmp_attached(adev->link->ap)) {
1385 adev->flags &= ~ATA_DFLAG_NCQ;
1387 "NCQ disabled for command-based switching\n");
1392 static int mv_qc_defer(struct ata_queued_cmd *qc)
1394 struct ata_link *link = qc->dev->link;
1395 struct ata_port *ap = link->ap;
1396 struct mv_port_priv *pp = ap->private_data;
1399 * Don't allow new commands if we're in a delayed EH state
1400 * for NCQ and/or FIS-based switching.
1402 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1403 return ATA_DEFER_PORT;
1405 /* PIO commands need exclusive link: no other commands [DMA or PIO]
1406 * can run concurrently.
1407 * set excl_link when we want to send a PIO command in DMA mode
1408 * or a non-NCQ command in NCQ mode.
1409 * When we receive a command from that link, and there are no
1410 * outstanding commands, mark a flag to clear excl_link and let
1411 * the command go through.
1413 if (unlikely(ap->excl_link)) {
1414 if (link == ap->excl_link) {
1415 if (ap->nr_active_links)
1416 return ATA_DEFER_PORT;
1417 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
1420 return ATA_DEFER_PORT;
1424 * If the port is completely idle, then allow the new qc.
1426 if (ap->nr_active_links == 0)
1430 * The port is operating in host queuing mode (EDMA) with NCQ
1431 * enabled, allow multiple NCQ commands. EDMA also allows
1432 * queueing multiple DMA commands but libata core currently
1435 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1436 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
1437 if (ata_is_ncq(qc->tf.protocol))
1440 ap->excl_link = link;
1441 return ATA_DEFER_PORT;
1445 return ATA_DEFER_PORT;
1448 static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
1450 struct mv_port_priv *pp = ap->private_data;
1451 void __iomem *port_mmio;
1453 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1454 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1455 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
1457 ltmode = *old_ltmode & ~LTMODE_BIT8;
1458 haltcond = *old_haltcond | EDMA_ERR_DEV;
1461 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1462 ltmode = *old_ltmode | LTMODE_BIT8;
1464 haltcond &= ~EDMA_ERR_DEV;
1466 fiscfg |= FISCFG_WAIT_DEV_ERR;
1468 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1471 port_mmio = mv_ap_base(ap);
1472 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
1473 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
1474 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
1477 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1479 struct mv_host_priv *hpriv = ap->host->private_data;
1482 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1483 old = readl(hpriv->base + GPIO_PORT_CTL);
1485 new = old | (1 << 22);
1487 new = old & ~(1 << 22);
1489 writel(new, hpriv->base + GPIO_PORT_CTL);
1493 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1494 * @ap: Port being initialized
1496 * There are two DMA modes on these chips: basic DMA, and EDMA.
1498 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1499 * of basic DMA on the GEN_IIE versions of the chips.
1501 * This bit survives EDMA resets, and must be set for basic DMA
1502 * to function, and should be cleared when EDMA is active.
1504 static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1506 struct mv_port_priv *pp = ap->private_data;
1507 u32 new, *old = &pp->cached.unknown_rsvd;
1513 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
1517 * SOC chips have an issue whereby the HDD LEDs don't always blink
1518 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1519 * of the SOC takes care of it, generating a steady blink rate when
1520 * any drive on the chip is active.
1522 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1523 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1525 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1526 * LED operation works then, and provides better (more accurate) feedback.
1528 * Note that this code assumes that an SOC never has more than one HC onboard.
1530 static void mv_soc_led_blink_enable(struct ata_port *ap)
1532 struct ata_host *host = ap->host;
1533 struct mv_host_priv *hpriv = host->private_data;
1534 void __iomem *hc_mmio;
1537 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1539 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1540 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1541 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1542 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1545 static void mv_soc_led_blink_disable(struct ata_port *ap)
1547 struct ata_host *host = ap->host;
1548 struct mv_host_priv *hpriv = host->private_data;
1549 void __iomem *hc_mmio;
1553 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1556 /* disable led-blink only if no ports are using NCQ */
1557 for (port = 0; port < hpriv->n_ports; port++) {
1558 struct ata_port *this_ap = host->ports[port];
1559 struct mv_port_priv *pp = this_ap->private_data;
1561 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1565 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1566 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1567 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1568 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1571 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
1574 struct mv_port_priv *pp = ap->private_data;
1575 struct mv_host_priv *hpriv = ap->host->private_data;
1576 void __iomem *port_mmio = mv_ap_base(ap);
1578 /* set up non-NCQ EDMA configuration */
1579 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1581 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
1583 if (IS_GEN_I(hpriv))
1584 cfg |= (1 << 8); /* enab config burst size mask */
1586 else if (IS_GEN_II(hpriv)) {
1587 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1588 mv_60x1_errata_sata25(ap, want_ncq);
1590 } else if (IS_GEN_IIE(hpriv)) {
1591 int want_fbs = sata_pmp_attached(ap);
1593 * Possible future enhancement:
1595 * The chip can use FBS with non-NCQ, if we allow it,
1596 * But first we need to have the error handling in place
1597 * for this mode (datasheet section 7.3.15.4.2.3).
1598 * So disallow non-NCQ FBS for now.
1600 want_fbs &= want_ncq;
1602 mv_config_fbs(ap, want_ncq, want_fbs);
1605 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1606 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1609 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1611 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1613 cfg |= (1 << 18); /* enab early completion */
1615 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1616 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1617 mv_bmdma_enable_iie(ap, !want_edma);
1619 if (IS_SOC(hpriv)) {
1621 mv_soc_led_blink_enable(ap);
1623 mv_soc_led_blink_disable(ap);
1628 cfg |= EDMA_CFG_NCQ;
1629 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1632 writelfl(cfg, port_mmio + EDMA_CFG);
1635 static void mv_port_free_dma_mem(struct ata_port *ap)
1637 struct mv_host_priv *hpriv = ap->host->private_data;
1638 struct mv_port_priv *pp = ap->private_data;
1642 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1646 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1650 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1651 * For later hardware, we have one unique sg_tbl per NCQ tag.
1653 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1654 if (pp->sg_tbl[tag]) {
1655 if (tag == 0 || !IS_GEN_I(hpriv))
1656 dma_pool_free(hpriv->sg_tbl_pool,
1658 pp->sg_tbl_dma[tag]);
1659 pp->sg_tbl[tag] = NULL;
1665 * mv_port_start - Port specific init/start routine.
1666 * @ap: ATA channel to manipulate
1668 * Allocate and point to DMA memory, init port private memory,
1672 * Inherited from caller.
1674 static int mv_port_start(struct ata_port *ap)
1676 struct device *dev = ap->host->dev;
1677 struct mv_host_priv *hpriv = ap->host->private_data;
1678 struct mv_port_priv *pp;
1679 unsigned long flags;
1682 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1685 ap->private_data = pp;
1687 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1690 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1692 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1694 goto out_port_free_dma_mem;
1695 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1697 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1698 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1699 ap->flags |= ATA_FLAG_AN;
1701 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1702 * For later hardware, we need one unique sg_tbl per NCQ tag.
1704 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1705 if (tag == 0 || !IS_GEN_I(hpriv)) {
1706 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1707 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1708 if (!pp->sg_tbl[tag])
1709 goto out_port_free_dma_mem;
1711 pp->sg_tbl[tag] = pp->sg_tbl[0];
1712 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1716 spin_lock_irqsave(ap->lock, flags);
1717 mv_save_cached_regs(ap);
1718 mv_edma_cfg(ap, 0, 0);
1719 spin_unlock_irqrestore(ap->lock, flags);
1723 out_port_free_dma_mem:
1724 mv_port_free_dma_mem(ap);
1729 * mv_port_stop - Port specific cleanup/stop routine.
1730 * @ap: ATA channel to manipulate
1732 * Stop DMA, cleanup port memory.
1735 * This routine uses the host lock to protect the DMA stop.
1737 static void mv_port_stop(struct ata_port *ap)
1739 unsigned long flags;
1741 spin_lock_irqsave(ap->lock, flags);
1743 mv_enable_port_irqs(ap, 0);
1744 spin_unlock_irqrestore(ap->lock, flags);
1745 mv_port_free_dma_mem(ap);
1749 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1750 * @qc: queued command whose SG list to source from
1752 * Populate the SG list and mark the last entry.
1755 * Inherited from caller.
1757 static void mv_fill_sg(struct ata_queued_cmd *qc)
1759 struct mv_port_priv *pp = qc->ap->private_data;
1760 struct scatterlist *sg;
1761 struct mv_sg *mv_sg, *last_sg = NULL;
1764 mv_sg = pp->sg_tbl[qc->tag];
1765 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1766 dma_addr_t addr = sg_dma_address(sg);
1767 u32 sg_len = sg_dma_len(sg);
1770 u32 offset = addr & 0xffff;
1773 if (offset + len > 0x10000)
1774 len = 0x10000 - offset;
1776 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1777 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1778 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1779 mv_sg->reserved = 0;
1789 if (likely(last_sg))
1790 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1791 mb(); /* ensure data structure is visible to the chipset */
1794 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1796 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1797 (last ? CRQB_CMD_LAST : 0);
1798 *cmdw = cpu_to_le16(tmp);
1802 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1803 * @ap: Port associated with this ATA transaction.
1805 * We need this only for ATAPI bmdma transactions,
1806 * as otherwise we experience spurious interrupts
1807 * after libata-sff handles the bmdma interrupts.
1809 static void mv_sff_irq_clear(struct ata_port *ap)
1811 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1815 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1816 * @qc: queued command to check for chipset/DMA compatibility.
1818 * The bmdma engines cannot handle speculative data sizes
1819 * (bytecount under/over flow). So only allow DMA for
1820 * data transfer commands with known data sizes.
1823 * Inherited from caller.
1825 static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1827 struct scsi_cmnd *scmd = qc->scsicmd;
1830 switch (scmd->cmnd[0]) {
1838 case GPCMD_SEND_DVD_STRUCTURE:
1839 case GPCMD_SEND_CUE_SHEET:
1840 return 0; /* DMA is safe */
1843 return -EOPNOTSUPP; /* use PIO instead */
1847 * mv_bmdma_setup - Set up BMDMA transaction
1848 * @qc: queued command to prepare DMA for.
1851 * Inherited from caller.
1853 static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1855 struct ata_port *ap = qc->ap;
1856 void __iomem *port_mmio = mv_ap_base(ap);
1857 struct mv_port_priv *pp = ap->private_data;
1861 /* clear all DMA cmd bits */
1862 writel(0, port_mmio + BMDMA_CMD);
1864 /* load PRD table addr. */
1865 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1866 port_mmio + BMDMA_PRD_HIGH);
1867 writelfl(pp->sg_tbl_dma[qc->tag],
1868 port_mmio + BMDMA_PRD_LOW);
1870 /* issue r/w command */
1871 ap->ops->sff_exec_command(ap, &qc->tf);
1875 * mv_bmdma_start - Start a BMDMA transaction
1876 * @qc: queued command to start DMA on.
1879 * Inherited from caller.
1881 static void mv_bmdma_start(struct ata_queued_cmd *qc)
1883 struct ata_port *ap = qc->ap;
1884 void __iomem *port_mmio = mv_ap_base(ap);
1885 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1886 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1888 /* start host DMA transaction */
1889 writelfl(cmd, port_mmio + BMDMA_CMD);
1893 * mv_bmdma_stop - Stop BMDMA transfer
1894 * @qc: queued command to stop DMA on.
1896 * Clears the ATA_DMA_START flag in the bmdma control register
1899 * Inherited from caller.
1901 static void mv_bmdma_stop_ap(struct ata_port *ap)
1903 void __iomem *port_mmio = mv_ap_base(ap);
1906 /* clear start/stop bit */
1907 cmd = readl(port_mmio + BMDMA_CMD);
1908 if (cmd & ATA_DMA_START) {
1909 cmd &= ~ATA_DMA_START;
1910 writelfl(cmd, port_mmio + BMDMA_CMD);
1912 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1913 ata_sff_dma_pause(ap);
1917 static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1919 mv_bmdma_stop_ap(qc->ap);
1923 * mv_bmdma_status - Read BMDMA status
1924 * @ap: port for which to retrieve DMA status.
1926 * Read and return equivalent of the sff BMDMA status register.
1929 * Inherited from caller.
1931 static u8 mv_bmdma_status(struct ata_port *ap)
1933 void __iomem *port_mmio = mv_ap_base(ap);
1937 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1938 * and the ATA_DMA_INTR bit doesn't exist.
1940 reg = readl(port_mmio + BMDMA_STATUS);
1941 if (reg & ATA_DMA_ACTIVE)
1942 status = ATA_DMA_ACTIVE;
1943 else if (reg & ATA_DMA_ERR)
1944 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1947 * Just because DMA_ACTIVE is 0 (DMA completed),
1948 * this does _not_ mean the device is "done".
1949 * So we should not yet be signalling ATA_DMA_INTR
1950 * in some cases. Eg. DSM/TRIM, and perhaps others.
1952 mv_bmdma_stop_ap(ap);
1953 if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY)
1956 status = ATA_DMA_INTR;
1961 static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
1963 struct ata_taskfile *tf = &qc->tf;
1965 * Workaround for 88SX60x1 FEr SATA#24.
1967 * Chip may corrupt WRITEs if multi_count >= 4kB.
1968 * Note that READs are unaffected.
1970 * It's not clear if this errata really means "4K bytes",
1971 * or if it always happens for multi_count > 7
1972 * regardless of device sector_size.
1974 * So, for safety, any write with multi_count > 7
1975 * gets converted here into a regular PIO write instead:
1977 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
1978 if (qc->dev->multi_count > 7) {
1979 switch (tf->command) {
1980 case ATA_CMD_WRITE_MULTI:
1981 tf->command = ATA_CMD_PIO_WRITE;
1983 case ATA_CMD_WRITE_MULTI_FUA_EXT:
1984 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
1986 case ATA_CMD_WRITE_MULTI_EXT:
1987 tf->command = ATA_CMD_PIO_WRITE_EXT;
1995 * mv_qc_prep - Host specific command preparation.
1996 * @qc: queued command to prepare
1998 * This routine simply redirects to the general purpose routine
1999 * if command is not DMA. Else, it handles prep of the CRQB
2000 * (command request block), does some sanity checking, and calls
2001 * the SG load routine.
2004 * Inherited from caller.
2006 static void mv_qc_prep(struct ata_queued_cmd *qc)
2008 struct ata_port *ap = qc->ap;
2009 struct mv_port_priv *pp = ap->private_data;
2011 struct ata_taskfile *tf = &qc->tf;
2015 switch (tf->protocol) {
2017 if (tf->command == ATA_CMD_DSM)
2021 break; /* continue below */
2023 mv_rw_multi_errata_sata24(qc);
2029 /* Fill in command request block
2031 if (!(tf->flags & ATA_TFLAG_WRITE))
2032 flags |= CRQB_FLAG_READ;
2033 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2034 flags |= qc->tag << CRQB_TAG_SHIFT;
2035 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2037 /* get current queue index from software */
2038 in_index = pp->req_idx;
2040 pp->crqb[in_index].sg_addr =
2041 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2042 pp->crqb[in_index].sg_addr_hi =
2043 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2044 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
2046 cw = &pp->crqb[in_index].ata_cmd[0];
2048 /* Sadly, the CRQB cannot accommodate all registers--there are
2049 * only 11 bytes...so we must pick and choose required
2050 * registers based on the command. So, we drop feature and
2051 * hob_feature for [RW] DMA commands, but they are needed for
2052 * NCQ. NCQ will drop hob_nsect, which is not needed there
2053 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
2055 switch (tf->command) {
2057 case ATA_CMD_READ_EXT:
2059 case ATA_CMD_WRITE_EXT:
2060 case ATA_CMD_WRITE_FUA_EXT:
2061 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
2063 case ATA_CMD_FPDMA_READ:
2064 case ATA_CMD_FPDMA_WRITE:
2065 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
2066 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
2069 /* The only other commands EDMA supports in non-queued and
2070 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
2071 * of which are defined/used by Linux. If we get here, this
2072 * driver needs work.
2074 * FIXME: modify libata to give qc_prep a return value and
2075 * return error here.
2077 BUG_ON(tf->command);
2080 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
2081 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
2082 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
2083 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
2084 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
2085 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
2086 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
2087 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
2088 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
2090 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2096 * mv_qc_prep_iie - Host specific command preparation.
2097 * @qc: queued command to prepare
2099 * This routine simply redirects to the general purpose routine
2100 * if command is not DMA. Else, it handles prep of the CRQB
2101 * (command request block), does some sanity checking, and calls
2102 * the SG load routine.
2105 * Inherited from caller.
2107 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
2109 struct ata_port *ap = qc->ap;
2110 struct mv_port_priv *pp = ap->private_data;
2111 struct mv_crqb_iie *crqb;
2112 struct ata_taskfile *tf = &qc->tf;
2116 if ((tf->protocol != ATA_PROT_DMA) &&
2117 (tf->protocol != ATA_PROT_NCQ))
2119 if (tf->command == ATA_CMD_DSM)
2120 return; /* use bmdma for this */
2122 /* Fill in Gen IIE command request block */
2123 if (!(tf->flags & ATA_TFLAG_WRITE))
2124 flags |= CRQB_FLAG_READ;
2126 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2127 flags |= qc->tag << CRQB_TAG_SHIFT;
2128 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
2129 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2131 /* get current queue index from software */
2132 in_index = pp->req_idx;
2134 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
2135 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2136 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2137 crqb->flags = cpu_to_le32(flags);
2139 crqb->ata_cmd[0] = cpu_to_le32(
2140 (tf->command << 16) |
2143 crqb->ata_cmd[1] = cpu_to_le32(
2149 crqb->ata_cmd[2] = cpu_to_le32(
2150 (tf->hob_lbal << 0) |
2151 (tf->hob_lbam << 8) |
2152 (tf->hob_lbah << 16) |
2153 (tf->hob_feature << 24)
2155 crqb->ata_cmd[3] = cpu_to_le32(
2157 (tf->hob_nsect << 8)
2160 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2166 * mv_sff_check_status - fetch device status, if valid
2167 * @ap: ATA port to fetch status from
2169 * When using command issue via mv_qc_issue_fis(),
2170 * the initial ATA_BUSY state does not show up in the
2171 * ATA status (shadow) register. This can confuse libata!
2173 * So we have a hook here to fake ATA_BUSY for that situation,
2174 * until the first time a BUSY, DRQ, or ERR bit is seen.
2176 * The rest of the time, it simply returns the ATA status register.
2178 static u8 mv_sff_check_status(struct ata_port *ap)
2180 u8 stat = ioread8(ap->ioaddr.status_addr);
2181 struct mv_port_priv *pp = ap->private_data;
2183 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2184 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2185 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2193 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2194 * @fis: fis to be sent
2195 * @nwords: number of 32-bit words in the fis
2197 static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2199 void __iomem *port_mmio = mv_ap_base(ap);
2200 u32 ifctl, old_ifctl, ifstat;
2201 int i, timeout = 200, final_word = nwords - 1;
2203 /* Initiate FIS transmission mode */
2204 old_ifctl = readl(port_mmio + SATA_IFCTL);
2205 ifctl = 0x100 | (old_ifctl & 0xf);
2206 writelfl(ifctl, port_mmio + SATA_IFCTL);
2208 /* Send all words of the FIS except for the final word */
2209 for (i = 0; i < final_word; ++i)
2210 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
2212 /* Flag end-of-transmission, and then send the final word */
2213 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
2214 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
2217 * Wait for FIS transmission to complete.
2218 * This typically takes just a single iteration.
2221 ifstat = readl(port_mmio + SATA_IFSTAT);
2222 } while (!(ifstat & 0x1000) && --timeout);
2224 /* Restore original port configuration */
2225 writelfl(old_ifctl, port_mmio + SATA_IFCTL);
2227 /* See if it worked */
2228 if ((ifstat & 0x3000) != 0x1000) {
2229 ata_port_warn(ap, "%s transmission error, ifstat=%08x\n",
2231 return AC_ERR_OTHER;
2237 * mv_qc_issue_fis - Issue a command directly as a FIS
2238 * @qc: queued command to start
2240 * Note that the ATA shadow registers are not updated
2241 * after command issue, so the device will appear "READY"
2242 * if polled, even while it is BUSY processing the command.
2244 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2246 * Note: we don't get updated shadow regs on *completion*
2247 * of non-data commands. So avoid sending them via this function,
2248 * as they will appear to have completed immediately.
2250 * GEN_IIE has special registers that we could get the result tf from,
2251 * but earlier chipsets do not. For now, we ignore those registers.
2253 static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2255 struct ata_port *ap = qc->ap;
2256 struct mv_port_priv *pp = ap->private_data;
2257 struct ata_link *link = qc->dev->link;
2261 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
2262 err = mv_send_fis(ap, fis, ARRAY_SIZE(fis));
2266 switch (qc->tf.protocol) {
2267 case ATAPI_PROT_PIO:
2268 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2270 case ATAPI_PROT_NODATA:
2271 ap->hsm_task_state = HSM_ST_FIRST;
2274 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2275 if (qc->tf.flags & ATA_TFLAG_WRITE)
2276 ap->hsm_task_state = HSM_ST_FIRST;
2278 ap->hsm_task_state = HSM_ST;
2281 ap->hsm_task_state = HSM_ST_LAST;
2285 if (qc->tf.flags & ATA_TFLAG_POLLING)
2286 ata_sff_queue_pio_task(link, 0);
2291 * mv_qc_issue - Initiate a command to the host
2292 * @qc: queued command to start
2294 * This routine simply redirects to the general purpose routine
2295 * if command is not DMA. Else, it sanity checks our local
2296 * caches of the request producer/consumer indices then enables
2297 * DMA and bumps the request producer index.
2300 * Inherited from caller.
2302 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
2304 static int limit_warnings = 10;
2305 struct ata_port *ap = qc->ap;
2306 void __iomem *port_mmio = mv_ap_base(ap);
2307 struct mv_port_priv *pp = ap->private_data;
2309 unsigned int port_irqs;
2311 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2313 switch (qc->tf.protocol) {
2315 if (qc->tf.command == ATA_CMD_DSM) {
2316 if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */
2317 return AC_ERR_OTHER;
2318 break; /* use bmdma for this */
2322 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2323 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2324 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2326 /* Write the request in pointer to kick the EDMA to life */
2327 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
2328 port_mmio + EDMA_REQ_Q_IN_PTR);
2333 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2335 * Someday, we might implement special polling workarounds
2336 * for these, but it all seems rather unnecessary since we
2337 * normally use only DMA for commands which transfer more
2338 * than a single block of data.
2340 * Much of the time, this could just work regardless.
2341 * So for now, just log the incident, and allow the attempt.
2343 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
2345 ata_link_warn(qc->dev->link, DRV_NAME
2346 ": attempting PIO w/multiple DRQ: "
2347 "this may fail due to h/w errata\n");
2350 case ATA_PROT_NODATA:
2351 case ATAPI_PROT_PIO:
2352 case ATAPI_PROT_NODATA:
2353 if (ap->flags & ATA_FLAG_PIO_POLLING)
2354 qc->tf.flags |= ATA_TFLAG_POLLING;
2358 if (qc->tf.flags & ATA_TFLAG_POLLING)
2359 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2361 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2364 * We're about to send a non-EDMA capable command to the
2365 * port. Turn off EDMA so there won't be problems accessing
2366 * shadow block, etc registers.
2369 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2370 mv_pmp_select(ap, qc->dev->link->pmp);
2372 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2373 struct mv_host_priv *hpriv = ap->host->private_data;
2375 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
2377 * After any NCQ error, the READ_LOG_EXT command
2378 * from libata-eh *must* use mv_qc_issue_fis().
2379 * Otherwise it might fail, due to chip errata.
2381 * Rather than special-case it, we'll just *always*
2382 * use this method here for READ_LOG_EXT, making for
2385 if (IS_GEN_II(hpriv))
2386 return mv_qc_issue_fis(qc);
2388 return ata_bmdma_qc_issue(qc);
2391 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2393 struct mv_port_priv *pp = ap->private_data;
2394 struct ata_queued_cmd *qc;
2396 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2398 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2399 if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))
2404 static void mv_pmp_error_handler(struct ata_port *ap)
2406 unsigned int pmp, pmp_map;
2407 struct mv_port_priv *pp = ap->private_data;
2409 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2411 * Perform NCQ error analysis on failed PMPs
2412 * before we freeze the port entirely.
2414 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2416 pmp_map = pp->delayed_eh_pmp_map;
2417 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2418 for (pmp = 0; pmp_map != 0; pmp++) {
2419 unsigned int this_pmp = (1 << pmp);
2420 if (pmp_map & this_pmp) {
2421 struct ata_link *link = &ap->pmp_link[pmp];
2422 pmp_map &= ~this_pmp;
2423 ata_eh_analyze_ncq_error(link);
2426 ata_port_freeze(ap);
2428 sata_pmp_error_handler(ap);
2431 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2433 void __iomem *port_mmio = mv_ap_base(ap);
2435 return readl(port_mmio + SATA_TESTCTL) >> 16;
2438 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2440 struct ata_eh_info *ehi;
2444 * Initialize EH info for PMPs which saw device errors
2446 ehi = &ap->link.eh_info;
2447 for (pmp = 0; pmp_map != 0; pmp++) {
2448 unsigned int this_pmp = (1 << pmp);
2449 if (pmp_map & this_pmp) {
2450 struct ata_link *link = &ap->pmp_link[pmp];
2452 pmp_map &= ~this_pmp;
2453 ehi = &link->eh_info;
2454 ata_ehi_clear_desc(ehi);
2455 ata_ehi_push_desc(ehi, "dev err");
2456 ehi->err_mask |= AC_ERR_DEV;
2457 ehi->action |= ATA_EH_RESET;
2458 ata_link_abort(link);
2463 static int mv_req_q_empty(struct ata_port *ap)
2465 void __iomem *port_mmio = mv_ap_base(ap);
2466 u32 in_ptr, out_ptr;
2468 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
2469 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2470 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
2471 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2472 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2475 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2477 struct mv_port_priv *pp = ap->private_data;
2479 unsigned int old_map, new_map;
2482 * Device error during FBS+NCQ operation:
2484 * Set a port flag to prevent further I/O being enqueued.
2485 * Leave the EDMA running to drain outstanding commands from this port.
2486 * Perform the post-mortem/EH only when all responses are complete.
2487 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2489 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2490 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2491 pp->delayed_eh_pmp_map = 0;
2493 old_map = pp->delayed_eh_pmp_map;
2494 new_map = old_map | mv_get_err_pmp_map(ap);
2496 if (old_map != new_map) {
2497 pp->delayed_eh_pmp_map = new_map;
2498 mv_pmp_eh_prep(ap, new_map & ~old_map);
2500 failed_links = hweight16(new_map);
2503 "%s: pmp_map=%04x qc_map=%04x failed_links=%d nr_active_links=%d\n",
2504 __func__, pp->delayed_eh_pmp_map,
2505 ap->qc_active, failed_links,
2506 ap->nr_active_links);
2508 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
2509 mv_process_crpb_entries(ap, pp);
2512 ata_port_info(ap, "%s: done\n", __func__);
2513 return 1; /* handled */
2515 ata_port_info(ap, "%s: waiting\n", __func__);
2516 return 1; /* handled */
2519 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2522 * Possible future enhancement:
2524 * FBS+non-NCQ operation is not yet implemented.
2525 * See related notes in mv_edma_cfg().
2527 * Device error during FBS+non-NCQ operation:
2529 * We need to snapshot the shadow registers for each failed command.
2530 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2532 return 0; /* not handled */
2535 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2537 struct mv_port_priv *pp = ap->private_data;
2539 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2540 return 0; /* EDMA was not active: not handled */
2541 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2542 return 0; /* FBS was not active: not handled */
2544 if (!(edma_err_cause & EDMA_ERR_DEV))
2545 return 0; /* non DEV error: not handled */
2546 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2547 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2548 return 0; /* other problems: not handled */
2550 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2552 * EDMA should NOT have self-disabled for this case.
2553 * If it did, then something is wrong elsewhere,
2554 * and we cannot handle it here.
2556 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2557 ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n",
2558 __func__, edma_err_cause, pp->pp_flags);
2559 return 0; /* not handled */
2561 return mv_handle_fbs_ncq_dev_err(ap);
2564 * EDMA should have self-disabled for this case.
2565 * If it did not, then something is wrong elsewhere,
2566 * and we cannot handle it here.
2568 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2569 ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n",
2570 __func__, edma_err_cause, pp->pp_flags);
2571 return 0; /* not handled */
2573 return mv_handle_fbs_non_ncq_dev_err(ap);
2575 return 0; /* not handled */
2578 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
2580 struct ata_eh_info *ehi = &ap->link.eh_info;
2581 char *when = "idle";
2583 ata_ehi_clear_desc(ehi);
2584 if (edma_was_enabled) {
2585 when = "EDMA enabled";
2587 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2588 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
2591 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
2592 ehi->err_mask |= AC_ERR_OTHER;
2593 ehi->action |= ATA_EH_RESET;
2594 ata_port_freeze(ap);
2598 * mv_err_intr - Handle error interrupts on the port
2599 * @ap: ATA channel to manipulate
2601 * Most cases require a full reset of the chip's state machine,
2602 * which also performs a COMRESET.
2603 * Also, if the port disabled DMA, update our cached copy to match.
2606 * Inherited from caller.
2608 static void mv_err_intr(struct ata_port *ap)
2610 void __iomem *port_mmio = mv_ap_base(ap);
2611 u32 edma_err_cause, eh_freeze_mask, serr = 0;
2613 struct mv_port_priv *pp = ap->private_data;
2614 struct mv_host_priv *hpriv = ap->host->private_data;
2615 unsigned int action = 0, err_mask = 0;
2616 struct ata_eh_info *ehi = &ap->link.eh_info;
2617 struct ata_queued_cmd *qc;
2621 * Read and clear the SError and err_cause bits.
2622 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2623 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
2625 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2626 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2628 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
2629 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2630 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
2631 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
2633 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
2635 if (edma_err_cause & EDMA_ERR_DEV) {
2637 * Device errors during FIS-based switching operation
2638 * require special handling.
2640 if (mv_handle_dev_err(ap, edma_err_cause))
2644 qc = mv_get_active_qc(ap);
2645 ata_ehi_clear_desc(ehi);
2646 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2647 edma_err_cause, pp->pp_flags);
2649 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2650 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
2651 if (fis_cause & FIS_IRQ_CAUSE_AN) {
2652 u32 ec = edma_err_cause &
2653 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2654 sata_async_notification(ap);
2656 return; /* Just an AN; no need for the nukes */
2657 ata_ehi_push_desc(ehi, "SDB notify");
2661 * All generations share these EDMA error cause bits:
2663 if (edma_err_cause & EDMA_ERR_DEV) {
2664 err_mask |= AC_ERR_DEV;
2665 action |= ATA_EH_RESET;
2666 ata_ehi_push_desc(ehi, "dev error");
2668 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
2669 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
2670 EDMA_ERR_INTRL_PAR)) {
2671 err_mask |= AC_ERR_ATA_BUS;
2672 action |= ATA_EH_RESET;
2673 ata_ehi_push_desc(ehi, "parity error");
2675 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2676 ata_ehi_hotplugged(ehi);
2677 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
2678 "dev disconnect" : "dev connect");
2679 action |= ATA_EH_RESET;
2683 * Gen-I has a different SELF_DIS bit,
2684 * different FREEZE bits, and no SERR bit:
2686 if (IS_GEN_I(hpriv)) {
2687 eh_freeze_mask = EDMA_EH_FREEZE_5;
2688 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
2689 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2690 ata_ehi_push_desc(ehi, "EDMA self-disable");
2693 eh_freeze_mask = EDMA_EH_FREEZE;
2694 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2695 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2696 ata_ehi_push_desc(ehi, "EDMA self-disable");
2698 if (edma_err_cause & EDMA_ERR_SERR) {
2699 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2700 err_mask |= AC_ERR_ATA_BUS;
2701 action |= ATA_EH_RESET;
2706 err_mask = AC_ERR_OTHER;
2707 action |= ATA_EH_RESET;
2710 ehi->serror |= serr;
2711 ehi->action |= action;
2714 qc->err_mask |= err_mask;
2716 ehi->err_mask |= err_mask;
2718 if (err_mask == AC_ERR_DEV) {
2720 * Cannot do ata_port_freeze() here,
2721 * because it would kill PIO access,
2722 * which is needed for further diagnosis.
2726 } else if (edma_err_cause & eh_freeze_mask) {
2728 * Note to self: ata_port_freeze() calls ata_port_abort()
2730 ata_port_freeze(ap);
2737 ata_link_abort(qc->dev->link);
2743 static bool mv_process_crpb_response(struct ata_port *ap,
2744 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2747 u16 edma_status = le16_to_cpu(response->flags);
2750 * edma_status from a response queue entry:
2751 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
2752 * MSB is saved ATA status from command completion.
2755 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2758 * Error will be seen/handled by
2759 * mv_err_intr(). So do nothing at all here.
2764 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2765 if (!ac_err_mask(ata_status))
2767 /* else: leave it for mv_err_intr() */
2771 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
2773 void __iomem *port_mmio = mv_ap_base(ap);
2774 struct mv_host_priv *hpriv = ap->host->private_data;
2776 bool work_done = false;
2778 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
2780 /* Get the hardware queue position index */
2781 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
2782 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2784 /* Process new responses from since the last time we looked */
2785 while (in_index != pp->resp_idx) {
2787 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
2789 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2791 if (IS_GEN_I(hpriv)) {
2792 /* 50xx: no NCQ, only one command active at a time */
2793 tag = ap->link.active_tag;
2795 /* Gen II/IIE: get command tag from CRPB entry */
2796 tag = le16_to_cpu(response->id) & 0x1f;
2798 if (mv_process_crpb_response(ap, response, tag, ncq_enabled))
2799 done_mask |= 1 << tag;
2804 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
2806 /* Update the software queue position index in hardware */
2807 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2808 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2809 port_mmio + EDMA_RSP_Q_OUT_PTR);
2813 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2815 struct mv_port_priv *pp;
2816 int edma_was_enabled;
2819 * Grab a snapshot of the EDMA_EN flag setting,
2820 * so that we have a consistent view for this port,
2821 * even if something we call of our routines changes it.
2823 pp = ap->private_data;
2824 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2826 * Process completed CRPB response(s) before other events.
2828 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2829 mv_process_crpb_entries(ap, pp);
2830 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2831 mv_handle_fbs_ncq_dev_err(ap);
2834 * Handle chip-reported errors, or continue on to handle PIO.
2836 if (unlikely(port_cause & ERR_IRQ)) {
2838 } else if (!edma_was_enabled) {
2839 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2841 ata_bmdma_port_intr(ap, qc);
2843 mv_unexpected_intr(ap, edma_was_enabled);
2848 * mv_host_intr - Handle all interrupts on the given host controller
2849 * @host: host specific structure
2850 * @main_irq_cause: Main interrupt cause register for the chip.
2853 * Inherited from caller.
2855 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2857 struct mv_host_priv *hpriv = host->private_data;
2858 void __iomem *mmio = hpriv->base, *hc_mmio;
2859 unsigned int handled = 0, port;
2861 /* If asserted, clear the "all ports" IRQ coalescing bit */
2862 if (main_irq_cause & ALL_PORTS_COAL_DONE)
2863 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
2865 for (port = 0; port < hpriv->n_ports; port++) {
2866 struct ata_port *ap = host->ports[port];
2867 unsigned int p, shift, hardport, port_cause;
2869 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2871 * Each hc within the host has its own hc_irq_cause register,
2872 * where the interrupting ports bits get ack'd.
2874 if (hardport == 0) { /* first port on this hc ? */
2875 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2876 u32 port_mask, ack_irqs;
2878 * Skip this entire hc if nothing pending for any ports
2881 port += MV_PORTS_PER_HC - 1;
2885 * We don't need/want to read the hc_irq_cause register,
2886 * because doing so hurts performance, and
2887 * main_irq_cause already gives us everything we need.
2889 * But we do have to *write* to the hc_irq_cause to ack
2890 * the ports that we are handling this time through.
2892 * This requires that we create a bitmap for those
2893 * ports which interrupted us, and use that bitmap
2894 * to ack (only) those ports via hc_irq_cause.
2897 if (hc_cause & PORTS_0_3_COAL_DONE)
2898 ack_irqs = HC_COAL_IRQ;
2899 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2900 if ((port + p) >= hpriv->n_ports)
2902 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2903 if (hc_cause & port_mask)
2904 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2906 hc_mmio = mv_hc_base_from_port(mmio, port);
2907 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
2911 * Handle interrupts signalled for this port:
2913 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2915 mv_port_intr(ap, port_cause);
2920 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2922 struct mv_host_priv *hpriv = host->private_data;
2923 struct ata_port *ap;
2924 struct ata_queued_cmd *qc;
2925 struct ata_eh_info *ehi;
2926 unsigned int i, err_mask, printed = 0;
2929 err_cause = readl(mmio + hpriv->irq_cause_offset);
2931 dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause);
2933 DPRINTK("All regs @ PCI error\n");
2934 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2936 writelfl(0, mmio + hpriv->irq_cause_offset);
2938 for (i = 0; i < host->n_ports; i++) {
2939 ap = host->ports[i];
2940 if (!ata_link_offline(&ap->link)) {
2941 ehi = &ap->link.eh_info;
2942 ata_ehi_clear_desc(ehi);
2944 ata_ehi_push_desc(ehi,
2945 "PCI err cause 0x%08x", err_cause);
2946 err_mask = AC_ERR_HOST_BUS;
2947 ehi->action = ATA_EH_RESET;
2948 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2950 qc->err_mask |= err_mask;
2952 ehi->err_mask |= err_mask;
2954 ata_port_freeze(ap);
2957 return 1; /* handled */
2961 * mv_interrupt - Main interrupt event handler
2963 * @dev_instance: private data; in this case the host structure
2965 * Read the read only register to determine if any host
2966 * controllers have pending interrupts. If so, call lower level
2967 * routine to handle. Also check for PCI errors which are only
2971 * This routine holds the host lock while processing pending
2974 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2976 struct ata_host *host = dev_instance;
2977 struct mv_host_priv *hpriv = host->private_data;
2978 unsigned int handled = 0;
2979 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
2980 u32 main_irq_cause, pending_irqs;
2982 spin_lock(&host->lock);
2984 /* for MSI: block new interrupts while in here */
2986 mv_write_main_irq_mask(0, hpriv);
2988 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2989 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
2991 * Deal with cases where we either have nothing pending, or have read
2992 * a bogus register value which can indicate HW removal or PCI fault.
2994 if (pending_irqs && main_irq_cause != 0xffffffffU) {
2995 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
2996 handled = mv_pci_error(host, hpriv->base);
2998 handled = mv_host_intr(host, pending_irqs);
3001 /* for MSI: unmask; interrupt cause bits will retrigger now */
3003 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
3005 spin_unlock(&host->lock);
3007 return IRQ_RETVAL(handled);
3010 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
3014 switch (sc_reg_in) {
3018 ofs = sc_reg_in * sizeof(u32);
3027 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
3029 struct mv_host_priv *hpriv = link->ap->host->private_data;
3030 void __iomem *mmio = hpriv->base;
3031 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
3032 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3034 if (ofs != 0xffffffffU) {
3035 *val = readl(addr + ofs);
3041 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
3043 struct mv_host_priv *hpriv = link->ap->host->private_data;
3044 void __iomem *mmio = hpriv->base;
3045 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
3046 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3048 if (ofs != 0xffffffffU) {
3049 writelfl(val, addr + ofs);
3055 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
3057 struct pci_dev *pdev = to_pci_dev(host->dev);
3060 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
3063 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3065 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3068 mv_reset_pci_bus(host, mmio);
3071 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3073 writel(0x0fcfffff, mmio + FLASH_CTL);
3076 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
3079 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
3082 tmp = readl(phy_mmio + MV5_PHY_MODE);
3084 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3085 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
3088 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3092 writel(0, mmio + GPIO_PORT_CTL);
3094 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
3096 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3098 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3101 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3104 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
3105 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
3107 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
3110 tmp = readl(phy_mmio + MV5_LTMODE);
3112 writel(tmp, phy_mmio + MV5_LTMODE);
3114 tmp = readl(phy_mmio + MV5_PHY_CTL);
3117 writel(tmp, phy_mmio + MV5_PHY_CTL);
3120 tmp = readl(phy_mmio + MV5_PHY_MODE);
3122 tmp |= hpriv->signal[port].pre;
3123 tmp |= hpriv->signal[port].amps;
3124 writel(tmp, phy_mmio + MV5_PHY_MODE);
3129 #define ZERO(reg) writel(0, port_mmio + (reg))
3130 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
3133 void __iomem *port_mmio = mv_port_base(mmio, port);
3135 mv_reset_channel(hpriv, mmio, port);
3137 ZERO(0x028); /* command */
3138 writel(0x11f, port_mmio + EDMA_CFG);
3139 ZERO(0x004); /* timer */
3140 ZERO(0x008); /* irq err cause */
3141 ZERO(0x00c); /* irq err mask */
3142 ZERO(0x010); /* rq bah */
3143 ZERO(0x014); /* rq inp */
3144 ZERO(0x018); /* rq outp */
3145 ZERO(0x01c); /* respq bah */
3146 ZERO(0x024); /* respq outp */
3147 ZERO(0x020); /* respq inp */
3148 ZERO(0x02c); /* test control */
3149 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
3153 #define ZERO(reg) writel(0, hc_mmio + (reg))
3154 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3157 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3165 tmp = readl(hc_mmio + 0x20);
3168 writel(tmp, hc_mmio + 0x20);
3172 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3175 unsigned int hc, port;
3177 for (hc = 0; hc < n_hc; hc++) {
3178 for (port = 0; port < MV_PORTS_PER_HC; port++)
3179 mv5_reset_hc_port(hpriv, mmio,
3180 (hc * MV_PORTS_PER_HC) + port);
3182 mv5_reset_one_hc(hpriv, mmio, hc);
3189 #define ZERO(reg) writel(0, mmio + (reg))
3190 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
3192 struct mv_host_priv *hpriv = host->private_data;
3195 tmp = readl(mmio + MV_PCI_MODE);
3197 writel(tmp, mmio + MV_PCI_MODE);
3199 ZERO(MV_PCI_DISC_TIMER);
3200 ZERO(MV_PCI_MSI_TRIGGER);
3201 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
3202 ZERO(MV_PCI_SERR_MASK);
3203 ZERO(hpriv->irq_cause_offset);
3204 ZERO(hpriv->irq_mask_offset);
3205 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3206 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3207 ZERO(MV_PCI_ERR_ATTRIBUTE);
3208 ZERO(MV_PCI_ERR_COMMAND);
3212 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3216 mv5_reset_flash(hpriv, mmio);
3218 tmp = readl(mmio + GPIO_PORT_CTL);
3220 tmp |= (1 << 5) | (1 << 6);
3221 writel(tmp, mmio + GPIO_PORT_CTL);
3225 * mv6_reset_hc - Perform the 6xxx global soft reset
3226 * @mmio: base address of the HBA
3228 * This routine only applies to 6xxx parts.
3231 * Inherited from caller.
3233 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3236 void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
3240 /* Following procedure defined in PCI "main command and status
3244 writel(t | STOP_PCI_MASTER, reg);
3246 for (i = 0; i < 1000; i++) {
3249 if (PCI_MASTER_EMPTY & t)
3252 if (!(PCI_MASTER_EMPTY & t)) {
3253 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3261 writel(t | GLOB_SFT_RST, reg);
3264 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3266 if (!(GLOB_SFT_RST & t)) {
3267 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3272 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3275 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3278 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3280 if (GLOB_SFT_RST & t) {
3281 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3288 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
3291 void __iomem *port_mmio;
3294 tmp = readl(mmio + RESET_CFG);
3295 if ((tmp & (1 << 0)) == 0) {
3296 hpriv->signal[idx].amps = 0x7 << 8;
3297 hpriv->signal[idx].pre = 0x1 << 5;
3301 port_mmio = mv_port_base(mmio, idx);
3302 tmp = readl(port_mmio + PHY_MODE2);
3304 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3305 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3308 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3310 writel(0x00000060, mmio + GPIO_PORT_CTL);
3313 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3316 void __iomem *port_mmio = mv_port_base(mmio, port);
3318 u32 hp_flags = hpriv->hp_flags;
3320 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3322 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3325 if (fix_phy_mode2) {
3326 m2 = readl(port_mmio + PHY_MODE2);
3329 writel(m2, port_mmio + PHY_MODE2);
3333 m2 = readl(port_mmio + PHY_MODE2);
3334 m2 &= ~((1 << 16) | (1 << 31));
3335 writel(m2, port_mmio + PHY_MODE2);
3341 * Gen-II/IIe PHY_MODE3 errata RM#2:
3342 * Achieves better receiver noise performance than the h/w default:
3344 m3 = readl(port_mmio + PHY_MODE3);
3345 m3 = (m3 & 0x1f) | (0x5555601 << 5);
3347 /* Guideline 88F5182 (GL# SATA-S11) */
3351 if (fix_phy_mode4) {
3352 u32 m4 = readl(port_mmio + PHY_MODE4);
3354 * Enforce reserved-bit restrictions on GenIIe devices only.
3355 * For earlier chipsets, force only the internal config field
3356 * (workaround for errata FEr SATA#10 part 1).
3358 if (IS_GEN_IIE(hpriv))
3359 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3361 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
3362 writel(m4, port_mmio + PHY_MODE4);
3365 * Workaround for 60x1-B2 errata SATA#13:
3366 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3367 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
3368 * Or ensure we use writelfl() when writing PHY_MODE4.
3370 writel(m3, port_mmio + PHY_MODE3);
3372 /* Revert values of pre-emphasis and signal amps to the saved ones */
3373 m2 = readl(port_mmio + PHY_MODE2);
3375 m2 &= ~MV_M2_PREAMP_MASK;
3376 m2 |= hpriv->signal[port].amps;
3377 m2 |= hpriv->signal[port].pre;
3380 /* according to mvSata 3.6.1, some IIE values are fixed */
3381 if (IS_GEN_IIE(hpriv)) {
3386 writel(m2, port_mmio + PHY_MODE2);
3389 /* TODO: use the generic LED interface to configure the SATA Presence */
3390 /* & Acitivy LEDs on the board */
3391 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3397 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3400 void __iomem *port_mmio;
3403 port_mmio = mv_port_base(mmio, idx);
3404 tmp = readl(port_mmio + PHY_MODE2);
3406 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3407 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3411 #define ZERO(reg) writel(0, port_mmio + (reg))
3412 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3413 void __iomem *mmio, unsigned int port)
3415 void __iomem *port_mmio = mv_port_base(mmio, port);
3417 mv_reset_channel(hpriv, mmio, port);
3419 ZERO(0x028); /* command */
3420 writel(0x101f, port_mmio + EDMA_CFG);
3421 ZERO(0x004); /* timer */
3422 ZERO(0x008); /* irq err cause */
3423 ZERO(0x00c); /* irq err mask */
3424 ZERO(0x010); /* rq bah */
3425 ZERO(0x014); /* rq inp */
3426 ZERO(0x018); /* rq outp */
3427 ZERO(0x01c); /* respq bah */
3428 ZERO(0x024); /* respq outp */
3429 ZERO(0x020); /* respq inp */
3430 ZERO(0x02c); /* test control */
3431 writel(0x800, port_mmio + EDMA_IORDY_TMOUT);
3436 #define ZERO(reg) writel(0, hc_mmio + (reg))
3437 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3440 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3450 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3451 void __iomem *mmio, unsigned int n_hc)
3455 for (port = 0; port < hpriv->n_ports; port++)
3456 mv_soc_reset_hc_port(hpriv, mmio, port);
3458 mv_soc_reset_one_hc(hpriv, mmio);
3463 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3469 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3474 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
3475 void __iomem *mmio, unsigned int port)
3477 void __iomem *port_mmio = mv_port_base(mmio, port);
3480 reg = readl(port_mmio + PHY_MODE3);
3481 reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
3483 reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
3485 writel(reg, port_mmio + PHY_MODE3);
3487 reg = readl(port_mmio + PHY_MODE4);
3488 reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
3490 writel(reg, port_mmio + PHY_MODE4);
3492 reg = readl(port_mmio + PHY_MODE9_GEN2);
3493 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3495 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3496 writel(reg, port_mmio + PHY_MODE9_GEN2);
3498 reg = readl(port_mmio + PHY_MODE9_GEN1);
3499 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3501 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3502 writel(reg, port_mmio + PHY_MODE9_GEN1);
3506 * soc_is_65 - check if the soc is 65 nano device
3508 * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
3509 * register, this register should contain non-zero value and it exists only
3510 * in the 65 nano devices, when reading it from older devices we get 0.
3512 static bool soc_is_65n(struct mv_host_priv *hpriv)
3514 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3516 if (readl(port0_mmio + PHYCFG_OFS))
3521 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
3523 u32 ifcfg = readl(port_mmio + SATA_IFCFG);
3525 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
3527 ifcfg |= (1 << 7); /* enable gen2i speed */
3528 writelfl(ifcfg, port_mmio + SATA_IFCFG);
3531 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
3532 unsigned int port_no)
3534 void __iomem *port_mmio = mv_port_base(mmio, port_no);
3537 * The datasheet warns against setting EDMA_RESET when EDMA is active
3538 * (but doesn't say what the problem might be). So we first try
3539 * to disable the EDMA engine before doing the EDMA_RESET operation.
3541 mv_stop_edma_engine(port_mmio);
3542 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3544 if (!IS_GEN_I(hpriv)) {
3545 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3546 mv_setup_ifcfg(port_mmio, 1);
3549 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
3550 * link, and physical layers. It resets all SATA interface registers
3551 * (except for SATA_IFCFG), and issues a COMRESET to the dev.
3553 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3554 udelay(25); /* allow reset propagation */
3555 writelfl(0, port_mmio + EDMA_CMD);
3557 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3559 if (IS_GEN_I(hpriv))
3563 static void mv_pmp_select(struct ata_port *ap, int pmp)
3565 if (sata_pmp_supported(ap)) {
3566 void __iomem *port_mmio = mv_ap_base(ap);
3567 u32 reg = readl(port_mmio + SATA_IFCTL);
3568 int old = reg & 0xf;
3571 reg = (reg & ~0xf) | pmp;
3572 writelfl(reg, port_mmio + SATA_IFCTL);
3577 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3578 unsigned long deadline)
3580 mv_pmp_select(link->ap, sata_srst_pmp(link));
3581 return sata_std_hardreset(link, class, deadline);
3584 static int mv_softreset(struct ata_link *link, unsigned int *class,
3585 unsigned long deadline)
3587 mv_pmp_select(link->ap, sata_srst_pmp(link));
3588 return ata_sff_softreset(link, class, deadline);
3591 static int mv_hardreset(struct ata_link *link, unsigned int *class,
3592 unsigned long deadline)
3594 struct ata_port *ap = link->ap;
3595 struct mv_host_priv *hpriv = ap->host->private_data;
3596 struct mv_port_priv *pp = ap->private_data;
3597 void __iomem *mmio = hpriv->base;
3598 int rc, attempts = 0, extra = 0;
3602 mv_reset_channel(hpriv, mmio, ap->port_no);
3603 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
3605 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
3607 /* Workaround for errata FEr SATA#10 (part 2) */
3609 const unsigned long *timing =
3610 sata_ehc_deb_timing(&link->eh_context);
3612 rc = sata_link_hardreset(link, timing, deadline + extra,
3614 rc = online ? -EAGAIN : rc;
3617 sata_scr_read(link, SCR_STATUS, &sstatus);
3618 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3619 /* Force 1.5gb/s link speed and try again */
3620 mv_setup_ifcfg(mv_ap_base(ap), 0);
3621 if (time_after(jiffies + HZ, deadline))
3622 extra = HZ; /* only extend it once, max */
3624 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
3625 mv_save_cached_regs(ap);
3626 mv_edma_cfg(ap, 0, 0);
3631 static void mv_eh_freeze(struct ata_port *ap)
3634 mv_enable_port_irqs(ap, 0);
3637 static void mv_eh_thaw(struct ata_port *ap)
3639 struct mv_host_priv *hpriv = ap->host->private_data;
3640 unsigned int port = ap->port_no;
3641 unsigned int hardport = mv_hardport_from_port(port);
3642 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3643 void __iomem *port_mmio = mv_ap_base(ap);
3646 /* clear EDMA errors on this port */
3647 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3649 /* clear pending irq events */
3650 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
3651 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
3653 mv_enable_port_irqs(ap, ERR_IRQ);
3657 * mv_port_init - Perform some early initialization on a single port.
3658 * @port: libata data structure storing shadow register addresses
3659 * @port_mmio: base address of the port
3661 * Initialize shadow register mmio addresses, clear outstanding
3662 * interrupts on the port, and unmask interrupts for the future
3663 * start of the port.
3666 * Inherited from caller.
3668 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
3670 void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
3672 /* PIO related setup
3674 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
3676 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3677 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3678 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3679 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3680 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3681 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
3683 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3684 /* special case: control/altstatus doesn't have ATA_REG_ address */
3685 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
3687 /* Clear any currently outstanding port interrupt conditions */
3688 serr = port_mmio + mv_scr_offset(SCR_ERROR);
3689 writelfl(readl(serr), serr);
3690 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3692 /* unmask all non-transient EDMA error interrupts */
3693 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
3695 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
3696 readl(port_mmio + EDMA_CFG),
3697 readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
3698 readl(port_mmio + EDMA_ERR_IRQ_MASK));
3701 static unsigned int mv_in_pcix_mode(struct ata_host *host)
3703 struct mv_host_priv *hpriv = host->private_data;
3704 void __iomem *mmio = hpriv->base;
3707 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
3708 return 0; /* not PCI-X capable */
3709 reg = readl(mmio + MV_PCI_MODE);
3710 if ((reg & MV_PCI_MODE_MASK) == 0)
3711 return 0; /* conventional PCI mode */
3712 return 1; /* chip is in PCI-X mode */
3715 static int mv_pci_cut_through_okay(struct ata_host *host)
3717 struct mv_host_priv *hpriv = host->private_data;
3718 void __iomem *mmio = hpriv->base;
3721 if (!mv_in_pcix_mode(host)) {
3722 reg = readl(mmio + MV_PCI_COMMAND);
3723 if (reg & MV_PCI_COMMAND_MRDTRIG)
3724 return 0; /* not okay */
3726 return 1; /* okay */
3729 static void mv_60x1b2_errata_pci7(struct ata_host *host)
3731 struct mv_host_priv *hpriv = host->private_data;
3732 void __iomem *mmio = hpriv->base;
3734 /* workaround for 60x1-B2 errata PCI#7 */
3735 if (mv_in_pcix_mode(host)) {
3736 u32 reg = readl(mmio + MV_PCI_COMMAND);
3737 writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
3741 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
3743 struct pci_dev *pdev = to_pci_dev(host->dev);
3744 struct mv_host_priv *hpriv = host->private_data;
3745 u32 hp_flags = hpriv->hp_flags;
3747 switch (board_idx) {
3749 hpriv->ops = &mv5xxx_ops;
3750 hp_flags |= MV_HP_GEN_I;
3752 switch (pdev->revision) {
3754 hp_flags |= MV_HP_ERRATA_50XXB0;
3757 hp_flags |= MV_HP_ERRATA_50XXB2;
3760 dev_warn(&pdev->dev,
3761 "Applying 50XXB2 workarounds to unknown rev\n");
3762 hp_flags |= MV_HP_ERRATA_50XXB2;
3769 hpriv->ops = &mv5xxx_ops;
3770 hp_flags |= MV_HP_GEN_I;
3772 switch (pdev->revision) {
3774 hp_flags |= MV_HP_ERRATA_50XXB0;
3777 hp_flags |= MV_HP_ERRATA_50XXB2;
3780 dev_warn(&pdev->dev,
3781 "Applying B2 workarounds to unknown rev\n");
3782 hp_flags |= MV_HP_ERRATA_50XXB2;
3789 hpriv->ops = &mv6xxx_ops;
3790 hp_flags |= MV_HP_GEN_II;
3792 switch (pdev->revision) {
3794 mv_60x1b2_errata_pci7(host);
3795 hp_flags |= MV_HP_ERRATA_60X1B2;
3798 hp_flags |= MV_HP_ERRATA_60X1C0;
3801 dev_warn(&pdev->dev,
3802 "Applying B2 workarounds to unknown rev\n");
3803 hp_flags |= MV_HP_ERRATA_60X1B2;
3809 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
3810 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3811 (pdev->device == 0x2300 || pdev->device == 0x2310))
3814 * Highpoint RocketRAID PCIe 23xx series cards:
3816 * Unconfigured drives are treated as "Legacy"
3817 * by the BIOS, and it overwrites sector 8 with
3818 * a "Lgcy" metadata block prior to Linux boot.
3820 * Configured drives (RAID or JBOD) leave sector 8
3821 * alone, but instead overwrite a high numbered
3822 * sector for the RAID metadata. This sector can
3823 * be determined exactly, by truncating the physical
3824 * drive capacity to a nice even GB value.
3826 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3828 * Warn the user, lest they think we're just buggy.
3830 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3831 " BIOS CORRUPTS DATA on all attached drives,"
3832 " regardless of if/how they are configured."
3834 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3835 " use sectors 8-9 on \"Legacy\" drives,"
3836 " and avoid the final two gigabytes on"
3837 " all RocketRAID BIOS initialized drives.\n");
3841 hpriv->ops = &mv6xxx_ops;
3842 hp_flags |= MV_HP_GEN_IIE;
3843 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3844 hp_flags |= MV_HP_CUT_THROUGH;
3846 switch (pdev->revision) {
3847 case 0x2: /* Rev.B0: the first/only public release */
3848 hp_flags |= MV_HP_ERRATA_60X1C0;
3851 dev_warn(&pdev->dev,
3852 "Applying 60X1C0 workarounds to unknown rev\n");
3853 hp_flags |= MV_HP_ERRATA_60X1C0;
3858 if (soc_is_65n(hpriv))
3859 hpriv->ops = &mv_soc_65n_ops;
3861 hpriv->ops = &mv_soc_ops;
3862 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3863 MV_HP_ERRATA_60X1C0;
3867 dev_err(host->dev, "BUG: invalid board index %u\n", board_idx);
3871 hpriv->hp_flags = hp_flags;
3872 if (hp_flags & MV_HP_PCIE) {
3873 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
3874 hpriv->irq_mask_offset = PCIE_IRQ_MASK;
3875 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3877 hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
3878 hpriv->irq_mask_offset = PCI_IRQ_MASK;
3879 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3886 * mv_init_host - Perform some early initialization of the host.
3887 * @host: ATA host to initialize
3889 * If possible, do an early global reset of the host. Then do
3890 * our port init and clear/unmask all/relevant host interrupts.
3893 * Inherited from caller.
3895 static int mv_init_host(struct ata_host *host)
3897 int rc = 0, n_hc, port, hc;
3898 struct mv_host_priv *hpriv = host->private_data;
3899 void __iomem *mmio = hpriv->base;
3901 rc = mv_chip_id(host, hpriv->board_idx);
3905 if (IS_SOC(hpriv)) {
3906 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
3907 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
3909 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
3910 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
3913 /* initialize shadow irq mask with register's value */
3914 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3916 /* global interrupt mask: 0 == mask everything */
3917 mv_set_main_irq_mask(host, ~0, 0);
3919 n_hc = mv_get_hc_count(host->ports[0]->flags);
3921 for (port = 0; port < host->n_ports; port++)
3922 if (hpriv->ops->read_preamp)
3923 hpriv->ops->read_preamp(hpriv, port, mmio);
3925 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3929 hpriv->ops->reset_flash(hpriv, mmio);
3930 hpriv->ops->reset_bus(host, mmio);
3931 hpriv->ops->enable_leds(hpriv, mmio);
3933 for (port = 0; port < host->n_ports; port++) {
3934 struct ata_port *ap = host->ports[port];
3935 void __iomem *port_mmio = mv_port_base(mmio, port);
3937 mv_port_init(&ap->ioaddr, port_mmio);
3940 for (hc = 0; hc < n_hc; hc++) {
3941 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3943 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3944 "(before clear)=0x%08x\n", hc,
3945 readl(hc_mmio + HC_CFG),
3946 readl(hc_mmio + HC_IRQ_CAUSE));
3948 /* Clear any currently outstanding hc interrupt conditions */
3949 writelfl(0, hc_mmio + HC_IRQ_CAUSE);
3952 if (!IS_SOC(hpriv)) {
3953 /* Clear any currently outstanding host interrupt conditions */
3954 writelfl(0, mmio + hpriv->irq_cause_offset);
3956 /* and unmask interrupt generation for host regs */
3957 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
3961 * enable only global host interrupts for now.
3962 * The per-port interrupts get done later as ports are set up.
3964 mv_set_main_irq_mask(host, 0, PCI_ERR);
3965 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3966 irq_coalescing_usecs);
3971 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3973 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3975 if (!hpriv->crqb_pool)
3978 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3980 if (!hpriv->crpb_pool)
3983 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3985 if (!hpriv->sg_tbl_pool)
3991 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3992 const struct mbus_dram_target_info *dram)
3996 for (i = 0; i < 4; i++) {
3997 writel(0, hpriv->base + WINDOW_CTRL(i));
3998 writel(0, hpriv->base + WINDOW_BASE(i));
4001 for (i = 0; i < dram->num_cs; i++) {
4002 const struct mbus_dram_window *cs = dram->cs + i;
4004 writel(((cs->size - 1) & 0xffff0000) |
4005 (cs->mbus_attr << 8) |
4006 (dram->mbus_dram_target_id << 4) | 1,
4007 hpriv->base + WINDOW_CTRL(i));
4008 writel(cs->base, hpriv->base + WINDOW_BASE(i));
4013 * mv_platform_probe - handle a positive probe of an soc Marvell
4015 * @pdev: platform device found
4018 * Inherited from caller.
4020 static int mv_platform_probe(struct platform_device *pdev)
4022 const struct mv_sata_platform_data *mv_platform_data;
4023 const struct mbus_dram_target_info *dram;
4024 const struct ata_port_info *ppi[] =
4025 { &mv_port_info[chip_soc], NULL };
4026 struct ata_host *host;
4027 struct mv_host_priv *hpriv;
4028 struct resource *res;
4031 #if defined(CONFIG_HAVE_CLK)
4035 ata_print_version_once(&pdev->dev, DRV_VERSION);
4038 * Simple resource validation ..
4040 if (unlikely(pdev->num_resources != 2)) {
4041 dev_err(&pdev->dev, "invalid number of resources\n");
4046 * Get the register base first
4048 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4053 mv_platform_data = pdev->dev.platform_data;
4054 n_ports = mv_platform_data->n_ports;
4056 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4057 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4059 if (!host || !hpriv)
4061 #if defined(CONFIG_HAVE_CLK)
4062 hpriv->port_clks = devm_kzalloc(&pdev->dev,
4063 sizeof(struct clk *) * n_ports,
4065 if (!hpriv->port_clks)
4068 host->private_data = hpriv;
4069 hpriv->n_ports = n_ports;
4070 hpriv->board_idx = chip_soc;
4073 hpriv->base = devm_ioremap(&pdev->dev, res->start,
4074 resource_size(res));
4075 hpriv->base -= SATAHC0_REG_BASE;
4077 #if defined(CONFIG_HAVE_CLK)
4078 hpriv->clk = clk_get(&pdev->dev, NULL);
4079 if (IS_ERR(hpriv->clk))
4080 dev_notice(&pdev->dev, "cannot get optional clkdev\n");
4082 clk_prepare_enable(hpriv->clk);
4084 for (port = 0; port < n_ports; port++) {
4085 char port_number[16];
4086 sprintf(port_number, "%d", port);
4087 hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);
4088 if (!IS_ERR(hpriv->port_clks[port]))
4089 clk_prepare_enable(hpriv->port_clks[port]);
4094 * (Re-)program MBUS remapping windows if we are asked to.
4096 dram = mv_mbus_dram_info();
4098 mv_conf_mbus_windows(hpriv, dram);
4100 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4104 /* initialize adapter */
4105 rc = mv_init_host(host);
4109 dev_info(&pdev->dev, "slots %u ports %d\n",
4110 (unsigned)MV_MAX_Q_DEPTH, host->n_ports);
4112 rc = ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
4113 IRQF_SHARED, &mv6_sht);
4118 #if defined(CONFIG_HAVE_CLK)
4119 if (!IS_ERR(hpriv->clk)) {
4120 clk_disable_unprepare(hpriv->clk);
4121 clk_put(hpriv->clk);
4123 for (port = 0; port < n_ports; port++) {
4124 if (!IS_ERR(hpriv->port_clks[port])) {
4125 clk_disable_unprepare(hpriv->port_clks[port]);
4126 clk_put(hpriv->port_clks[port]);
4136 * mv_platform_remove - unplug a platform interface
4137 * @pdev: platform device
4139 * A platform bus SATA device has been unplugged. Perform the needed
4140 * cleanup. Also called on module unload for any active devices.
4142 static int __devexit mv_platform_remove(struct platform_device *pdev)
4144 struct ata_host *host = platform_get_drvdata(pdev);
4145 #if defined(CONFIG_HAVE_CLK)
4146 struct mv_host_priv *hpriv = host->private_data;
4149 ata_host_detach(host);
4151 #if defined(CONFIG_HAVE_CLK)
4152 if (!IS_ERR(hpriv->clk)) {
4153 clk_disable_unprepare(hpriv->clk);
4154 clk_put(hpriv->clk);
4156 for (port = 0; port < host->n_ports; port++) {
4157 if (!IS_ERR(hpriv->port_clks[port])) {
4158 clk_disable_unprepare(hpriv->port_clks[port]);
4159 clk_put(hpriv->port_clks[port]);
4167 static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state)
4169 struct ata_host *host = platform_get_drvdata(pdev);
4171 return ata_host_suspend(host, state);
4176 static int mv_platform_resume(struct platform_device *pdev)
4178 struct ata_host *host = platform_get_drvdata(pdev);
4179 const struct mbus_dram_target_info *dram;
4183 struct mv_host_priv *hpriv = host->private_data;
4186 * (Re-)program MBUS remapping windows if we are asked to.
4188 dram = mv_mbus_dram_info();
4190 mv_conf_mbus_windows(hpriv, dram);
4192 /* initialize adapter */
4193 ret = mv_init_host(host);
4195 printk(KERN_ERR DRV_NAME ": Error during HW init\n");
4198 ata_host_resume(host);
4204 #define mv_platform_suspend NULL
4205 #define mv_platform_resume NULL
4208 static struct platform_driver mv_platform_driver = {
4209 .probe = mv_platform_probe,
4210 .remove = __devexit_p(mv_platform_remove),
4211 .suspend = mv_platform_suspend,
4212 .resume = mv_platform_resume,
4215 .owner = THIS_MODULE,
4221 static int mv_pci_init_one(struct pci_dev *pdev,
4222 const struct pci_device_id *ent);
4224 static int mv_pci_device_resume(struct pci_dev *pdev);
4228 static struct pci_driver mv_pci_driver = {
4230 .id_table = mv_pci_tbl,
4231 .probe = mv_pci_init_one,
4232 .remove = ata_pci_remove_one,
4234 .suspend = ata_pci_device_suspend,
4235 .resume = mv_pci_device_resume,
4240 /* move to PCI layer or libata core? */
4241 static int pci_go_64(struct pci_dev *pdev)
4245 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4246 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4248 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4251 "64-bit DMA enable failed\n");
4256 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4258 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
4261 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4264 "32-bit consistent DMA enable failed\n");
4273 * mv_print_info - Dump key info to kernel log for perusal.
4274 * @host: ATA host to print info about
4276 * FIXME: complete this.
4279 * Inherited from caller.
4281 static void mv_print_info(struct ata_host *host)
4283 struct pci_dev *pdev = to_pci_dev(host->dev);
4284 struct mv_host_priv *hpriv = host->private_data;
4286 const char *scc_s, *gen;
4288 /* Use this to determine the HW stepping of the chip so we know
4289 * what errata to workaround
4291 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
4294 else if (scc == 0x01)
4299 if (IS_GEN_I(hpriv))
4301 else if (IS_GEN_II(hpriv))
4303 else if (IS_GEN_IIE(hpriv))
4308 dev_info(&pdev->dev, "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
4309 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
4310 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
4314 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
4315 * @pdev: PCI device found
4316 * @ent: PCI device ID entry for the matched host
4319 * Inherited from caller.
4321 static int mv_pci_init_one(struct pci_dev *pdev,
4322 const struct pci_device_id *ent)
4324 unsigned int board_idx = (unsigned int)ent->driver_data;
4325 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4326 struct ata_host *host;
4327 struct mv_host_priv *hpriv;
4328 int n_ports, port, rc;
4330 ata_print_version_once(&pdev->dev, DRV_VERSION);
4333 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4335 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4336 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4337 if (!host || !hpriv)
4339 host->private_data = hpriv;
4340 hpriv->n_ports = n_ports;
4341 hpriv->board_idx = board_idx;
4343 /* acquire resources */
4344 rc = pcim_enable_device(pdev);
4348 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4350 pcim_pin_device(pdev);
4353 host->iomap = pcim_iomap_table(pdev);
4354 hpriv->base = host->iomap[MV_PRIMARY_BAR];
4356 rc = pci_go_64(pdev);
4360 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4364 for (port = 0; port < host->n_ports; port++) {
4365 struct ata_port *ap = host->ports[port];
4366 void __iomem *port_mmio = mv_port_base(hpriv->base, port);
4367 unsigned int offset = port_mmio - hpriv->base;
4369 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
4370 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
4373 /* initialize adapter */
4374 rc = mv_init_host(host);
4378 /* Enable message-switched interrupts, if requested */
4379 if (msi && pci_enable_msi(pdev) == 0)
4380 hpriv->hp_flags |= MV_HP_FLAG_MSI;
4382 mv_dump_pci_cfg(pdev, 0x68);
4383 mv_print_info(host);
4385 pci_set_master(pdev);
4386 pci_try_set_mwi(pdev);
4387 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
4388 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
4392 static int mv_pci_device_resume(struct pci_dev *pdev)
4394 struct ata_host *host = pci_get_drvdata(pdev);
4397 rc = ata_pci_device_do_resume(pdev);
4401 /* initialize adapter */
4402 rc = mv_init_host(host);
4406 ata_host_resume(host);
4413 static int mv_platform_probe(struct platform_device *pdev);
4414 static int __devexit mv_platform_remove(struct platform_device *pdev);
4416 static int __init mv_init(void)
4420 rc = pci_register_driver(&mv_pci_driver);
4424 rc = platform_driver_register(&mv_platform_driver);
4428 pci_unregister_driver(&mv_pci_driver);
4433 static void __exit mv_exit(void)
4436 pci_unregister_driver(&mv_pci_driver);
4438 platform_driver_unregister(&mv_platform_driver);
4441 MODULE_AUTHOR("Brett Russ");
4442 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4443 MODULE_LICENSE("GPL");
4444 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4445 MODULE_VERSION(DRV_VERSION);
4446 MODULE_ALIAS("platform:" DRV_NAME);
4448 module_init(mv_init);
4449 module_exit(mv_exit);