2 * sata_mv.c - Marvell SATA support
4 * Copyright 2008: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 * --> Errata workaround for NCQ device errors.
30 * --> More errata workarounds for PCI-X.
32 * --> Complete a full errata audit for all chipsets to identify others.
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
38 * --> Develop a low-power-consumption strategy, and implement it.
40 * --> [Experiment, low priority] Investigate interrupt coalescing.
41 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
42 * the overhead reduced by interrupt mitigation is quite often not
43 * worth the latency cost.
45 * --> [Experiment, Marvell value added] Is it possible to use target
46 * mode to cross-connect two Linux boxes with Marvell cards? If so,
47 * creating LibATA target mode support would be very interesting.
49 * Target mode, for those without docs, is the ability to directly
50 * connect two SATA ports.
53 #include <linux/kernel.h>
54 #include <linux/module.h>
55 #include <linux/pci.h>
56 #include <linux/init.h>
57 #include <linux/blkdev.h>
58 #include <linux/delay.h>
59 #include <linux/interrupt.h>
60 #include <linux/dmapool.h>
61 #include <linux/dma-mapping.h>
62 #include <linux/device.h>
63 #include <linux/platform_device.h>
64 #include <linux/ata_platform.h>
65 #include <linux/mbus.h>
66 #include <linux/bitops.h>
67 #include <scsi/scsi_host.h>
68 #include <scsi/scsi_cmnd.h>
69 #include <scsi/scsi_device.h>
70 #include <linux/libata.h>
72 #define DRV_NAME "sata_mv"
73 #define DRV_VERSION "1.24"
76 /* BAR's are enumerated in terms of pci_resource_start() terms */
77 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
78 MV_IO_BAR = 2, /* offset 0x18: IO space */
79 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
81 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
82 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
85 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
86 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
87 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
88 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
89 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
90 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
92 MV_SATAHC0_REG_BASE = 0x20000,
93 MV_FLASH_CTL_OFS = 0x1046c,
94 MV_GPIO_PORT_CTL_OFS = 0x104f0,
95 MV_RESET_CFG_OFS = 0x180d8,
97 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
98 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
99 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
100 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
103 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
105 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
106 * CRPB needs alignment on a 256B boundary. Size == 256B
107 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
109 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
110 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
112 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
114 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
115 MV_PORT_HC_SHIFT = 2,
116 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
117 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
118 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
121 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
122 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
124 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
125 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
126 ATA_FLAG_PIO_POLLING,
128 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
130 MV_GENIIE_FLAGS = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
131 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
132 ATA_FLAG_NCQ | ATA_FLAG_AN,
134 CRQB_FLAG_READ = (1 << 0),
136 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
137 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
138 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
139 CRQB_CMD_ADDR_SHIFT = 8,
140 CRQB_CMD_CS = (0x2 << 11),
141 CRQB_CMD_LAST = (1 << 15),
143 CRPB_FLAG_STATUS_SHIFT = 8,
144 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
145 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
147 EPRD_FLAG_END_OF_TBL = (1 << 31),
149 /* PCI interface registers */
151 PCI_COMMAND_OFS = 0xc00,
152 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
154 PCI_MAIN_CMD_STS_OFS = 0xd30,
155 STOP_PCI_MASTER = (1 << 2),
156 PCI_MASTER_EMPTY = (1 << 3),
157 GLOB_SFT_RST = (1 << 4),
159 MV_PCI_MODE_OFS = 0xd00,
160 MV_PCI_MODE_MASK = 0x30,
162 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
163 MV_PCI_DISC_TIMER = 0xd04,
164 MV_PCI_MSI_TRIGGER = 0xc38,
165 MV_PCI_SERR_MASK = 0xc28,
166 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
167 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
168 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
169 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
170 MV_PCI_ERR_COMMAND = 0x1d50,
172 PCI_IRQ_CAUSE_OFS = 0x1d58,
173 PCI_IRQ_MASK_OFS = 0x1d5c,
174 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
176 PCIE_IRQ_CAUSE_OFS = 0x1900,
177 PCIE_IRQ_MASK_OFS = 0x1910,
178 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
180 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
181 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
182 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
183 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
184 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
185 ERR_IRQ = (1 << 0), /* shift by port # */
186 DONE_IRQ = (1 << 1), /* shift by port # */
187 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
188 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
190 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
191 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
192 PORTS_0_3_COAL_DONE = (1 << 8),
193 PORTS_4_7_COAL_DONE = (1 << 17),
194 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
195 GPIO_INT = (1 << 22),
196 SELF_INT = (1 << 23),
197 TWSI_INT = (1 << 24),
198 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
199 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
200 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
202 /* SATAHC registers */
205 HC_IRQ_CAUSE_OFS = 0x14,
206 DMA_IRQ = (1 << 0), /* shift by port # */
207 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
208 DEV_IRQ = (1 << 8), /* shift by port # */
210 /* Shadow block registers */
212 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
215 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
216 SATA_ACTIVE_OFS = 0x350,
217 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
218 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
221 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
225 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
226 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
227 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
228 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
231 SATA_IFCTL_OFS = 0x344,
232 SATA_TESTCTL_OFS = 0x348,
233 SATA_IFSTAT_OFS = 0x34c,
234 VENDOR_UNIQUE_FIS_OFS = 0x35c,
237 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
238 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
241 MV5_LTMODE_OFS = 0x30,
242 MV5_PHY_CTL_OFS = 0x0C,
243 SATA_INTERFACE_CFG_OFS = 0x050,
245 MV_M2_PREAMP_MASK = 0x7e0,
249 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
250 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
251 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
252 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
253 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
254 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
255 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
257 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
258 EDMA_ERR_IRQ_MASK_OFS = 0xc,
259 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
260 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
261 EDMA_ERR_DEV = (1 << 2), /* device error */
262 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
263 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
264 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
265 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
266 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
267 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
268 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
269 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
270 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
271 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
272 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
274 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
275 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
276 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
277 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
278 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
280 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
282 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
283 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
284 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
285 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
286 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
287 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
289 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
291 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
292 EDMA_ERR_OVERRUN_5 = (1 << 5),
293 EDMA_ERR_UNDERRUN_5 = (1 << 6),
295 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
296 EDMA_ERR_LNK_CTRL_RX_1 |
297 EDMA_ERR_LNK_CTRL_RX_3 |
298 EDMA_ERR_LNK_CTRL_TX,
300 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
310 EDMA_ERR_LNK_CTRL_RX_2 |
311 EDMA_ERR_LNK_DATA_RX |
312 EDMA_ERR_LNK_DATA_TX |
313 EDMA_ERR_TRANS_PROTO,
315 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
320 EDMA_ERR_UNDERRUN_5 |
321 EDMA_ERR_SELF_DIS_5 |
327 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
328 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
330 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
331 EDMA_REQ_Q_PTR_SHIFT = 5,
333 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
334 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
335 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
336 EDMA_RSP_Q_PTR_SHIFT = 3,
338 EDMA_CMD_OFS = 0x28, /* EDMA command register */
339 EDMA_EN = (1 << 0), /* enable EDMA */
340 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
341 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
343 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
344 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
345 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
347 EDMA_IORDY_TMOUT_OFS = 0x34,
348 EDMA_ARB_CFG_OFS = 0x38,
350 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
352 /* Host private flags (hp_flags) */
353 MV_HP_FLAG_MSI = (1 << 0),
354 MV_HP_ERRATA_50XXB0 = (1 << 1),
355 MV_HP_ERRATA_50XXB2 = (1 << 2),
356 MV_HP_ERRATA_60X1B2 = (1 << 3),
357 MV_HP_ERRATA_60X1C0 = (1 << 4),
358 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
359 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
360 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
361 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
362 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
363 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
365 /* Port private flags (pp_flags) */
366 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
367 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
368 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
369 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
372 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
373 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
374 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
375 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
376 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
378 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
379 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
382 /* DMA boundary 0xffff is required by the s/g splitting
383 * we need on /length/ in mv_fill-sg().
385 MV_DMA_BOUNDARY = 0xffffU,
387 /* mask of register bits containing lower 32 bits
388 * of EDMA request queue DMA address
390 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
392 /* ditto, for response queue */
393 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
407 /* Command ReQuest Block: 32B */
423 /* Command ResPonse Block: 8B */
430 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
438 struct mv_port_priv {
439 struct mv_crqb *crqb;
441 struct mv_crpb *crpb;
443 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
444 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
446 unsigned int req_idx;
447 unsigned int resp_idx;
450 unsigned int delayed_eh_pmp_map;
453 struct mv_port_signal {
458 struct mv_host_priv {
461 struct mv_port_signal signal[8];
462 const struct mv_hw_ops *ops;
465 void __iomem *main_irq_cause_addr;
466 void __iomem *main_irq_mask_addr;
471 * These consistent DMA memory pools give us guaranteed
472 * alignment for hardware-accessed data structures,
473 * and less memory waste in accomplishing the alignment.
475 struct dma_pool *crqb_pool;
476 struct dma_pool *crpb_pool;
477 struct dma_pool *sg_tbl_pool;
481 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
483 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
484 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
486 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
488 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
489 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
492 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
493 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
494 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
495 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
496 static int mv_port_start(struct ata_port *ap);
497 static void mv_port_stop(struct ata_port *ap);
498 static int mv_qc_defer(struct ata_queued_cmd *qc);
499 static void mv_qc_prep(struct ata_queued_cmd *qc);
500 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
501 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
502 static int mv_hardreset(struct ata_link *link, unsigned int *class,
503 unsigned long deadline);
504 static void mv_eh_freeze(struct ata_port *ap);
505 static void mv_eh_thaw(struct ata_port *ap);
506 static void mv6_dev_config(struct ata_device *dev);
508 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
510 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
511 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
513 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
515 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
516 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
518 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
520 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
521 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
523 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
525 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
526 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
528 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
530 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
531 void __iomem *mmio, unsigned int n_hc);
532 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
534 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
535 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
536 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
537 unsigned int port_no);
538 static int mv_stop_edma(struct ata_port *ap);
539 static int mv_stop_edma_engine(void __iomem *port_mmio);
540 static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
542 static void mv_pmp_select(struct ata_port *ap, int pmp);
543 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
544 unsigned long deadline);
545 static int mv_softreset(struct ata_link *link, unsigned int *class,
546 unsigned long deadline);
547 static void mv_pmp_error_handler(struct ata_port *ap);
548 static void mv_process_crpb_entries(struct ata_port *ap,
549 struct mv_port_priv *pp);
551 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
552 * because we have to allow room for worst case splitting of
553 * PRDs for 64K boundaries in mv_fill_sg().
555 static struct scsi_host_template mv5_sht = {
556 ATA_BASE_SHT(DRV_NAME),
557 .sg_tablesize = MV_MAX_SG_CT / 2,
558 .dma_boundary = MV_DMA_BOUNDARY,
561 static struct scsi_host_template mv6_sht = {
562 ATA_NCQ_SHT(DRV_NAME),
563 .can_queue = MV_MAX_Q_DEPTH - 1,
564 .sg_tablesize = MV_MAX_SG_CT / 2,
565 .dma_boundary = MV_DMA_BOUNDARY,
568 static struct ata_port_operations mv5_ops = {
569 .inherits = &ata_sff_port_ops,
571 .qc_defer = mv_qc_defer,
572 .qc_prep = mv_qc_prep,
573 .qc_issue = mv_qc_issue,
575 .freeze = mv_eh_freeze,
577 .hardreset = mv_hardreset,
578 .error_handler = ata_std_error_handler, /* avoid SFF EH */
579 .post_internal_cmd = ATA_OP_NULL,
581 .scr_read = mv5_scr_read,
582 .scr_write = mv5_scr_write,
584 .port_start = mv_port_start,
585 .port_stop = mv_port_stop,
588 static struct ata_port_operations mv6_ops = {
589 .inherits = &mv5_ops,
590 .dev_config = mv6_dev_config,
591 .scr_read = mv_scr_read,
592 .scr_write = mv_scr_write,
594 .pmp_hardreset = mv_pmp_hardreset,
595 .pmp_softreset = mv_softreset,
596 .softreset = mv_softreset,
597 .error_handler = mv_pmp_error_handler,
600 static struct ata_port_operations mv_iie_ops = {
601 .inherits = &mv6_ops,
602 .dev_config = ATA_OP_NULL,
603 .qc_prep = mv_qc_prep_iie,
606 static const struct ata_port_info mv_port_info[] = {
608 .flags = MV_COMMON_FLAGS,
609 .pio_mask = 0x1f, /* pio0-4 */
610 .udma_mask = ATA_UDMA6,
611 .port_ops = &mv5_ops,
614 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
615 .pio_mask = 0x1f, /* pio0-4 */
616 .udma_mask = ATA_UDMA6,
617 .port_ops = &mv5_ops,
620 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
621 .pio_mask = 0x1f, /* pio0-4 */
622 .udma_mask = ATA_UDMA6,
623 .port_ops = &mv5_ops,
626 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
627 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
629 .pio_mask = 0x1f, /* pio0-4 */
630 .udma_mask = ATA_UDMA6,
631 .port_ops = &mv6_ops,
634 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
635 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
636 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
637 .pio_mask = 0x1f, /* pio0-4 */
638 .udma_mask = ATA_UDMA6,
639 .port_ops = &mv6_ops,
642 .flags = MV_GENIIE_FLAGS,
643 .pio_mask = 0x1f, /* pio0-4 */
644 .udma_mask = ATA_UDMA6,
645 .port_ops = &mv_iie_ops,
648 .flags = MV_GENIIE_FLAGS,
649 .pio_mask = 0x1f, /* pio0-4 */
650 .udma_mask = ATA_UDMA6,
651 .port_ops = &mv_iie_ops,
654 .flags = MV_GENIIE_FLAGS,
655 .pio_mask = 0x1f, /* pio0-4 */
656 .udma_mask = ATA_UDMA6,
657 .port_ops = &mv_iie_ops,
661 static const struct pci_device_id mv_pci_tbl[] = {
662 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
663 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
664 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
665 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
666 /* RocketRAID 1720/174x have different identifiers */
667 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
668 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
669 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
671 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
672 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
673 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
674 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
675 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
677 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
680 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
682 /* Marvell 7042 support */
683 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
685 /* Highpoint RocketRAID PCIe series */
686 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
687 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
689 { } /* terminate list */
692 static const struct mv_hw_ops mv5xxx_ops = {
693 .phy_errata = mv5_phy_errata,
694 .enable_leds = mv5_enable_leds,
695 .read_preamp = mv5_read_preamp,
696 .reset_hc = mv5_reset_hc,
697 .reset_flash = mv5_reset_flash,
698 .reset_bus = mv5_reset_bus,
701 static const struct mv_hw_ops mv6xxx_ops = {
702 .phy_errata = mv6_phy_errata,
703 .enable_leds = mv6_enable_leds,
704 .read_preamp = mv6_read_preamp,
705 .reset_hc = mv6_reset_hc,
706 .reset_flash = mv6_reset_flash,
707 .reset_bus = mv_reset_pci_bus,
710 static const struct mv_hw_ops mv_soc_ops = {
711 .phy_errata = mv6_phy_errata,
712 .enable_leds = mv_soc_enable_leds,
713 .read_preamp = mv_soc_read_preamp,
714 .reset_hc = mv_soc_reset_hc,
715 .reset_flash = mv_soc_reset_flash,
716 .reset_bus = mv_soc_reset_bus,
723 static inline void writelfl(unsigned long data, void __iomem *addr)
726 (void) readl(addr); /* flush to avoid PCI posted write */
729 static inline unsigned int mv_hc_from_port(unsigned int port)
731 return port >> MV_PORT_HC_SHIFT;
734 static inline unsigned int mv_hardport_from_port(unsigned int port)
736 return port & MV_PORT_MASK;
740 * Consolidate some rather tricky bit shift calculations.
741 * This is hot-path stuff, so not a function.
742 * Simple code, with two return values, so macro rather than inline.
744 * port is the sole input, in range 0..7.
745 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
746 * hardport is the other output, in range 0..3.
748 * Note that port and hardport may be the same variable in some cases.
750 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
752 shift = mv_hc_from_port(port) * HC_SHIFT; \
753 hardport = mv_hardport_from_port(port); \
754 shift += hardport * 2; \
757 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
759 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
762 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
765 return mv_hc_base(base, mv_hc_from_port(port));
768 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
770 return mv_hc_base_from_port(base, port) +
771 MV_SATAHC_ARBTR_REG_SZ +
772 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
775 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
777 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
778 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
780 return hc_mmio + ofs;
783 static inline void __iomem *mv_host_base(struct ata_host *host)
785 struct mv_host_priv *hpriv = host->private_data;
789 static inline void __iomem *mv_ap_base(struct ata_port *ap)
791 return mv_port_base(mv_host_base(ap->host), ap->port_no);
794 static inline int mv_get_hc_count(unsigned long port_flags)
796 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
799 static void mv_set_edma_ptrs(void __iomem *port_mmio,
800 struct mv_host_priv *hpriv,
801 struct mv_port_priv *pp)
806 * initialize request queue
808 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
809 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
811 WARN_ON(pp->crqb_dma & 0x3ff);
812 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
813 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
814 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
815 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
818 * initialize response queue
820 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
821 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
823 WARN_ON(pp->crpb_dma & 0xff);
824 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
825 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
826 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
827 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
830 static void mv_set_main_irq_mask(struct ata_host *host,
831 u32 disable_bits, u32 enable_bits)
833 struct mv_host_priv *hpriv = host->private_data;
834 u32 old_mask, new_mask;
836 old_mask = hpriv->main_irq_mask;
837 new_mask = (old_mask & ~disable_bits) | enable_bits;
838 if (new_mask != old_mask) {
839 hpriv->main_irq_mask = new_mask;
840 writelfl(new_mask, hpriv->main_irq_mask_addr);
844 static void mv_enable_port_irqs(struct ata_port *ap,
845 unsigned int port_bits)
847 unsigned int shift, hardport, port = ap->port_no;
848 u32 disable_bits, enable_bits;
850 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
852 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
853 enable_bits = port_bits << shift;
854 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
858 * mv_start_dma - Enable eDMA engine
859 * @base: port base address
860 * @pp: port private data
862 * Verify the local cache of the eDMA state is accurate with a
866 * Inherited from caller.
868 static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
869 struct mv_port_priv *pp, u8 protocol)
871 int want_ncq = (protocol == ATA_PROT_NCQ);
873 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
874 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
875 if (want_ncq != using_ncq)
878 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
879 struct mv_host_priv *hpriv = ap->host->private_data;
880 int hardport = mv_hardport_from_port(ap->port_no);
881 void __iomem *hc_mmio = mv_hc_base_from_port(
882 mv_host_base(ap->host), ap->port_no);
885 /* clear EDMA event indicators, if any */
886 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
888 /* clear pending irq events */
889 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
890 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
892 mv_edma_cfg(ap, want_ncq);
894 /* clear FIS IRQ Cause */
895 if (IS_GEN_IIE(hpriv))
896 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
898 mv_set_edma_ptrs(port_mmio, hpriv, pp);
899 mv_enable_port_irqs(ap, DONE_IRQ|ERR_IRQ);
901 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
902 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
906 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
908 void __iomem *port_mmio = mv_ap_base(ap);
909 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
910 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
914 * Wait for the EDMA engine to finish transactions in progress.
915 * No idea what a good "timeout" value might be, but measurements
916 * indicate that it often requires hundreds of microseconds
917 * with two drives in-use. So we use the 15msec value above
918 * as a rough guess at what even more drives might require.
920 for (i = 0; i < timeout; ++i) {
921 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
922 if ((edma_stat & empty_idle) == empty_idle)
926 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
930 * mv_stop_edma_engine - Disable eDMA engine
931 * @port_mmio: io base address
934 * Inherited from caller.
936 static int mv_stop_edma_engine(void __iomem *port_mmio)
940 /* Disable eDMA. The disable bit auto clears. */
941 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
943 /* Wait for the chip to confirm eDMA is off. */
944 for (i = 10000; i > 0; i--) {
945 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
946 if (!(reg & EDMA_EN))
953 static int mv_stop_edma(struct ata_port *ap)
955 void __iomem *port_mmio = mv_ap_base(ap);
956 struct mv_port_priv *pp = ap->private_data;
958 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
960 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
961 mv_wait_for_edma_empty_idle(ap);
962 if (mv_stop_edma_engine(port_mmio)) {
963 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
970 static void mv_dump_mem(void __iomem *start, unsigned bytes)
973 for (b = 0; b < bytes; ) {
974 DPRINTK("%p: ", start + b);
975 for (w = 0; b < bytes && w < 4; w++) {
976 printk("%08x ", readl(start + b));
984 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
989 for (b = 0; b < bytes; ) {
990 DPRINTK("%02x: ", b);
991 for (w = 0; b < bytes && w < 4; w++) {
992 (void) pci_read_config_dword(pdev, b, &dw);
1000 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1001 struct pci_dev *pdev)
1004 void __iomem *hc_base = mv_hc_base(mmio_base,
1005 port >> MV_PORT_HC_SHIFT);
1006 void __iomem *port_base;
1007 int start_port, num_ports, p, start_hc, num_hcs, hc;
1010 start_hc = start_port = 0;
1011 num_ports = 8; /* shld be benign for 4 port devs */
1014 start_hc = port >> MV_PORT_HC_SHIFT;
1016 num_ports = num_hcs = 1;
1018 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1019 num_ports > 1 ? num_ports - 1 : start_port);
1022 DPRINTK("PCI config space regs:\n");
1023 mv_dump_pci_cfg(pdev, 0x68);
1025 DPRINTK("PCI regs:\n");
1026 mv_dump_mem(mmio_base+0xc00, 0x3c);
1027 mv_dump_mem(mmio_base+0xd00, 0x34);
1028 mv_dump_mem(mmio_base+0xf00, 0x4);
1029 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1030 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1031 hc_base = mv_hc_base(mmio_base, hc);
1032 DPRINTK("HC regs (HC %i):\n", hc);
1033 mv_dump_mem(hc_base, 0x1c);
1035 for (p = start_port; p < start_port + num_ports; p++) {
1036 port_base = mv_port_base(mmio_base, p);
1037 DPRINTK("EDMA regs (port %i):\n", p);
1038 mv_dump_mem(port_base, 0x54);
1039 DPRINTK("SATA regs (port %i):\n", p);
1040 mv_dump_mem(port_base+0x300, 0x60);
1045 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1049 switch (sc_reg_in) {
1053 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1056 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1065 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
1067 unsigned int ofs = mv_scr_offset(sc_reg_in);
1069 if (ofs != 0xffffffffU) {
1070 *val = readl(mv_ap_base(link->ap) + ofs);
1076 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
1078 unsigned int ofs = mv_scr_offset(sc_reg_in);
1080 if (ofs != 0xffffffffU) {
1081 writelfl(val, mv_ap_base(link->ap) + ofs);
1087 static void mv6_dev_config(struct ata_device *adev)
1090 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1092 * Gen-II does not support NCQ over a port multiplier
1093 * (no FIS-based switching).
1095 if (adev->flags & ATA_DFLAG_NCQ) {
1096 if (sata_pmp_attached(adev->link->ap)) {
1097 adev->flags &= ~ATA_DFLAG_NCQ;
1098 ata_dev_printk(adev, KERN_INFO,
1099 "NCQ disabled for command-based switching\n");
1104 static int mv_qc_defer(struct ata_queued_cmd *qc)
1106 struct ata_link *link = qc->dev->link;
1107 struct ata_port *ap = link->ap;
1108 struct mv_port_priv *pp = ap->private_data;
1111 * Don't allow new commands if we're in a delayed EH state
1112 * for NCQ and/or FIS-based switching.
1114 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1115 return ATA_DEFER_PORT;
1117 * If the port is completely idle, then allow the new qc.
1119 if (ap->nr_active_links == 0)
1123 * The port is operating in host queuing mode (EDMA) with NCQ
1124 * enabled, allow multiple NCQ commands. EDMA also allows
1125 * queueing multiple DMA commands but libata core currently
1128 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1129 (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol))
1132 return ATA_DEFER_PORT;
1135 static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
1137 u32 new_fiscfg, old_fiscfg;
1138 u32 new_ltmode, old_ltmode;
1139 u32 new_haltcond, old_haltcond;
1141 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1142 old_ltmode = readl(port_mmio + LTMODE_OFS);
1143 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
1145 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1146 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1147 new_haltcond = old_haltcond | EDMA_ERR_DEV;
1150 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1151 new_ltmode = old_ltmode | LTMODE_BIT8;
1153 new_haltcond &= ~EDMA_ERR_DEV;
1155 new_fiscfg |= FISCFG_WAIT_DEV_ERR;
1158 if (new_fiscfg != old_fiscfg)
1159 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
1160 if (new_ltmode != old_ltmode)
1161 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
1162 if (new_haltcond != old_haltcond)
1163 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
1166 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1168 struct mv_host_priv *hpriv = ap->host->private_data;
1171 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1172 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1174 new = old | (1 << 22);
1176 new = old & ~(1 << 22);
1178 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1181 static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
1184 struct mv_port_priv *pp = ap->private_data;
1185 struct mv_host_priv *hpriv = ap->host->private_data;
1186 void __iomem *port_mmio = mv_ap_base(ap);
1188 /* set up non-NCQ EDMA configuration */
1189 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1190 pp->pp_flags &= ~MV_PP_FLAG_FBS_EN;
1192 if (IS_GEN_I(hpriv))
1193 cfg |= (1 << 8); /* enab config burst size mask */
1195 else if (IS_GEN_II(hpriv)) {
1196 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1197 mv_60x1_errata_sata25(ap, want_ncq);
1199 } else if (IS_GEN_IIE(hpriv)) {
1200 int want_fbs = sata_pmp_attached(ap);
1202 * Possible future enhancement:
1204 * The chip can use FBS with non-NCQ, if we allow it,
1205 * But first we need to have the error handling in place
1206 * for this mode (datasheet section 7.3.15.4.2.3).
1207 * So disallow non-NCQ FBS for now.
1209 want_fbs &= want_ncq;
1211 mv_config_fbs(port_mmio, want_ncq, want_fbs);
1214 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1215 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1218 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1219 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1221 cfg |= (1 << 18); /* enab early completion */
1222 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1223 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1227 cfg |= EDMA_CFG_NCQ;
1228 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1230 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1232 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1235 static void mv_port_free_dma_mem(struct ata_port *ap)
1237 struct mv_host_priv *hpriv = ap->host->private_data;
1238 struct mv_port_priv *pp = ap->private_data;
1242 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1246 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1250 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1251 * For later hardware, we have one unique sg_tbl per NCQ tag.
1253 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1254 if (pp->sg_tbl[tag]) {
1255 if (tag == 0 || !IS_GEN_I(hpriv))
1256 dma_pool_free(hpriv->sg_tbl_pool,
1258 pp->sg_tbl_dma[tag]);
1259 pp->sg_tbl[tag] = NULL;
1265 * mv_port_start - Port specific init/start routine.
1266 * @ap: ATA channel to manipulate
1268 * Allocate and point to DMA memory, init port private memory,
1272 * Inherited from caller.
1274 static int mv_port_start(struct ata_port *ap)
1276 struct device *dev = ap->host->dev;
1277 struct mv_host_priv *hpriv = ap->host->private_data;
1278 struct mv_port_priv *pp;
1281 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1284 ap->private_data = pp;
1286 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1289 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1291 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1293 goto out_port_free_dma_mem;
1294 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1296 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1297 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1298 ap->flags |= ATA_FLAG_AN;
1300 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1301 * For later hardware, we need one unique sg_tbl per NCQ tag.
1303 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1304 if (tag == 0 || !IS_GEN_I(hpriv)) {
1305 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1306 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1307 if (!pp->sg_tbl[tag])
1308 goto out_port_free_dma_mem;
1310 pp->sg_tbl[tag] = pp->sg_tbl[0];
1311 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1316 out_port_free_dma_mem:
1317 mv_port_free_dma_mem(ap);
1322 * mv_port_stop - Port specific cleanup/stop routine.
1323 * @ap: ATA channel to manipulate
1325 * Stop DMA, cleanup port memory.
1328 * This routine uses the host lock to protect the DMA stop.
1330 static void mv_port_stop(struct ata_port *ap)
1333 mv_enable_port_irqs(ap, 0);
1334 mv_port_free_dma_mem(ap);
1338 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1339 * @qc: queued command whose SG list to source from
1341 * Populate the SG list and mark the last entry.
1344 * Inherited from caller.
1346 static void mv_fill_sg(struct ata_queued_cmd *qc)
1348 struct mv_port_priv *pp = qc->ap->private_data;
1349 struct scatterlist *sg;
1350 struct mv_sg *mv_sg, *last_sg = NULL;
1353 mv_sg = pp->sg_tbl[qc->tag];
1354 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1355 dma_addr_t addr = sg_dma_address(sg);
1356 u32 sg_len = sg_dma_len(sg);
1359 u32 offset = addr & 0xffff;
1362 if ((offset + sg_len > 0x10000))
1363 len = 0x10000 - offset;
1365 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1366 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1367 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1377 if (likely(last_sg))
1378 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1381 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1383 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1384 (last ? CRQB_CMD_LAST : 0);
1385 *cmdw = cpu_to_le16(tmp);
1389 * mv_qc_prep - Host specific command preparation.
1390 * @qc: queued command to prepare
1392 * This routine simply redirects to the general purpose routine
1393 * if command is not DMA. Else, it handles prep of the CRQB
1394 * (command request block), does some sanity checking, and calls
1395 * the SG load routine.
1398 * Inherited from caller.
1400 static void mv_qc_prep(struct ata_queued_cmd *qc)
1402 struct ata_port *ap = qc->ap;
1403 struct mv_port_priv *pp = ap->private_data;
1405 struct ata_taskfile *tf;
1409 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1410 (qc->tf.protocol != ATA_PROT_NCQ))
1413 /* Fill in command request block
1415 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1416 flags |= CRQB_FLAG_READ;
1417 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1418 flags |= qc->tag << CRQB_TAG_SHIFT;
1419 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1421 /* get current queue index from software */
1422 in_index = pp->req_idx;
1424 pp->crqb[in_index].sg_addr =
1425 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1426 pp->crqb[in_index].sg_addr_hi =
1427 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1428 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1430 cw = &pp->crqb[in_index].ata_cmd[0];
1433 /* Sadly, the CRQB cannot accomodate all registers--there are
1434 * only 11 bytes...so we must pick and choose required
1435 * registers based on the command. So, we drop feature and
1436 * hob_feature for [RW] DMA commands, but they are needed for
1437 * NCQ. NCQ will drop hob_nsect, which is not needed there
1438 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
1440 switch (tf->command) {
1442 case ATA_CMD_READ_EXT:
1444 case ATA_CMD_WRITE_EXT:
1445 case ATA_CMD_WRITE_FUA_EXT:
1446 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1448 case ATA_CMD_FPDMA_READ:
1449 case ATA_CMD_FPDMA_WRITE:
1450 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1451 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1454 /* The only other commands EDMA supports in non-queued and
1455 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1456 * of which are defined/used by Linux. If we get here, this
1457 * driver needs work.
1459 * FIXME: modify libata to give qc_prep a return value and
1460 * return error here.
1462 BUG_ON(tf->command);
1465 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1466 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1467 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1468 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1469 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1470 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1471 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1472 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1473 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1475 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1481 * mv_qc_prep_iie - Host specific command preparation.
1482 * @qc: queued command to prepare
1484 * This routine simply redirects to the general purpose routine
1485 * if command is not DMA. Else, it handles prep of the CRQB
1486 * (command request block), does some sanity checking, and calls
1487 * the SG load routine.
1490 * Inherited from caller.
1492 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1494 struct ata_port *ap = qc->ap;
1495 struct mv_port_priv *pp = ap->private_data;
1496 struct mv_crqb_iie *crqb;
1497 struct ata_taskfile *tf;
1501 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1502 (qc->tf.protocol != ATA_PROT_NCQ))
1505 /* Fill in Gen IIE command request block */
1506 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1507 flags |= CRQB_FLAG_READ;
1509 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1510 flags |= qc->tag << CRQB_TAG_SHIFT;
1511 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
1512 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1514 /* get current queue index from software */
1515 in_index = pp->req_idx;
1517 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1518 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1519 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1520 crqb->flags = cpu_to_le32(flags);
1523 crqb->ata_cmd[0] = cpu_to_le32(
1524 (tf->command << 16) |
1527 crqb->ata_cmd[1] = cpu_to_le32(
1533 crqb->ata_cmd[2] = cpu_to_le32(
1534 (tf->hob_lbal << 0) |
1535 (tf->hob_lbam << 8) |
1536 (tf->hob_lbah << 16) |
1537 (tf->hob_feature << 24)
1539 crqb->ata_cmd[3] = cpu_to_le32(
1541 (tf->hob_nsect << 8)
1544 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1550 * mv_qc_issue - Initiate a command to the host
1551 * @qc: queued command to start
1553 * This routine simply redirects to the general purpose routine
1554 * if command is not DMA. Else, it sanity checks our local
1555 * caches of the request producer/consumer indices then enables
1556 * DMA and bumps the request producer index.
1559 * Inherited from caller.
1561 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1563 struct ata_port *ap = qc->ap;
1564 void __iomem *port_mmio = mv_ap_base(ap);
1565 struct mv_port_priv *pp = ap->private_data;
1568 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1569 (qc->tf.protocol != ATA_PROT_NCQ)) {
1570 static int limit_warnings = 10;
1572 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
1574 * Someday, we might implement special polling workarounds
1575 * for these, but it all seems rather unnecessary since we
1576 * normally use only DMA for commands which transfer more
1577 * than a single block of data.
1579 * Much of the time, this could just work regardless.
1580 * So for now, just log the incident, and allow the attempt.
1582 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
1584 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
1585 ": attempting PIO w/multiple DRQ: "
1586 "this may fail due to h/w errata\n");
1589 * We're about to send a non-EDMA capable command to the
1590 * port. Turn off EDMA so there won't be problems accessing
1591 * shadow block, etc registers.
1594 mv_enable_port_irqs(ap, ERR_IRQ);
1595 mv_pmp_select(ap, qc->dev->link->pmp);
1596 return ata_sff_qc_issue(qc);
1599 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
1601 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1602 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
1604 /* and write the request in pointer to kick the EDMA to life */
1605 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1606 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1611 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1613 struct mv_port_priv *pp = ap->private_data;
1614 struct ata_queued_cmd *qc;
1616 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1618 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1619 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1624 static void mv_pmp_error_handler(struct ata_port *ap)
1626 unsigned int pmp, pmp_map;
1627 struct mv_port_priv *pp = ap->private_data;
1629 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1631 * Perform NCQ error analysis on failed PMPs
1632 * before we freeze the port entirely.
1634 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1636 pmp_map = pp->delayed_eh_pmp_map;
1637 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1638 for (pmp = 0; pmp_map != 0; pmp++) {
1639 unsigned int this_pmp = (1 << pmp);
1640 if (pmp_map & this_pmp) {
1641 struct ata_link *link = &ap->pmp_link[pmp];
1642 pmp_map &= ~this_pmp;
1643 ata_eh_analyze_ncq_error(link);
1646 ata_port_freeze(ap);
1648 sata_pmp_error_handler(ap);
1651 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
1653 void __iomem *port_mmio = mv_ap_base(ap);
1655 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
1658 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1660 struct ata_eh_info *ehi;
1664 * Initialize EH info for PMPs which saw device errors
1666 ehi = &ap->link.eh_info;
1667 for (pmp = 0; pmp_map != 0; pmp++) {
1668 unsigned int this_pmp = (1 << pmp);
1669 if (pmp_map & this_pmp) {
1670 struct ata_link *link = &ap->pmp_link[pmp];
1672 pmp_map &= ~this_pmp;
1673 ehi = &link->eh_info;
1674 ata_ehi_clear_desc(ehi);
1675 ata_ehi_push_desc(ehi, "dev err");
1676 ehi->err_mask |= AC_ERR_DEV;
1677 ehi->action |= ATA_EH_RESET;
1678 ata_link_abort(link);
1683 static int mv_req_q_empty(struct ata_port *ap)
1685 void __iomem *port_mmio = mv_ap_base(ap);
1686 u32 in_ptr, out_ptr;
1688 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS)
1689 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1690 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1691 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1692 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
1695 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1697 struct mv_port_priv *pp = ap->private_data;
1699 unsigned int old_map, new_map;
1702 * Device error during FBS+NCQ operation:
1704 * Set a port flag to prevent further I/O being enqueued.
1705 * Leave the EDMA running to drain outstanding commands from this port.
1706 * Perform the post-mortem/EH only when all responses are complete.
1707 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
1709 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
1710 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
1711 pp->delayed_eh_pmp_map = 0;
1713 old_map = pp->delayed_eh_pmp_map;
1714 new_map = old_map | mv_get_err_pmp_map(ap);
1716 if (old_map != new_map) {
1717 pp->delayed_eh_pmp_map = new_map;
1718 mv_pmp_eh_prep(ap, new_map & ~old_map);
1720 failed_links = hweight16(new_map);
1722 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
1723 "failed_links=%d nr_active_links=%d\n",
1724 __func__, pp->delayed_eh_pmp_map,
1725 ap->qc_active, failed_links,
1726 ap->nr_active_links);
1728 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
1729 mv_process_crpb_entries(ap, pp);
1732 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
1733 return 1; /* handled */
1735 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
1736 return 1; /* handled */
1739 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
1742 * Possible future enhancement:
1744 * FBS+non-NCQ operation is not yet implemented.
1745 * See related notes in mv_edma_cfg().
1747 * Device error during FBS+non-NCQ operation:
1749 * We need to snapshot the shadow registers for each failed command.
1750 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
1752 return 0; /* not handled */
1755 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
1757 struct mv_port_priv *pp = ap->private_data;
1759 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1760 return 0; /* EDMA was not active: not handled */
1761 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
1762 return 0; /* FBS was not active: not handled */
1764 if (!(edma_err_cause & EDMA_ERR_DEV))
1765 return 0; /* non DEV error: not handled */
1766 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
1767 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
1768 return 0; /* other problems: not handled */
1770 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1772 * EDMA should NOT have self-disabled for this case.
1773 * If it did, then something is wrong elsewhere,
1774 * and we cannot handle it here.
1776 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1777 ata_port_printk(ap, KERN_WARNING,
1778 "%s: err_cause=0x%x pp_flags=0x%x\n",
1779 __func__, edma_err_cause, pp->pp_flags);
1780 return 0; /* not handled */
1782 return mv_handle_fbs_ncq_dev_err(ap);
1785 * EDMA should have self-disabled for this case.
1786 * If it did not, then something is wrong elsewhere,
1787 * and we cannot handle it here.
1789 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
1790 ata_port_printk(ap, KERN_WARNING,
1791 "%s: err_cause=0x%x pp_flags=0x%x\n",
1792 __func__, edma_err_cause, pp->pp_flags);
1793 return 0; /* not handled */
1795 return mv_handle_fbs_non_ncq_dev_err(ap);
1797 return 0; /* not handled */
1800 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
1802 struct ata_eh_info *ehi = &ap->link.eh_info;
1803 char *when = "idle";
1805 ata_ehi_clear_desc(ehi);
1806 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
1808 } else if (edma_was_enabled) {
1809 when = "EDMA enabled";
1811 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1812 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1815 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
1816 ehi->err_mask |= AC_ERR_OTHER;
1817 ehi->action |= ATA_EH_RESET;
1818 ata_port_freeze(ap);
1822 * mv_err_intr - Handle error interrupts on the port
1823 * @ap: ATA channel to manipulate
1825 * Most cases require a full reset of the chip's state machine,
1826 * which also performs a COMRESET.
1827 * Also, if the port disabled DMA, update our cached copy to match.
1830 * Inherited from caller.
1832 static void mv_err_intr(struct ata_port *ap)
1834 void __iomem *port_mmio = mv_ap_base(ap);
1835 u32 edma_err_cause, eh_freeze_mask, serr = 0;
1837 struct mv_port_priv *pp = ap->private_data;
1838 struct mv_host_priv *hpriv = ap->host->private_data;
1839 unsigned int action = 0, err_mask = 0;
1840 struct ata_eh_info *ehi = &ap->link.eh_info;
1841 struct ata_queued_cmd *qc;
1845 * Read and clear the SError and err_cause bits.
1846 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
1847 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
1849 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1850 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
1852 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1853 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
1854 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1855 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1857 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1859 if (edma_err_cause & EDMA_ERR_DEV) {
1861 * Device errors during FIS-based switching operation
1862 * require special handling.
1864 if (mv_handle_dev_err(ap, edma_err_cause))
1868 qc = mv_get_active_qc(ap);
1869 ata_ehi_clear_desc(ehi);
1870 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
1871 edma_err_cause, pp->pp_flags);
1873 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
1874 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
1875 if (fis_cause & SATA_FIS_IRQ_AN) {
1876 u32 ec = edma_err_cause &
1877 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
1878 sata_async_notification(ap);
1880 return; /* Just an AN; no need for the nukes */
1881 ata_ehi_push_desc(ehi, "SDB notify");
1885 * All generations share these EDMA error cause bits:
1887 if (edma_err_cause & EDMA_ERR_DEV) {
1888 err_mask |= AC_ERR_DEV;
1889 action |= ATA_EH_RESET;
1890 ata_ehi_push_desc(ehi, "dev error");
1892 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
1893 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
1894 EDMA_ERR_INTRL_PAR)) {
1895 err_mask |= AC_ERR_ATA_BUS;
1896 action |= ATA_EH_RESET;
1897 ata_ehi_push_desc(ehi, "parity error");
1899 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1900 ata_ehi_hotplugged(ehi);
1901 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
1902 "dev disconnect" : "dev connect");
1903 action |= ATA_EH_RESET;
1907 * Gen-I has a different SELF_DIS bit,
1908 * different FREEZE bits, and no SERR bit:
1910 if (IS_GEN_I(hpriv)) {
1911 eh_freeze_mask = EDMA_EH_FREEZE_5;
1912 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
1913 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1914 ata_ehi_push_desc(ehi, "EDMA self-disable");
1917 eh_freeze_mask = EDMA_EH_FREEZE;
1918 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1919 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1920 ata_ehi_push_desc(ehi, "EDMA self-disable");
1922 if (edma_err_cause & EDMA_ERR_SERR) {
1923 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1924 err_mask |= AC_ERR_ATA_BUS;
1925 action |= ATA_EH_RESET;
1930 err_mask = AC_ERR_OTHER;
1931 action |= ATA_EH_RESET;
1934 ehi->serror |= serr;
1935 ehi->action |= action;
1938 qc->err_mask |= err_mask;
1940 ehi->err_mask |= err_mask;
1942 if (err_mask == AC_ERR_DEV) {
1944 * Cannot do ata_port_freeze() here,
1945 * because it would kill PIO access,
1946 * which is needed for further diagnosis.
1950 } else if (edma_err_cause & eh_freeze_mask) {
1952 * Note to self: ata_port_freeze() calls ata_port_abort()
1954 ata_port_freeze(ap);
1961 ata_link_abort(qc->dev->link);
1967 static void mv_process_crpb_response(struct ata_port *ap,
1968 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1970 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1974 u16 edma_status = le16_to_cpu(response->flags);
1976 * edma_status from a response queue entry:
1977 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1978 * MSB is saved ATA status from command completion.
1981 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1984 * Error will be seen/handled by mv_err_intr().
1985 * So do nothing at all here.
1990 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
1991 if (!ac_err_mask(ata_status))
1992 ata_qc_complete(qc);
1993 /* else: leave it for mv_err_intr() */
1995 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2000 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
2002 void __iomem *port_mmio = mv_ap_base(ap);
2003 struct mv_host_priv *hpriv = ap->host->private_data;
2005 bool work_done = false;
2006 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
2008 /* Get the hardware queue position index */
2009 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
2010 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2012 /* Process new responses from since the last time we looked */
2013 while (in_index != pp->resp_idx) {
2015 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
2017 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2019 if (IS_GEN_I(hpriv)) {
2020 /* 50xx: no NCQ, only one command active at a time */
2021 tag = ap->link.active_tag;
2023 /* Gen II/IIE: get command tag from CRPB entry */
2024 tag = le16_to_cpu(response->id) & 0x1f;
2026 mv_process_crpb_response(ap, response, tag, ncq_enabled);
2030 /* Update the software queue position index in hardware */
2032 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2033 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2034 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
2037 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2039 struct mv_port_priv *pp;
2040 int edma_was_enabled;
2042 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2043 mv_unexpected_intr(ap, 0);
2047 * Grab a snapshot of the EDMA_EN flag setting,
2048 * so that we have a consistent view for this port,
2049 * even if something we call of our routines changes it.
2051 pp = ap->private_data;
2052 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2054 * Process completed CRPB response(s) before other events.
2056 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2057 mv_process_crpb_entries(ap, pp);
2058 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2059 mv_handle_fbs_ncq_dev_err(ap);
2062 * Handle chip-reported errors, or continue on to handle PIO.
2064 if (unlikely(port_cause & ERR_IRQ)) {
2066 } else if (!edma_was_enabled) {
2067 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2069 ata_sff_host_intr(ap, qc);
2071 mv_unexpected_intr(ap, edma_was_enabled);
2076 * mv_host_intr - Handle all interrupts on the given host controller
2077 * @host: host specific structure
2078 * @main_irq_cause: Main interrupt cause register for the chip.
2081 * Inherited from caller.
2083 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2085 struct mv_host_priv *hpriv = host->private_data;
2086 void __iomem *mmio = hpriv->base, *hc_mmio;
2087 unsigned int handled = 0, port;
2089 for (port = 0; port < hpriv->n_ports; port++) {
2090 struct ata_port *ap = host->ports[port];
2091 unsigned int p, shift, hardport, port_cause;
2093 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2095 * Each hc within the host has its own hc_irq_cause register,
2096 * where the interrupting ports bits get ack'd.
2098 if (hardport == 0) { /* first port on this hc ? */
2099 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2100 u32 port_mask, ack_irqs;
2102 * Skip this entire hc if nothing pending for any ports
2105 port += MV_PORTS_PER_HC - 1;
2109 * We don't need/want to read the hc_irq_cause register,
2110 * because doing so hurts performance, and
2111 * main_irq_cause already gives us everything we need.
2113 * But we do have to *write* to the hc_irq_cause to ack
2114 * the ports that we are handling this time through.
2116 * This requires that we create a bitmap for those
2117 * ports which interrupted us, and use that bitmap
2118 * to ack (only) those ports via hc_irq_cause.
2121 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2122 if ((port + p) >= hpriv->n_ports)
2124 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2125 if (hc_cause & port_mask)
2126 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2128 hc_mmio = mv_hc_base_from_port(mmio, port);
2129 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
2133 * Handle interrupts signalled for this port:
2135 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2137 mv_port_intr(ap, port_cause);
2142 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2144 struct mv_host_priv *hpriv = host->private_data;
2145 struct ata_port *ap;
2146 struct ata_queued_cmd *qc;
2147 struct ata_eh_info *ehi;
2148 unsigned int i, err_mask, printed = 0;
2151 err_cause = readl(mmio + hpriv->irq_cause_ofs);
2153 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2156 DPRINTK("All regs @ PCI error\n");
2157 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2159 writelfl(0, mmio + hpriv->irq_cause_ofs);
2161 for (i = 0; i < host->n_ports; i++) {
2162 ap = host->ports[i];
2163 if (!ata_link_offline(&ap->link)) {
2164 ehi = &ap->link.eh_info;
2165 ata_ehi_clear_desc(ehi);
2167 ata_ehi_push_desc(ehi,
2168 "PCI err cause 0x%08x", err_cause);
2169 err_mask = AC_ERR_HOST_BUS;
2170 ehi->action = ATA_EH_RESET;
2171 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2173 qc->err_mask |= err_mask;
2175 ehi->err_mask |= err_mask;
2177 ata_port_freeze(ap);
2180 return 1; /* handled */
2184 * mv_interrupt - Main interrupt event handler
2186 * @dev_instance: private data; in this case the host structure
2188 * Read the read only register to determine if any host
2189 * controllers have pending interrupts. If so, call lower level
2190 * routine to handle. Also check for PCI errors which are only
2194 * This routine holds the host lock while processing pending
2197 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2199 struct ata_host *host = dev_instance;
2200 struct mv_host_priv *hpriv = host->private_data;
2201 unsigned int handled = 0;
2202 u32 main_irq_cause, pending_irqs;
2204 spin_lock(&host->lock);
2205 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2206 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
2208 * Deal with cases where we either have nothing pending, or have read
2209 * a bogus register value which can indicate HW removal or PCI fault.
2211 if (pending_irqs && main_irq_cause != 0xffffffffU) {
2212 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
2213 handled = mv_pci_error(host, hpriv->base);
2215 handled = mv_host_intr(host, pending_irqs);
2217 spin_unlock(&host->lock);
2218 return IRQ_RETVAL(handled);
2221 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2225 switch (sc_reg_in) {
2229 ofs = sc_reg_in * sizeof(u32);
2238 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
2240 struct mv_host_priv *hpriv = link->ap->host->private_data;
2241 void __iomem *mmio = hpriv->base;
2242 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
2243 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2245 if (ofs != 0xffffffffU) {
2246 *val = readl(addr + ofs);
2252 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
2254 struct mv_host_priv *hpriv = link->ap->host->private_data;
2255 void __iomem *mmio = hpriv->base;
2256 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
2257 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2259 if (ofs != 0xffffffffU) {
2260 writelfl(val, addr + ofs);
2266 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
2268 struct pci_dev *pdev = to_pci_dev(host->dev);
2271 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
2274 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2276 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2279 mv_reset_pci_bus(host, mmio);
2282 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2284 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
2287 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
2290 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2293 tmp = readl(phy_mmio + MV5_PHY_MODE);
2295 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2296 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
2299 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2303 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
2305 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2307 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2309 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2312 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2315 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2316 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2318 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2321 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
2323 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
2325 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
2328 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
2331 tmp = readl(phy_mmio + MV5_PHY_MODE);
2333 tmp |= hpriv->signal[port].pre;
2334 tmp |= hpriv->signal[port].amps;
2335 writel(tmp, phy_mmio + MV5_PHY_MODE);
2340 #define ZERO(reg) writel(0, port_mmio + (reg))
2341 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2344 void __iomem *port_mmio = mv_port_base(mmio, port);
2346 mv_reset_channel(hpriv, mmio, port);
2348 ZERO(0x028); /* command */
2349 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2350 ZERO(0x004); /* timer */
2351 ZERO(0x008); /* irq err cause */
2352 ZERO(0x00c); /* irq err mask */
2353 ZERO(0x010); /* rq bah */
2354 ZERO(0x014); /* rq inp */
2355 ZERO(0x018); /* rq outp */
2356 ZERO(0x01c); /* respq bah */
2357 ZERO(0x024); /* respq outp */
2358 ZERO(0x020); /* respq inp */
2359 ZERO(0x02c); /* test control */
2360 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2364 #define ZERO(reg) writel(0, hc_mmio + (reg))
2365 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2368 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2376 tmp = readl(hc_mmio + 0x20);
2379 writel(tmp, hc_mmio + 0x20);
2383 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2386 unsigned int hc, port;
2388 for (hc = 0; hc < n_hc; hc++) {
2389 for (port = 0; port < MV_PORTS_PER_HC; port++)
2390 mv5_reset_hc_port(hpriv, mmio,
2391 (hc * MV_PORTS_PER_HC) + port);
2393 mv5_reset_one_hc(hpriv, mmio, hc);
2400 #define ZERO(reg) writel(0, mmio + (reg))
2401 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
2403 struct mv_host_priv *hpriv = host->private_data;
2406 tmp = readl(mmio + MV_PCI_MODE_OFS);
2408 writel(tmp, mmio + MV_PCI_MODE_OFS);
2410 ZERO(MV_PCI_DISC_TIMER);
2411 ZERO(MV_PCI_MSI_TRIGGER);
2412 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
2413 ZERO(MV_PCI_SERR_MASK);
2414 ZERO(hpriv->irq_cause_ofs);
2415 ZERO(hpriv->irq_mask_ofs);
2416 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2417 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2418 ZERO(MV_PCI_ERR_ATTRIBUTE);
2419 ZERO(MV_PCI_ERR_COMMAND);
2423 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2427 mv5_reset_flash(hpriv, mmio);
2429 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
2431 tmp |= (1 << 5) | (1 << 6);
2432 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
2436 * mv6_reset_hc - Perform the 6xxx global soft reset
2437 * @mmio: base address of the HBA
2439 * This routine only applies to 6xxx parts.
2442 * Inherited from caller.
2444 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2447 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2451 /* Following procedure defined in PCI "main command and status
2455 writel(t | STOP_PCI_MASTER, reg);
2457 for (i = 0; i < 1000; i++) {
2460 if (PCI_MASTER_EMPTY & t)
2463 if (!(PCI_MASTER_EMPTY & t)) {
2464 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2472 writel(t | GLOB_SFT_RST, reg);
2475 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2477 if (!(GLOB_SFT_RST & t)) {
2478 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2483 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2486 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2489 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2491 if (GLOB_SFT_RST & t) {
2492 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2499 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
2502 void __iomem *port_mmio;
2505 tmp = readl(mmio + MV_RESET_CFG_OFS);
2506 if ((tmp & (1 << 0)) == 0) {
2507 hpriv->signal[idx].amps = 0x7 << 8;
2508 hpriv->signal[idx].pre = 0x1 << 5;
2512 port_mmio = mv_port_base(mmio, idx);
2513 tmp = readl(port_mmio + PHY_MODE2);
2515 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2516 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2519 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2521 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
2524 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2527 void __iomem *port_mmio = mv_port_base(mmio, port);
2529 u32 hp_flags = hpriv->hp_flags;
2531 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2533 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2536 if (fix_phy_mode2) {
2537 m2 = readl(port_mmio + PHY_MODE2);
2540 writel(m2, port_mmio + PHY_MODE2);
2544 m2 = readl(port_mmio + PHY_MODE2);
2545 m2 &= ~((1 << 16) | (1 << 31));
2546 writel(m2, port_mmio + PHY_MODE2);
2552 * Gen-II/IIe PHY_MODE3 errata RM#2:
2553 * Achieves better receiver noise performance than the h/w default:
2555 m3 = readl(port_mmio + PHY_MODE3);
2556 m3 = (m3 & 0x1f) | (0x5555601 << 5);
2558 /* Guideline 88F5182 (GL# SATA-S11) */
2562 if (fix_phy_mode4) {
2563 u32 m4 = readl(port_mmio + PHY_MODE4);
2565 * Enforce reserved-bit restrictions on GenIIe devices only.
2566 * For earlier chipsets, force only the internal config field
2567 * (workaround for errata FEr SATA#10 part 1).
2569 if (IS_GEN_IIE(hpriv))
2570 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
2572 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
2573 writel(m4, port_mmio + PHY_MODE4);
2576 * Workaround for 60x1-B2 errata SATA#13:
2577 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
2578 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
2580 writel(m3, port_mmio + PHY_MODE3);
2582 /* Revert values of pre-emphasis and signal amps to the saved ones */
2583 m2 = readl(port_mmio + PHY_MODE2);
2585 m2 &= ~MV_M2_PREAMP_MASK;
2586 m2 |= hpriv->signal[port].amps;
2587 m2 |= hpriv->signal[port].pre;
2590 /* according to mvSata 3.6.1, some IIE values are fixed */
2591 if (IS_GEN_IIE(hpriv)) {
2596 writel(m2, port_mmio + PHY_MODE2);
2599 /* TODO: use the generic LED interface to configure the SATA Presence */
2600 /* & Acitivy LEDs on the board */
2601 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2607 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2610 void __iomem *port_mmio;
2613 port_mmio = mv_port_base(mmio, idx);
2614 tmp = readl(port_mmio + PHY_MODE2);
2616 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2617 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2621 #define ZERO(reg) writel(0, port_mmio + (reg))
2622 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2623 void __iomem *mmio, unsigned int port)
2625 void __iomem *port_mmio = mv_port_base(mmio, port);
2627 mv_reset_channel(hpriv, mmio, port);
2629 ZERO(0x028); /* command */
2630 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2631 ZERO(0x004); /* timer */
2632 ZERO(0x008); /* irq err cause */
2633 ZERO(0x00c); /* irq err mask */
2634 ZERO(0x010); /* rq bah */
2635 ZERO(0x014); /* rq inp */
2636 ZERO(0x018); /* rq outp */
2637 ZERO(0x01c); /* respq bah */
2638 ZERO(0x024); /* respq outp */
2639 ZERO(0x020); /* respq inp */
2640 ZERO(0x02c); /* test control */
2641 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2646 #define ZERO(reg) writel(0, hc_mmio + (reg))
2647 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2650 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2660 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2661 void __iomem *mmio, unsigned int n_hc)
2665 for (port = 0; port < hpriv->n_ports; port++)
2666 mv_soc_reset_hc_port(hpriv, mmio, port);
2668 mv_soc_reset_one_hc(hpriv, mmio);
2673 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2679 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2684 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
2686 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
2688 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
2690 ifcfg |= (1 << 7); /* enable gen2i speed */
2691 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
2694 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
2695 unsigned int port_no)
2697 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2700 * The datasheet warns against setting EDMA_RESET when EDMA is active
2701 * (but doesn't say what the problem might be). So we first try
2702 * to disable the EDMA engine before doing the EDMA_RESET operation.
2704 mv_stop_edma_engine(port_mmio);
2705 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2707 if (!IS_GEN_I(hpriv)) {
2708 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2709 mv_setup_ifcfg(port_mmio, 1);
2712 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
2713 * link, and physical layers. It resets all SATA interface registers
2714 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
2716 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2717 udelay(25); /* allow reset propagation */
2718 writelfl(0, port_mmio + EDMA_CMD_OFS);
2720 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2722 if (IS_GEN_I(hpriv))
2726 static void mv_pmp_select(struct ata_port *ap, int pmp)
2728 if (sata_pmp_supported(ap)) {
2729 void __iomem *port_mmio = mv_ap_base(ap);
2730 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2731 int old = reg & 0xf;
2734 reg = (reg & ~0xf) | pmp;
2735 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2740 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2741 unsigned long deadline)
2743 mv_pmp_select(link->ap, sata_srst_pmp(link));
2744 return sata_std_hardreset(link, class, deadline);
2747 static int mv_softreset(struct ata_link *link, unsigned int *class,
2748 unsigned long deadline)
2750 mv_pmp_select(link->ap, sata_srst_pmp(link));
2751 return ata_sff_softreset(link, class, deadline);
2754 static int mv_hardreset(struct ata_link *link, unsigned int *class,
2755 unsigned long deadline)
2757 struct ata_port *ap = link->ap;
2758 struct mv_host_priv *hpriv = ap->host->private_data;
2759 struct mv_port_priv *pp = ap->private_data;
2760 void __iomem *mmio = hpriv->base;
2761 int rc, attempts = 0, extra = 0;
2765 mv_reset_channel(hpriv, mmio, ap->port_no);
2766 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2768 /* Workaround for errata FEr SATA#10 (part 2) */
2770 const unsigned long *timing =
2771 sata_ehc_deb_timing(&link->eh_context);
2773 rc = sata_link_hardreset(link, timing, deadline + extra,
2775 rc = online ? -EAGAIN : rc;
2778 sata_scr_read(link, SCR_STATUS, &sstatus);
2779 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2780 /* Force 1.5gb/s link speed and try again */
2781 mv_setup_ifcfg(mv_ap_base(ap), 0);
2782 if (time_after(jiffies + HZ, deadline))
2783 extra = HZ; /* only extend it once, max */
2785 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
2790 static void mv_eh_freeze(struct ata_port *ap)
2793 mv_enable_port_irqs(ap, 0);
2796 static void mv_eh_thaw(struct ata_port *ap)
2798 struct mv_host_priv *hpriv = ap->host->private_data;
2799 unsigned int port = ap->port_no;
2800 unsigned int hardport = mv_hardport_from_port(port);
2801 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
2802 void __iomem *port_mmio = mv_ap_base(ap);
2805 /* clear EDMA errors on this port */
2806 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2808 /* clear pending irq events */
2809 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
2810 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
2812 mv_enable_port_irqs(ap, ERR_IRQ);
2816 * mv_port_init - Perform some early initialization on a single port.
2817 * @port: libata data structure storing shadow register addresses
2818 * @port_mmio: base address of the port
2820 * Initialize shadow register mmio addresses, clear outstanding
2821 * interrupts on the port, and unmask interrupts for the future
2822 * start of the port.
2825 * Inherited from caller.
2827 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2829 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
2832 /* PIO related setup
2834 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
2836 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2837 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2838 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2839 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2840 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2841 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
2843 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2844 /* special case: control/altstatus doesn't have ATA_REG_ address */
2845 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2848 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
2850 /* Clear any currently outstanding port interrupt conditions */
2851 serr_ofs = mv_scr_offset(SCR_ERROR);
2852 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2853 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2855 /* unmask all non-transient EDMA error interrupts */
2856 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
2858 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2859 readl(port_mmio + EDMA_CFG_OFS),
2860 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2861 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2864 static unsigned int mv_in_pcix_mode(struct ata_host *host)
2866 struct mv_host_priv *hpriv = host->private_data;
2867 void __iomem *mmio = hpriv->base;
2870 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
2871 return 0; /* not PCI-X capable */
2872 reg = readl(mmio + MV_PCI_MODE_OFS);
2873 if ((reg & MV_PCI_MODE_MASK) == 0)
2874 return 0; /* conventional PCI mode */
2875 return 1; /* chip is in PCI-X mode */
2878 static int mv_pci_cut_through_okay(struct ata_host *host)
2880 struct mv_host_priv *hpriv = host->private_data;
2881 void __iomem *mmio = hpriv->base;
2884 if (!mv_in_pcix_mode(host)) {
2885 reg = readl(mmio + PCI_COMMAND_OFS);
2886 if (reg & PCI_COMMAND_MRDTRIG)
2887 return 0; /* not okay */
2889 return 1; /* okay */
2892 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
2894 struct pci_dev *pdev = to_pci_dev(host->dev);
2895 struct mv_host_priv *hpriv = host->private_data;
2896 u32 hp_flags = hpriv->hp_flags;
2898 switch (board_idx) {
2900 hpriv->ops = &mv5xxx_ops;
2901 hp_flags |= MV_HP_GEN_I;
2903 switch (pdev->revision) {
2905 hp_flags |= MV_HP_ERRATA_50XXB0;
2908 hp_flags |= MV_HP_ERRATA_50XXB2;
2911 dev_printk(KERN_WARNING, &pdev->dev,
2912 "Applying 50XXB2 workarounds to unknown rev\n");
2913 hp_flags |= MV_HP_ERRATA_50XXB2;
2920 hpriv->ops = &mv5xxx_ops;
2921 hp_flags |= MV_HP_GEN_I;
2923 switch (pdev->revision) {
2925 hp_flags |= MV_HP_ERRATA_50XXB0;
2928 hp_flags |= MV_HP_ERRATA_50XXB2;
2931 dev_printk(KERN_WARNING, &pdev->dev,
2932 "Applying B2 workarounds to unknown rev\n");
2933 hp_flags |= MV_HP_ERRATA_50XXB2;
2940 hpriv->ops = &mv6xxx_ops;
2941 hp_flags |= MV_HP_GEN_II;
2943 switch (pdev->revision) {
2945 hp_flags |= MV_HP_ERRATA_60X1B2;
2948 hp_flags |= MV_HP_ERRATA_60X1C0;
2951 dev_printk(KERN_WARNING, &pdev->dev,
2952 "Applying B2 workarounds to unknown rev\n");
2953 hp_flags |= MV_HP_ERRATA_60X1B2;
2959 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
2960 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2961 (pdev->device == 0x2300 || pdev->device == 0x2310))
2964 * Highpoint RocketRAID PCIe 23xx series cards:
2966 * Unconfigured drives are treated as "Legacy"
2967 * by the BIOS, and it overwrites sector 8 with
2968 * a "Lgcy" metadata block prior to Linux boot.
2970 * Configured drives (RAID or JBOD) leave sector 8
2971 * alone, but instead overwrite a high numbered
2972 * sector for the RAID metadata. This sector can
2973 * be determined exactly, by truncating the physical
2974 * drive capacity to a nice even GB value.
2976 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2978 * Warn the user, lest they think we're just buggy.
2980 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2981 " BIOS CORRUPTS DATA on all attached drives,"
2982 " regardless of if/how they are configured."
2984 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2985 " use sectors 8-9 on \"Legacy\" drives,"
2986 " and avoid the final two gigabytes on"
2987 " all RocketRAID BIOS initialized drives.\n");
2991 hpriv->ops = &mv6xxx_ops;
2992 hp_flags |= MV_HP_GEN_IIE;
2993 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
2994 hp_flags |= MV_HP_CUT_THROUGH;
2996 switch (pdev->revision) {
2997 case 0x2: /* Rev.B0: the first/only public release */
2998 hp_flags |= MV_HP_ERRATA_60X1C0;
3001 dev_printk(KERN_WARNING, &pdev->dev,
3002 "Applying 60X1C0 workarounds to unknown rev\n");
3003 hp_flags |= MV_HP_ERRATA_60X1C0;
3008 hpriv->ops = &mv_soc_ops;
3009 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3010 MV_HP_ERRATA_60X1C0;
3014 dev_printk(KERN_ERR, host->dev,
3015 "BUG: invalid board index %u\n", board_idx);
3019 hpriv->hp_flags = hp_flags;
3020 if (hp_flags & MV_HP_PCIE) {
3021 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3022 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3023 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3025 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3026 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3027 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3034 * mv_init_host - Perform some early initialization of the host.
3035 * @host: ATA host to initialize
3036 * @board_idx: controller index
3038 * If possible, do an early global reset of the host. Then do
3039 * our port init and clear/unmask all/relevant host interrupts.
3042 * Inherited from caller.
3044 static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3046 int rc = 0, n_hc, port, hc;
3047 struct mv_host_priv *hpriv = host->private_data;
3048 void __iomem *mmio = hpriv->base;
3050 rc = mv_chip_id(host, board_idx);
3054 if (IS_SOC(hpriv)) {
3055 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3056 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
3058 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3059 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
3062 /* initialize shadow irq mask with register's value */
3063 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3065 /* global interrupt mask: 0 == mask everything */
3066 mv_set_main_irq_mask(host, ~0, 0);
3068 n_hc = mv_get_hc_count(host->ports[0]->flags);
3070 for (port = 0; port < host->n_ports; port++)
3071 hpriv->ops->read_preamp(hpriv, port, mmio);
3073 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3077 hpriv->ops->reset_flash(hpriv, mmio);
3078 hpriv->ops->reset_bus(host, mmio);
3079 hpriv->ops->enable_leds(hpriv, mmio);
3081 for (port = 0; port < host->n_ports; port++) {
3082 struct ata_port *ap = host->ports[port];
3083 void __iomem *port_mmio = mv_port_base(mmio, port);
3085 mv_port_init(&ap->ioaddr, port_mmio);
3088 if (!IS_SOC(hpriv)) {
3089 unsigned int offset = port_mmio - mmio;
3090 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3091 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3096 for (hc = 0; hc < n_hc; hc++) {
3097 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3099 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3100 "(before clear)=0x%08x\n", hc,
3101 readl(hc_mmio + HC_CFG_OFS),
3102 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3104 /* Clear any currently outstanding hc interrupt conditions */
3105 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
3108 if (!IS_SOC(hpriv)) {
3109 /* Clear any currently outstanding host interrupt conditions */
3110 writelfl(0, mmio + hpriv->irq_cause_ofs);
3112 /* and unmask interrupt generation for host regs */
3113 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
3116 * enable only global host interrupts for now.
3117 * The per-port interrupts get done later as ports are set up.
3119 mv_set_main_irq_mask(host, 0, PCI_ERR);
3125 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3127 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3129 if (!hpriv->crqb_pool)
3132 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3134 if (!hpriv->crpb_pool)
3137 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3139 if (!hpriv->sg_tbl_pool)
3145 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3146 struct mbus_dram_target_info *dram)
3150 for (i = 0; i < 4; i++) {
3151 writel(0, hpriv->base + WINDOW_CTRL(i));
3152 writel(0, hpriv->base + WINDOW_BASE(i));
3155 for (i = 0; i < dram->num_cs; i++) {
3156 struct mbus_dram_window *cs = dram->cs + i;
3158 writel(((cs->size - 1) & 0xffff0000) |
3159 (cs->mbus_attr << 8) |
3160 (dram->mbus_dram_target_id << 4) | 1,
3161 hpriv->base + WINDOW_CTRL(i));
3162 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3167 * mv_platform_probe - handle a positive probe of an soc Marvell
3169 * @pdev: platform device found
3172 * Inherited from caller.
3174 static int mv_platform_probe(struct platform_device *pdev)
3176 static int printed_version;
3177 const struct mv_sata_platform_data *mv_platform_data;
3178 const struct ata_port_info *ppi[] =
3179 { &mv_port_info[chip_soc], NULL };
3180 struct ata_host *host;
3181 struct mv_host_priv *hpriv;
3182 struct resource *res;
3185 if (!printed_version++)
3186 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3189 * Simple resource validation ..
3191 if (unlikely(pdev->num_resources != 2)) {
3192 dev_err(&pdev->dev, "invalid number of resources\n");
3197 * Get the register base first
3199 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3204 mv_platform_data = pdev->dev.platform_data;
3205 n_ports = mv_platform_data->n_ports;
3207 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3208 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3210 if (!host || !hpriv)
3212 host->private_data = hpriv;
3213 hpriv->n_ports = n_ports;
3216 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3217 res->end - res->start + 1);
3218 hpriv->base -= MV_SATAHC0_REG_BASE;
3221 * (Re-)program MBUS remapping windows if we are asked to.
3223 if (mv_platform_data->dram != NULL)
3224 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3226 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3230 /* initialize adapter */
3231 rc = mv_init_host(host, chip_soc);
3235 dev_printk(KERN_INFO, &pdev->dev,
3236 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3239 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3240 IRQF_SHARED, &mv6_sht);
3245 * mv_platform_remove - unplug a platform interface
3246 * @pdev: platform device
3248 * A platform bus SATA device has been unplugged. Perform the needed
3249 * cleanup. Also called on module unload for any active devices.
3251 static int __devexit mv_platform_remove(struct platform_device *pdev)
3253 struct device *dev = &pdev->dev;
3254 struct ata_host *host = dev_get_drvdata(dev);
3256 ata_host_detach(host);
3260 static struct platform_driver mv_platform_driver = {
3261 .probe = mv_platform_probe,
3262 .remove = __devexit_p(mv_platform_remove),
3265 .owner = THIS_MODULE,
3271 static int mv_pci_init_one(struct pci_dev *pdev,
3272 const struct pci_device_id *ent);
3275 static struct pci_driver mv_pci_driver = {
3277 .id_table = mv_pci_tbl,
3278 .probe = mv_pci_init_one,
3279 .remove = ata_pci_remove_one,
3285 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3288 /* move to PCI layer or libata core? */
3289 static int pci_go_64(struct pci_dev *pdev)
3293 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3294 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3296 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3298 dev_printk(KERN_ERR, &pdev->dev,
3299 "64-bit DMA enable failed\n");
3304 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3306 dev_printk(KERN_ERR, &pdev->dev,
3307 "32-bit DMA enable failed\n");
3310 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3312 dev_printk(KERN_ERR, &pdev->dev,
3313 "32-bit consistent DMA enable failed\n");
3322 * mv_print_info - Dump key info to kernel log for perusal.
3323 * @host: ATA host to print info about
3325 * FIXME: complete this.
3328 * Inherited from caller.
3330 static void mv_print_info(struct ata_host *host)
3332 struct pci_dev *pdev = to_pci_dev(host->dev);
3333 struct mv_host_priv *hpriv = host->private_data;
3335 const char *scc_s, *gen;
3337 /* Use this to determine the HW stepping of the chip so we know
3338 * what errata to workaround
3340 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3343 else if (scc == 0x01)
3348 if (IS_GEN_I(hpriv))
3350 else if (IS_GEN_II(hpriv))
3352 else if (IS_GEN_IIE(hpriv))
3357 dev_printk(KERN_INFO, &pdev->dev,
3358 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3359 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
3360 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3364 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
3365 * @pdev: PCI device found
3366 * @ent: PCI device ID entry for the matched host
3369 * Inherited from caller.
3371 static int mv_pci_init_one(struct pci_dev *pdev,
3372 const struct pci_device_id *ent)
3374 static int printed_version;
3375 unsigned int board_idx = (unsigned int)ent->driver_data;
3376 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3377 struct ata_host *host;
3378 struct mv_host_priv *hpriv;
3381 if (!printed_version++)
3382 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3385 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3387 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3388 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3389 if (!host || !hpriv)
3391 host->private_data = hpriv;
3392 hpriv->n_ports = n_ports;
3394 /* acquire resources */
3395 rc = pcim_enable_device(pdev);
3399 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3401 pcim_pin_device(pdev);
3404 host->iomap = pcim_iomap_table(pdev);
3405 hpriv->base = host->iomap[MV_PRIMARY_BAR];
3407 rc = pci_go_64(pdev);
3411 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3415 /* initialize adapter */
3416 rc = mv_init_host(host, board_idx);
3420 /* Enable interrupts */
3421 if (msi && pci_enable_msi(pdev))
3424 mv_dump_pci_cfg(pdev, 0x68);
3425 mv_print_info(host);
3427 pci_set_master(pdev);
3428 pci_try_set_mwi(pdev);
3429 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
3430 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
3434 static int mv_platform_probe(struct platform_device *pdev);
3435 static int __devexit mv_platform_remove(struct platform_device *pdev);
3437 static int __init mv_init(void)
3441 rc = pci_register_driver(&mv_pci_driver);
3445 rc = platform_driver_register(&mv_platform_driver);
3449 pci_unregister_driver(&mv_pci_driver);
3454 static void __exit mv_exit(void)
3457 pci_unregister_driver(&mv_pci_driver);
3459 platform_driver_unregister(&mv_platform_driver);
3462 MODULE_AUTHOR("Brett Russ");
3463 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3464 MODULE_LICENSE("GPL");
3465 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3466 MODULE_VERSION(DRV_VERSION);
3467 MODULE_ALIAS("platform:" DRV_NAME);
3470 module_param(msi, int, 0444);
3471 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
3474 module_init(mv_init);
3475 module_exit(mv_exit);