2 * sata_sis.c - Silicon Integrated Systems SATA
4 * Maintained by: Uwe Koziolek
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004 Uwe Koziolek
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware documentation available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/device.h>
41 #include <scsi/scsi_host.h>
42 #include <linux/libata.h>
45 #define DRV_NAME "sata_sis"
46 #define DRV_VERSION "1.0"
52 /* PCI configuration registers */
53 SIS_GENCTL = 0x54, /* IDE General Control register */
54 SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
55 SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
56 SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
57 SIS_PMR = 0x90, /* port mapping register */
58 SIS_PMR_COMBINED = 0x30,
61 SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
63 GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
66 static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
67 static int sis_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
68 static int sis_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
70 static const struct pci_device_id sis_pci_tbl[] = {
71 { PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
72 { PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
73 { PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
74 { PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
75 { PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/680 */
76 { PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L/968/680 */
78 { } /* terminate list */
81 static struct pci_driver sis_pci_driver = {
83 .id_table = sis_pci_tbl,
84 .probe = sis_init_one,
85 .remove = ata_pci_remove_one,
88 static struct scsi_host_template sis_sht = {
89 ATA_BMDMA_SHT(DRV_NAME),
92 static const struct ata_port_operations sis_ops = {
93 .tf_load = ata_tf_load,
94 .tf_read = ata_tf_read,
95 .check_status = ata_check_status,
96 .exec_command = ata_exec_command,
97 .dev_select = ata_std_dev_select,
98 .bmdma_setup = ata_bmdma_setup,
99 .bmdma_start = ata_bmdma_start,
100 .bmdma_stop = ata_bmdma_stop,
101 .bmdma_status = ata_bmdma_status,
102 .qc_prep = ata_qc_prep,
103 .qc_issue = ata_qc_issue_prot,
104 .data_xfer = ata_data_xfer,
105 .mode_filter = ata_pci_default_filter,
106 .freeze = ata_bmdma_freeze,
107 .thaw = ata_bmdma_thaw,
108 .error_handler = ata_bmdma_error_handler,
109 .post_internal_cmd = ata_bmdma_post_internal_cmd,
110 .irq_clear = ata_bmdma_irq_clear,
111 .irq_on = ata_irq_on,
112 .scr_read = sis_scr_read,
113 .scr_write = sis_scr_write,
114 .port_start = ata_sff_port_start,
117 static const struct ata_port_info sis_port_info = {
118 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &sis_ops,
125 MODULE_AUTHOR("Uwe Koziolek");
126 MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
127 MODULE_LICENSE("GPL");
128 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
129 MODULE_VERSION(DRV_VERSION);
131 static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
133 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
134 unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
138 switch (pdev->device) {
141 pci_read_config_byte(pdev, SIS_PMR, &pmr);
142 if ((pmr & SIS_PMR_COMBINED) == 0)
143 addr += SIS180_SATA1_OFS;
149 addr += SIS182_SATA1_OFS;
156 static u32 sis_scr_cfg_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
158 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
159 unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
163 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
166 pci_read_config_byte(pdev, SIS_PMR, &pmr);
168 pci_read_config_dword(pdev, cfg_addr, val);
170 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
171 (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
172 pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
175 *val &= 0xfffffffb; /* avoid problems with powerdowned ports */
180 static void sis_scr_cfg_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
182 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
183 unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
186 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
189 pci_read_config_byte(pdev, SIS_PMR, &pmr);
191 pci_write_config_dword(pdev, cfg_addr, val);
193 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
194 (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
195 pci_write_config_dword(pdev, cfg_addr+0x10, val);
198 static int sis_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
200 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
203 if (sc_reg > SCR_CONTROL)
206 if (ap->flags & SIS_FLAG_CFGSCR)
207 return sis_scr_cfg_read(ap, sc_reg, val);
209 pci_read_config_byte(pdev, SIS_PMR, &pmr);
211 *val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));
213 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
214 (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
215 *val |= ioread32(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);
222 static int sis_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
224 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
227 if (sc_reg > SCR_CONTROL)
230 pci_read_config_byte(pdev, SIS_PMR, &pmr);
232 if (ap->flags & SIS_FLAG_CFGSCR)
233 sis_scr_cfg_write(ap, sc_reg, val);
235 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
236 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
237 (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
238 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
243 static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
245 static int printed_version;
246 struct ata_port_info pi = sis_port_info;
247 const struct ata_port_info *ppi[] = { &pi, &pi };
248 struct ata_host *host;
251 u8 port2_start = 0x20;
254 if (!printed_version++)
255 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
257 rc = pcim_enable_device(pdev);
261 /* check and see if the SCRs are in IO space or PCI cfg space */
262 pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
263 if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
264 pi.flags |= SIS_FLAG_CFGSCR;
266 /* if hardware thinks SCRs are in IO space, but there are
267 * no IO resources assigned, change to PCI cfg space.
269 if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
270 ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
271 (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
272 genctl &= ~GENCTL_IOMAPPED_SCR;
273 pci_write_config_dword(pdev, SIS_GENCTL, genctl);
274 pi.flags |= SIS_FLAG_CFGSCR;
277 pci_read_config_byte(pdev, SIS_PMR, &pmr);
278 switch (ent->device) {
282 /* The PATA-handling is provided by pata_sis */
283 switch (pmr & 0x30) {
285 ppi[1] = &sis_info133_for_sata;
289 ppi[0] = &sis_info133_for_sata;
292 if ((pmr & SIS_PMR_COMBINED) == 0) {
293 dev_printk(KERN_INFO, &pdev->dev,
294 "Detected SiS 180/181/964 chipset in SATA mode\n");
297 dev_printk(KERN_INFO, &pdev->dev,
298 "Detected SiS 180/181 chipset in combined mode\n");
300 pi.flags |= ATA_FLAG_SLAVE_POSS;
306 pci_read_config_dword(pdev, 0x6C, &val);
307 if (val & (1L << 31)) {
308 dev_printk(KERN_INFO, &pdev->dev,
309 "Detected SiS 182/965 chipset\n");
310 pi.flags |= ATA_FLAG_SLAVE_POSS;
312 dev_printk(KERN_INFO, &pdev->dev,
313 "Detected SiS 182/965L chipset\n");
318 dev_printk(KERN_INFO, &pdev->dev,
319 "Detected SiS 1182/966/680 SATA controller\n");
320 pi.flags |= ATA_FLAG_SLAVE_POSS;
324 dev_printk(KERN_INFO, &pdev->dev,
325 "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
326 ppi[0] = &sis_info133_for_sata;
327 ppi[1] = &sis_info133_for_sata;
331 rc = ata_pci_prepare_sff_host(pdev, ppi, &host);
335 if (!(pi.flags & SIS_FLAG_CFGSCR)) {
338 rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
341 mmio = host->iomap[SIS_SCR_PCI_BAR];
343 host->ports[0]->ioaddr.scr_addr = mmio;
344 host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
347 pci_set_master(pdev);
349 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
353 static int __init sis_init(void)
355 return pci_register_driver(&sis_pci_driver);
358 static void __exit sis_exit(void)
360 pci_unregister_driver(&sis_pci_driver);
363 module_init(sis_init);
364 module_exit(sis_exit);