2 * regmap based irq_chip
4 * Copyright 2011 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/device.h>
14 #include <linux/export.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 #include <linux/slab.h>
24 struct regmap_irq_chip_data {
26 struct irq_chip irq_chip;
29 const struct regmap_irq_chip *chip;
32 struct irq_domain *domain;
38 unsigned int *status_buf;
39 unsigned int *mask_buf;
40 unsigned int *mask_buf_def;
41 unsigned int *wake_buf;
43 unsigned int irq_reg_stride;
47 struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
50 return &data->chip->irqs[irq];
53 static void regmap_irq_lock(struct irq_data *data)
55 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
60 static void regmap_irq_sync_unlock(struct irq_data *data)
62 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
63 struct regmap *map = d->map;
67 if (d->chip->runtime_pm) {
68 ret = pm_runtime_get_sync(map->dev);
70 dev_err(map->dev, "IRQ sync failed to resume: %d\n",
75 * If there's been a change in the mask write it back to the
76 * hardware. We rely on the use of the regmap core cache to
77 * suppress pointless writes.
79 for (i = 0; i < d->chip->num_regs; i++) {
80 reg = d->chip->mask_base +
81 (i * map->reg_stride * d->irq_reg_stride);
82 if (d->chip->mask_invert)
83 ret = regmap_update_bits(d->map, reg,
84 d->mask_buf_def[i], ~d->mask_buf[i]);
86 ret = regmap_update_bits(d->map, reg,
87 d->mask_buf_def[i], d->mask_buf[i]);
89 dev_err(d->map->dev, "Failed to sync masks in %x\n",
92 reg = d->chip->wake_base +
93 (i * map->reg_stride * d->irq_reg_stride);
95 if (d->chip->wake_invert)
96 ret = regmap_update_bits(d->map, reg,
100 ret = regmap_update_bits(d->map, reg,
105 "Failed to sync wakes in %x: %d\n",
109 if (!d->chip->init_ack_masked)
112 * Ack all the masked interrupts unconditionally,
113 * OR if there is masked interrupt which hasn't been Acked,
114 * it'll be ignored in irq handler, then may introduce irq storm
116 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) {
117 reg = d->chip->ack_base +
118 (i * map->reg_stride * d->irq_reg_stride);
119 ret = regmap_write(map, reg, d->mask_buf[i]);
121 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n",
126 if (d->chip->runtime_pm)
127 pm_runtime_put(map->dev);
129 /* If we've changed our wakeup count propagate it to the parent */
130 if (d->wake_count < 0)
131 for (i = d->wake_count; i < 0; i++)
132 irq_set_irq_wake(d->irq, 0);
133 else if (d->wake_count > 0)
134 for (i = 0; i < d->wake_count; i++)
135 irq_set_irq_wake(d->irq, 1);
139 mutex_unlock(&d->lock);
142 static void regmap_irq_enable(struct irq_data *data)
144 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
145 struct regmap *map = d->map;
146 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
148 d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~irq_data->mask;
151 static void regmap_irq_disable(struct irq_data *data)
153 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
154 struct regmap *map = d->map;
155 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
157 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
160 static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
162 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
163 struct regmap *map = d->map;
164 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
168 d->wake_buf[irq_data->reg_offset / map->reg_stride]
173 d->wake_buf[irq_data->reg_offset / map->reg_stride]
181 static const struct irq_chip regmap_irq_chip = {
182 .irq_bus_lock = regmap_irq_lock,
183 .irq_bus_sync_unlock = regmap_irq_sync_unlock,
184 .irq_disable = regmap_irq_disable,
185 .irq_enable = regmap_irq_enable,
186 .irq_set_wake = regmap_irq_set_wake,
189 static irqreturn_t regmap_irq_thread(int irq, void *d)
191 struct regmap_irq_chip_data *data = d;
192 const struct regmap_irq_chip *chip = data->chip;
193 struct regmap *map = data->map;
195 bool handled = false;
198 if (chip->runtime_pm) {
199 ret = pm_runtime_get_sync(map->dev);
201 dev_err(map->dev, "IRQ thread failed to resume: %d\n",
203 pm_runtime_put(map->dev);
209 * Read in the statuses, using a single bulk read if possible
210 * in order to reduce the I/O overheads.
212 if (!map->use_single_rw && map->reg_stride == 1 &&
213 data->irq_reg_stride == 1) {
214 u8 *buf8 = data->status_reg_buf;
215 u16 *buf16 = data->status_reg_buf;
216 u32 *buf32 = data->status_reg_buf;
218 BUG_ON(!data->status_reg_buf);
220 ret = regmap_bulk_read(map, chip->status_base,
221 data->status_reg_buf,
224 dev_err(map->dev, "Failed to read IRQ status: %d\n",
229 for (i = 0; i < data->chip->num_regs; i++) {
230 switch (map->format.val_bytes) {
232 data->status_buf[i] = buf8[i];
235 data->status_buf[i] = buf16[i];
238 data->status_buf[i] = buf32[i];
247 for (i = 0; i < data->chip->num_regs; i++) {
248 ret = regmap_read(map, chip->status_base +
250 * data->irq_reg_stride),
251 &data->status_buf[i]);
255 "Failed to read IRQ status: %d\n",
257 if (chip->runtime_pm)
258 pm_runtime_put(map->dev);
265 * Ignore masked IRQs and ack if we need to; we ack early so
266 * there is no race between handling and acknowleding the
267 * interrupt. We assume that typically few of the interrupts
268 * will fire simultaneously so don't worry about overhead from
269 * doing a write per register.
271 for (i = 0; i < data->chip->num_regs; i++) {
272 data->status_buf[i] &= ~data->mask_buf[i];
274 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) {
275 reg = chip->ack_base +
276 (i * map->reg_stride * data->irq_reg_stride);
277 ret = regmap_write(map, reg, data->status_buf[i]);
279 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
284 for (i = 0; i < chip->num_irqs; i++) {
285 if (data->status_buf[chip->irqs[i].reg_offset /
286 map->reg_stride] & chip->irqs[i].mask) {
287 handle_nested_irq(irq_find_mapping(data->domain, i));
292 if (chip->runtime_pm)
293 pm_runtime_put(map->dev);
301 static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
304 struct regmap_irq_chip_data *data = h->host_data;
306 irq_set_chip_data(virq, data);
307 irq_set_chip(virq, &data->irq_chip);
308 irq_set_nested_thread(virq, 1);
309 irq_set_noprobe(virq);
314 static const struct irq_domain_ops regmap_domain_ops = {
315 .map = regmap_irq_map,
316 .xlate = irq_domain_xlate_twocell,
320 * regmap_add_irq_chip(): Use standard regmap IRQ controller handling
322 * map: The regmap for the device.
323 * irq: The IRQ the device uses to signal interrupts
324 * irq_flags: The IRQF_ flags to use for the primary interrupt.
325 * chip: Configuration for the interrupt controller.
326 * data: Runtime data structure for the controller, allocated on success
328 * Returns 0 on success or an errno on failure.
330 * In order for this to be efficient the chip really should use a
331 * register cache. The chip driver is responsible for restoring the
332 * register values used by the IRQ controller over suspend and resume.
334 int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
335 int irq_base, const struct regmap_irq_chip *chip,
336 struct regmap_irq_chip_data **data)
338 struct regmap_irq_chip_data *d;
343 if (chip->num_regs <= 0)
346 for (i = 0; i < chip->num_irqs; i++) {
347 if (chip->irqs[i].reg_offset % map->reg_stride)
349 if (chip->irqs[i].reg_offset / map->reg_stride >=
355 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
357 dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
363 d = kzalloc(sizeof(*d), GFP_KERNEL);
367 d->status_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
372 d->mask_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
377 d->mask_buf_def = kzalloc(sizeof(unsigned int) * chip->num_regs,
379 if (!d->mask_buf_def)
382 if (chip->wake_base) {
383 d->wake_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
389 d->irq_chip = regmap_irq_chip;
390 d->irq_chip.name = chip->name;
394 d->irq_base = irq_base;
396 if (chip->irq_reg_stride)
397 d->irq_reg_stride = chip->irq_reg_stride;
399 d->irq_reg_stride = 1;
401 if (!map->use_single_rw && map->reg_stride == 1 &&
402 d->irq_reg_stride == 1) {
403 d->status_reg_buf = kmalloc(map->format.val_bytes *
404 chip->num_regs, GFP_KERNEL);
405 if (!d->status_reg_buf)
409 mutex_init(&d->lock);
411 for (i = 0; i < chip->num_irqs; i++)
412 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
413 |= chip->irqs[i].mask;
415 /* Mask all the interrupts by default */
416 for (i = 0; i < chip->num_regs; i++) {
417 d->mask_buf[i] = d->mask_buf_def[i];
418 reg = chip->mask_base +
419 (i * map->reg_stride * d->irq_reg_stride);
420 if (chip->mask_invert)
421 ret = regmap_update_bits(map, reg,
422 d->mask_buf[i], ~d->mask_buf[i]);
424 ret = regmap_update_bits(map, reg,
425 d->mask_buf[i], d->mask_buf[i]);
427 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
432 if (!chip->init_ack_masked)
435 /* Ack masked but set interrupts */
436 reg = chip->status_base +
437 (i * map->reg_stride * d->irq_reg_stride);
438 ret = regmap_read(map, reg, &d->status_buf[i]);
440 dev_err(map->dev, "Failed to read IRQ status: %d\n",
445 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) {
446 reg = chip->ack_base +
447 (i * map->reg_stride * d->irq_reg_stride);
448 ret = regmap_write(map, reg,
449 d->status_buf[i] & d->mask_buf[i]);
451 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
458 /* Wake is disabled by default */
460 for (i = 0; i < chip->num_regs; i++) {
461 d->wake_buf[i] = d->mask_buf_def[i];
462 reg = chip->wake_base +
463 (i * map->reg_stride * d->irq_reg_stride);
465 if (chip->wake_invert)
466 ret = regmap_update_bits(map, reg,
470 ret = regmap_update_bits(map, reg,
474 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
482 d->domain = irq_domain_add_legacy(map->dev->of_node,
483 chip->num_irqs, irq_base, 0,
484 ®map_domain_ops, d);
486 d->domain = irq_domain_add_linear(map->dev->of_node,
488 ®map_domain_ops, d);
490 dev_err(map->dev, "Failed to create IRQ domain\n");
495 ret = request_threaded_irq(irq, NULL, regmap_irq_thread,
496 irq_flags | IRQF_ONESHOT,
499 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n",
500 irq, chip->name, ret);
509 /* Should really dispose of the domain but... */
512 kfree(d->mask_buf_def);
514 kfree(d->status_buf);
515 kfree(d->status_reg_buf);
519 EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
522 * regmap_del_irq_chip(): Stop interrupt handling for a regmap IRQ chip
524 * @irq: Primary IRQ for the device
525 * @d: regmap_irq_chip_data allocated by regmap_add_irq_chip()
527 void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
533 irq_domain_remove(d->domain);
535 kfree(d->mask_buf_def);
537 kfree(d->status_reg_buf);
538 kfree(d->status_buf);
541 EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
544 * regmap_irq_chip_get_base(): Retrieve interrupt base for a regmap IRQ chip
546 * Useful for drivers to request their own IRQs.
548 * @data: regmap_irq controller to operate on.
550 int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
552 WARN_ON(!data->irq_base);
553 return data->irq_base;
555 EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
558 * regmap_irq_get_virq(): Map an interrupt on a chip to a virtual IRQ
560 * Useful for drivers to request their own IRQs.
562 * @data: regmap_irq controller to operate on.
563 * @irq: index of the interrupt requested in the chip IRQs
565 int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
567 /* Handle holes in the IRQ list */
568 if (!data->chip->irqs[irq].mask)
571 return irq_create_mapping(data->domain, irq);
573 EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
576 * regmap_irq_get_domain(): Retrieve the irq_domain for the chip
578 * Useful for drivers to request their own IRQs and for integration
579 * with subsystems. For ease of integration NULL is accepted as a
580 * domain, allowing devices to just call this even if no domain is
583 * @data: regmap_irq controller to operate on.
585 struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data)
592 EXPORT_SYMBOL_GPL(regmap_irq_get_domain);