2 * regmap based irq_chip
4 * Copyright 2011 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/export.h>
14 #include <linux/device.h>
15 #include <linux/regmap.h>
16 #include <linux/irq.h>
17 #include <linux/interrupt.h>
18 #include <linux/irqdomain.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/slab.h>
24 struct regmap_irq_chip_data {
26 struct irq_chip irq_chip;
29 const struct regmap_irq_chip *chip;
32 struct irq_domain *domain;
38 unsigned int *status_buf;
39 unsigned int *mask_buf;
40 unsigned int *mask_buf_def;
41 unsigned int *wake_buf;
43 unsigned int irq_reg_stride;
47 struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
50 return &data->chip->irqs[irq];
53 static void regmap_irq_lock(struct irq_data *data)
55 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
60 static void regmap_irq_sync_unlock(struct irq_data *data)
62 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
63 struct regmap *map = d->map;
67 if (d->chip->runtime_pm) {
68 ret = pm_runtime_get_sync(map->dev);
70 dev_err(map->dev, "IRQ sync failed to resume: %d\n",
75 * If there's been a change in the mask write it back to the
76 * hardware. We rely on the use of the regmap core cache to
77 * suppress pointless writes.
79 for (i = 0; i < d->chip->num_regs; i++) {
80 reg = d->chip->mask_base +
81 (i * map->reg_stride * d->irq_reg_stride);
82 if (d->chip->mask_invert)
83 ret = regmap_update_bits(d->map, reg,
84 d->mask_buf_def[i], ~d->mask_buf[i]);
86 ret = regmap_update_bits(d->map, reg,
87 d->mask_buf_def[i], d->mask_buf[i]);
89 dev_err(d->map->dev, "Failed to sync masks in %x\n",
92 reg = d->chip->wake_base +
93 (i * map->reg_stride * d->irq_reg_stride);
95 if (d->chip->wake_invert)
96 ret = regmap_update_bits(d->map, reg,
100 ret = regmap_update_bits(d->map, reg,
105 "Failed to sync wakes in %x: %d\n",
110 if (d->chip->runtime_pm)
111 pm_runtime_put(map->dev);
113 /* If we've changed our wakeup count propagate it to the parent */
114 if (d->wake_count < 0)
115 for (i = d->wake_count; i < 0; i++)
116 irq_set_irq_wake(d->irq, 0);
117 else if (d->wake_count > 0)
118 for (i = 0; i < d->wake_count; i++)
119 irq_set_irq_wake(d->irq, 1);
123 mutex_unlock(&d->lock);
126 static void regmap_irq_enable(struct irq_data *data)
128 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
129 struct regmap *map = d->map;
130 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
132 d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~irq_data->mask;
135 static void regmap_irq_disable(struct irq_data *data)
137 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
138 struct regmap *map = d->map;
139 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
141 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
144 static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
146 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
147 struct regmap *map = d->map;
148 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
152 d->wake_buf[irq_data->reg_offset / map->reg_stride]
157 d->wake_buf[irq_data->reg_offset / map->reg_stride]
165 static const struct irq_chip regmap_irq_chip = {
166 .irq_bus_lock = regmap_irq_lock,
167 .irq_bus_sync_unlock = regmap_irq_sync_unlock,
168 .irq_disable = regmap_irq_disable,
169 .irq_enable = regmap_irq_enable,
170 .irq_set_wake = regmap_irq_set_wake,
173 static irqreturn_t regmap_irq_thread(int irq, void *d)
175 struct regmap_irq_chip_data *data = d;
176 const struct regmap_irq_chip *chip = data->chip;
177 struct regmap *map = data->map;
179 bool handled = false;
182 if (chip->runtime_pm) {
183 ret = pm_runtime_get_sync(map->dev);
185 dev_err(map->dev, "IRQ thread failed to resume: %d\n",
192 * Read in the statuses, using a single bulk read if possible
193 * in order to reduce the I/O overheads.
195 if (!map->use_single_rw && map->reg_stride == 1 &&
196 data->irq_reg_stride == 1) {
197 u8 *buf8 = data->status_reg_buf;
198 u16 *buf16 = data->status_reg_buf;
199 u32 *buf32 = data->status_reg_buf;
201 BUG_ON(!data->status_reg_buf);
203 ret = regmap_bulk_read(map, chip->status_base,
204 data->status_reg_buf,
207 dev_err(map->dev, "Failed to read IRQ status: %d\n",
212 for (i = 0; i < data->chip->num_regs; i++) {
213 switch (map->format.val_bytes) {
215 data->status_buf[i] = buf8[i];
218 data->status_buf[i] = buf16[i];
221 data->status_buf[i] = buf32[i];
230 for (i = 0; i < data->chip->num_regs; i++) {
231 ret = regmap_read(map, chip->status_base +
233 * data->irq_reg_stride),
234 &data->status_buf[i]);
238 "Failed to read IRQ status: %d\n",
240 if (chip->runtime_pm)
241 pm_runtime_put(map->dev);
248 * Ignore masked IRQs and ack if we need to; we ack early so
249 * there is no race between handling and acknowleding the
250 * interrupt. We assume that typically few of the interrupts
251 * will fire simultaneously so don't worry about overhead from
252 * doing a write per register.
254 for (i = 0; i < data->chip->num_regs; i++) {
255 data->status_buf[i] &= ~data->mask_buf[i];
257 if (data->status_buf[i] && chip->ack_base) {
258 reg = chip->ack_base +
259 (i * map->reg_stride * data->irq_reg_stride);
260 ret = regmap_write(map, reg, data->status_buf[i]);
262 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
267 for (i = 0; i < chip->num_irqs; i++) {
268 if (data->status_buf[chip->irqs[i].reg_offset /
269 map->reg_stride] & chip->irqs[i].mask) {
270 handle_nested_irq(irq_find_mapping(data->domain, i));
275 if (chip->runtime_pm)
276 pm_runtime_put(map->dev);
284 static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
287 struct regmap_irq_chip_data *data = h->host_data;
289 irq_set_chip_data(virq, data);
290 irq_set_chip(virq, &data->irq_chip);
291 irq_set_nested_thread(virq, 1);
293 /* ARM needs us to explicitly flag the IRQ as valid
294 * and will set them noprobe when we do so. */
296 set_irq_flags(virq, IRQF_VALID);
298 irq_set_noprobe(virq);
304 static struct irq_domain_ops regmap_domain_ops = {
305 .map = regmap_irq_map,
306 .xlate = irq_domain_xlate_twocell,
310 * regmap_add_irq_chip(): Use standard regmap IRQ controller handling
312 * map: The regmap for the device.
313 * irq: The IRQ the device uses to signal interrupts
314 * irq_flags: The IRQF_ flags to use for the primary interrupt.
315 * chip: Configuration for the interrupt controller.
316 * data: Runtime data structure for the controller, allocated on success
318 * Returns 0 on success or an errno on failure.
320 * In order for this to be efficient the chip really should use a
321 * register cache. The chip driver is responsible for restoring the
322 * register values used by the IRQ controller over suspend and resume.
324 int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
325 int irq_base, const struct regmap_irq_chip *chip,
326 struct regmap_irq_chip_data **data)
328 struct regmap_irq_chip_data *d;
333 for (i = 0; i < chip->num_irqs; i++) {
334 if (chip->irqs[i].reg_offset % map->reg_stride)
336 if (chip->irqs[i].reg_offset / map->reg_stride >=
342 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
344 dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
350 d = kzalloc(sizeof(*d), GFP_KERNEL);
356 d->status_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
361 d->mask_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
366 d->mask_buf_def = kzalloc(sizeof(unsigned int) * chip->num_regs,
368 if (!d->mask_buf_def)
371 if (chip->wake_base) {
372 d->wake_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
378 d->irq_chip = regmap_irq_chip;
379 d->irq_chip.name = chip->name;
383 d->irq_base = irq_base;
385 if (chip->irq_reg_stride)
386 d->irq_reg_stride = chip->irq_reg_stride;
388 d->irq_reg_stride = 1;
390 if (!map->use_single_rw && map->reg_stride == 1 &&
391 d->irq_reg_stride == 1) {
392 d->status_reg_buf = kmalloc(map->format.val_bytes *
393 chip->num_regs, GFP_KERNEL);
394 if (!d->status_reg_buf)
398 mutex_init(&d->lock);
400 for (i = 0; i < chip->num_irqs; i++)
401 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
402 |= chip->irqs[i].mask;
404 /* Mask all the interrupts by default */
405 for (i = 0; i < chip->num_regs; i++) {
406 d->mask_buf[i] = d->mask_buf_def[i];
407 reg = chip->mask_base +
408 (i * map->reg_stride * d->irq_reg_stride);
409 if (chip->mask_invert)
410 ret = regmap_update_bits(map, reg,
411 d->mask_buf[i], ~d->mask_buf[i]);
413 ret = regmap_update_bits(map, reg,
414 d->mask_buf[i], d->mask_buf[i]);
416 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
422 /* Wake is disabled by default */
424 for (i = 0; i < chip->num_regs; i++) {
425 d->wake_buf[i] = d->mask_buf_def[i];
426 reg = chip->wake_base +
427 (i * map->reg_stride * d->irq_reg_stride);
429 if (chip->wake_invert)
430 ret = regmap_update_bits(map, reg,
434 ret = regmap_update_bits(map, reg,
438 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
446 d->domain = irq_domain_add_legacy(map->dev->of_node,
447 chip->num_irqs, irq_base, 0,
448 ®map_domain_ops, d);
450 d->domain = irq_domain_add_linear(map->dev->of_node,
452 ®map_domain_ops, d);
454 dev_err(map->dev, "Failed to create IRQ domain\n");
459 ret = request_threaded_irq(irq, NULL, regmap_irq_thread, irq_flags,
462 dev_err(map->dev, "Failed to request IRQ %d: %d\n", irq, ret);
469 /* Should really dispose of the domain but... */
472 kfree(d->mask_buf_def);
474 kfree(d->status_buf);
475 kfree(d->status_reg_buf);
479 EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
482 * regmap_del_irq_chip(): Stop interrupt handling for a regmap IRQ chip
484 * @irq: Primary IRQ for the device
485 * @d: regmap_irq_chip_data allocated by regmap_add_irq_chip()
487 void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
493 /* We should unmap the domain but... */
495 kfree(d->mask_buf_def);
497 kfree(d->status_reg_buf);
498 kfree(d->status_buf);
501 EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
504 * regmap_irq_chip_get_base(): Retrieve interrupt base for a regmap IRQ chip
506 * Useful for drivers to request their own IRQs.
508 * @data: regmap_irq controller to operate on.
510 int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
512 WARN_ON(!data->irq_base);
513 return data->irq_base;
515 EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
518 * regmap_irq_get_virq(): Map an interrupt on a chip to a virtual IRQ
520 * Useful for drivers to request their own IRQs.
522 * @data: regmap_irq controller to operate on.
523 * @irq: index of the interrupt requested in the chip IRQs
525 int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
527 /* Handle holes in the IRQ list */
528 if (!data->chip->irqs[irq].mask)
531 return irq_create_mapping(data->domain, irq);
533 EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
536 * regmap_irq_get_domain(): Retrieve the irq_domain for the chip
538 * Useful for drivers to request their own IRQs and for integration
539 * with subsystems. For ease of integration NULL is accepted as a
540 * domain, allowing devices to just call this even if no domain is
543 * @data: regmap_irq controller to operate on.
545 struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data)
552 EXPORT_SYMBOL_GPL(regmap_irq_get_domain);