2 * Register map access API - MMIO support
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/clk.h>
20 #include <linux/err.h>
22 #include <linux/module.h>
23 #include <linux/regmap.h>
24 #include <linux/slab.h>
26 struct regmap_mmio_context {
31 void (*reg_write)(struct regmap_mmio_context *ctx,
32 unsigned int reg, unsigned int val);
33 unsigned int (*reg_read)(struct regmap_mmio_context *ctx,
37 static int regmap_mmio_regbits_check(size_t reg_bits)
52 static int regmap_mmio_get_min_stride(size_t val_bits)
58 /* The core treats 0 as 1 */
79 static void regmap_mmio_write8(struct regmap_mmio_context *ctx,
83 writeb(val, ctx->regs + reg);
86 static void regmap_mmio_write16le(struct regmap_mmio_context *ctx,
90 writew(val, ctx->regs + reg);
93 static void regmap_mmio_write16be(struct regmap_mmio_context *ctx,
97 iowrite16be(val, ctx->regs + reg);
100 static void regmap_mmio_write32le(struct regmap_mmio_context *ctx,
104 writel(val, ctx->regs + reg);
107 static void regmap_mmio_write32be(struct regmap_mmio_context *ctx,
111 iowrite32be(val, ctx->regs + reg);
115 static void regmap_mmio_write64le(struct regmap_mmio_context *ctx,
119 writeq(val, ctx->regs + reg);
123 static int regmap_mmio_write(void *context, unsigned int reg, unsigned int val)
125 struct regmap_mmio_context *ctx = context;
128 if (!IS_ERR(ctx->clk)) {
129 ret = clk_enable(ctx->clk);
134 ctx->reg_write(ctx, reg, val);
136 if (!IS_ERR(ctx->clk))
137 clk_disable(ctx->clk);
142 static unsigned int regmap_mmio_read8(struct regmap_mmio_context *ctx,
145 return readb(ctx->regs + reg);
148 static unsigned int regmap_mmio_read16le(struct regmap_mmio_context *ctx,
151 return readw(ctx->regs + reg);
154 static unsigned int regmap_mmio_read16be(struct regmap_mmio_context *ctx,
157 return ioread16be(ctx->regs + reg);
160 static unsigned int regmap_mmio_read32le(struct regmap_mmio_context *ctx,
163 return readl(ctx->regs + reg);
166 static unsigned int regmap_mmio_read32be(struct regmap_mmio_context *ctx,
169 return ioread32be(ctx->regs + reg);
173 static unsigned int regmap_mmio_read64le(struct regmap_mmio_context *ctx,
176 return readq(ctx->regs + reg);
180 static int regmap_mmio_read(void *context, unsigned int reg, unsigned int *val)
182 struct regmap_mmio_context *ctx = context;
185 if (!IS_ERR(ctx->clk)) {
186 ret = clk_enable(ctx->clk);
191 *val = ctx->reg_read(ctx, reg);
193 if (!IS_ERR(ctx->clk))
194 clk_disable(ctx->clk);
199 static void regmap_mmio_free_context(void *context)
201 struct regmap_mmio_context *ctx = context;
203 if (!IS_ERR(ctx->clk)) {
204 clk_unprepare(ctx->clk);
210 static const struct regmap_bus regmap_mmio = {
212 .reg_write = regmap_mmio_write,
213 .reg_read = regmap_mmio_read,
214 .free_context = regmap_mmio_free_context,
217 static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
220 const struct regmap_config *config)
222 struct regmap_mmio_context *ctx;
226 ret = regmap_mmio_regbits_check(config->reg_bits);
230 if (config->pad_bits)
231 return ERR_PTR(-EINVAL);
233 min_stride = regmap_mmio_get_min_stride(config->val_bits);
235 return ERR_PTR(min_stride);
237 if (config->reg_stride < min_stride)
238 return ERR_PTR(-EINVAL);
240 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
242 return ERR_PTR(-ENOMEM);
245 ctx->val_bytes = config->val_bits / 8;
246 ctx->clk = ERR_PTR(-ENODEV);
248 switch (config->reg_format_endian) {
249 case REGMAP_ENDIAN_DEFAULT:
250 case REGMAP_ENDIAN_LITTLE:
251 #ifdef __LITTLE_ENDIAN
252 case REGMAP_ENDIAN_NATIVE:
254 switch (config->val_bits) {
256 ctx->reg_read = regmap_mmio_read8;
257 ctx->reg_write = regmap_mmio_write8;
260 ctx->reg_read = regmap_mmio_read16le;
261 ctx->reg_write = regmap_mmio_write16le;
264 ctx->reg_read = regmap_mmio_read32le;
265 ctx->reg_write = regmap_mmio_write32le;
269 ctx->reg_read = regmap_mmio_read64le;
270 ctx->reg_write = regmap_mmio_write64le;
278 case REGMAP_ENDIAN_BIG:
280 case REGMAP_ENDIAN_NATIVE:
282 switch (config->val_bits) {
284 ctx->reg_read = regmap_mmio_read8;
285 ctx->reg_write = regmap_mmio_write8;
288 ctx->reg_read = regmap_mmio_read16be;
289 ctx->reg_write = regmap_mmio_write16be;
292 ctx->reg_read = regmap_mmio_read32be;
293 ctx->reg_write = regmap_mmio_write32be;
308 ctx->clk = clk_get(dev, clk_id);
309 if (IS_ERR(ctx->clk)) {
310 ret = PTR_ERR(ctx->clk);
314 ret = clk_prepare(ctx->clk);
328 struct regmap *__regmap_init_mmio_clk(struct device *dev, const char *clk_id,
330 const struct regmap_config *config,
331 struct lock_class_key *lock_key,
332 const char *lock_name)
334 struct regmap_mmio_context *ctx;
336 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
338 return ERR_CAST(ctx);
340 return __regmap_init(dev, ®map_mmio, ctx, config,
341 lock_key, lock_name);
343 EXPORT_SYMBOL_GPL(__regmap_init_mmio_clk);
345 struct regmap *__devm_regmap_init_mmio_clk(struct device *dev,
348 const struct regmap_config *config,
349 struct lock_class_key *lock_key,
350 const char *lock_name)
352 struct regmap_mmio_context *ctx;
354 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
356 return ERR_CAST(ctx);
358 return __devm_regmap_init(dev, ®map_mmio, ctx, config,
359 lock_key, lock_name);
361 EXPORT_SYMBOL_GPL(__devm_regmap_init_mmio_clk);
363 MODULE_LICENSE("GPL v2");