2 * Broadcom specific AMBA
3 * ChipCommon core driver
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
7 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
9 * Licensed under the GNU/GPL. See COPYING for details.
12 #include "bcma_private.h"
13 #include <linux/bcm47xx_wdt.h>
14 #include <linux/export.h>
15 #include <linux/platform_device.h>
16 #include <linux/bcma/bcma.h>
18 static void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
20 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
24 value |= bcma_cc_read32(cc, offset) & ~mask;
25 bcma_cc_write32(cc, offset, value);
30 u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
32 if (cc->capabilities & BCMA_CC_CAP_PMU)
33 return bcma_pmu_get_alp_clock(cc);
37 EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
39 static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
41 struct bcma_bus *bus = cc->core->bus;
44 if (cc->capabilities & BCMA_CC_CAP_PMU) {
45 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
47 else if (cc->core->id.rev < 26)
50 nb = (cc->core->id.rev >= 37) ? 32 : 24;
60 static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
63 struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
65 return bcma_chipco_watchdog_timer_set(cc, ticks);
68 static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
71 struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
74 ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
75 return ticks / cc->ticks_per_ms;
78 static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
80 struct bcma_bus *bus = cc->core->bus;
82 if (cc->capabilities & BCMA_CC_CAP_PMU) {
83 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
84 /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP
87 return bcma_chipco_get_alp_clock(cc) / 4000;
89 /* based on 32KHz ILP clock */
92 return bcma_chipco_get_alp_clock(cc) / 1000;
96 int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
98 struct bcm47xx_wdt wdt = {};
99 struct platform_device *pdev;
101 wdt.driver_data = cc;
102 wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
103 wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
105 bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
107 pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
108 cc->core->bus->num, &wdt,
111 return PTR_ERR(pdev);
118 void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
120 struct bcma_bus *bus = cc->core->bus;
122 if (cc->early_setup_done)
125 spin_lock_init(&cc->gpio_lock);
127 if (cc->core->id.rev >= 11)
128 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
129 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
130 if (cc->core->id.rev >= 35)
131 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
133 if (cc->capabilities & BCMA_CC_CAP_PMU)
134 bcma_pmu_early_init(cc);
136 if (IS_BUILTIN(CONFIG_BCM47XX) && bus->hosttype == BCMA_HOSTTYPE_SOC)
137 bcma_chipco_serial_init(cc);
139 cc->early_setup_done = true;
142 void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
150 bcma_core_chipcommon_early_init(cc);
152 if (cc->core->id.rev >= 20) {
153 u32 pullup = 0, pulldown = 0;
155 if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
160 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
161 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
164 if (cc->capabilities & BCMA_CC_CAP_PMU)
166 if (cc->capabilities & BCMA_CC_CAP_PCTL)
167 bcma_err(cc->core->bus, "Power control not implemented!\n");
169 if (cc->core->id.rev >= 16) {
170 if (cc->core->bus->sprom.leddc_on_time &&
171 cc->core->bus->sprom.leddc_off_time) {
172 leddc_on = cc->core->bus->sprom.leddc_on_time;
173 leddc_off = cc->core->bus->sprom.leddc_off_time;
175 bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
176 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
177 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
179 cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
181 cc->setup_done = true;
184 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
185 u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
189 maxt = bcma_chipco_watchdog_get_max_timer(cc);
190 if (cc->capabilities & BCMA_CC_CAP_PMU) {
193 else if (ticks > maxt)
195 bcma_pmu_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
197 struct bcma_bus *bus = cc->core->bus;
199 if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4707 &&
200 bus->chipinfo.id != BCMA_CHIP_ID_BCM47094 &&
201 bus->chipinfo.id != BCMA_CHIP_ID_BCM53018)
202 bcma_core_set_clockmode(cc->core,
203 ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC);
208 bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
213 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
215 bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
218 u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
220 return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
223 u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
225 return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
228 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
233 spin_lock_irqsave(&cc->gpio_lock, flags);
234 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
235 spin_unlock_irqrestore(&cc->gpio_lock, flags);
239 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
241 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
246 spin_lock_irqsave(&cc->gpio_lock, flags);
247 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
248 spin_unlock_irqrestore(&cc->gpio_lock, flags);
252 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
255 * If the bit is set to 0, chipcommon controlls this GPIO,
256 * if the bit is set to 1, it is used by some part of the chip and not our code.
258 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
263 spin_lock_irqsave(&cc->gpio_lock, flags);
264 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
265 spin_unlock_irqrestore(&cc->gpio_lock, flags);
269 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
271 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
276 spin_lock_irqsave(&cc->gpio_lock, flags);
277 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
278 spin_unlock_irqrestore(&cc->gpio_lock, flags);
283 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
288 spin_lock_irqsave(&cc->gpio_lock, flags);
289 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
290 spin_unlock_irqrestore(&cc->gpio_lock, flags);
295 u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
300 if (cc->core->id.rev < 20)
303 spin_lock_irqsave(&cc->gpio_lock, flags);
304 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
305 spin_unlock_irqrestore(&cc->gpio_lock, flags);
310 u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
315 if (cc->core->id.rev < 20)
318 spin_lock_irqsave(&cc->gpio_lock, flags);
319 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
320 spin_unlock_irqrestore(&cc->gpio_lock, flags);
325 static void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
327 #if IS_BUILTIN(CONFIG_BCM47XX)
331 unsigned int ccrev = cc->core->id.rev;
332 struct bcma_serial_port *ports = cc->serial_ports;
334 if (ccrev >= 11 && ccrev != 15) {
335 baud_base = bcma_chipco_get_alp_clock(cc);
337 /* Turn off UART clock before switching clocksource. */
338 bcma_cc_write32(cc, BCMA_CC_CORECTL,
339 bcma_cc_read32(cc, BCMA_CC_CORECTL)
340 & ~BCMA_CC_CORECTL_UARTCLKEN);
342 /* Set the override bit so we don't divide it */
343 bcma_cc_write32(cc, BCMA_CC_CORECTL,
344 bcma_cc_read32(cc, BCMA_CC_CORECTL)
345 | BCMA_CC_CORECTL_UARTCLK0);
347 /* Re-enable the UART clock. */
348 bcma_cc_write32(cc, BCMA_CC_CORECTL,
349 bcma_cc_read32(cc, BCMA_CC_CORECTL)
350 | BCMA_CC_CORECTL_UARTCLKEN);
353 bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n",
358 irq = bcma_core_irq(cc->core, 0);
360 /* Determine the registers of the UARTs */
361 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
362 for (i = 0; i < cc->nr_serial_ports; i++) {
363 ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
366 ports[i].baud_base = baud_base;
367 ports[i].reg_shift = 0;
369 #endif /* CONFIG_BCM47XX */