2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * with the reference on libata and ahci drvier in kernel
31 #include <asm/processor.h>
32 #include <asm/errno.h>
37 #include <linux/ctype.h>
40 struct ahci_probe_ent *probe_ent = NULL;
41 hd_driveid_t *ataid[AHCI_MAX_PORTS];
43 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
46 * Some controllers limit number of blocks they can read/write at once.
47 * Contemporary SSD devices work much faster if the read/write size is aligned
48 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
51 #ifndef MAX_SATA_BLOCKS_READ_WRITE
52 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
55 /* Maximum timeouts for each event */
56 #define WAIT_MS_SPINUP 10000
57 #define WAIT_MS_DATAIO 5000
58 #define WAIT_MS_LINKUP 4
60 static inline u32 ahci_port_base(u32 base, u32 port)
62 return base + 0x100 + (port * 0x80);
66 static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
67 unsigned int port_idx)
69 base = ahci_port_base(base, port_idx);
71 port->cmd_addr = base;
72 port->scr_addr = base + PORT_SCR;
76 #define msleep(a) udelay(a * 1000)
78 static void ahci_dcache_flush_range(unsigned begin, unsigned len)
80 const unsigned long start = begin;
81 const unsigned long end = start + len;
83 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
84 flush_dcache_range(start, end);
88 * SATA controller DMAs to physical RAM. Ensure data from the
89 * controller is invalidated from dcache; next access comes from
92 static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)
94 const unsigned long start = begin;
95 const unsigned long end = start + len;
97 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
98 invalidate_dcache_range(start, end);
102 * Ensure data for SATA controller is flushed out of dcache and
103 * written to physical memory.
105 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
107 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
108 AHCI_PORT_PRIV_DMA_SZ);
111 static int waiting_for_cmd_completed(volatile u8 *offset,
118 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
121 return (i < timeout_msec) ? 0 : -1;
125 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
127 #ifndef CONFIG_SCSI_AHCI_PLAT
128 pci_dev_t pdev = probe_ent->dev;
130 unsigned short vendor;
132 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
133 u32 tmp, cap_save, cmd;
135 volatile u8 *port_mmio;
137 debug("ahci_host_init: start\n");
139 cap_save = readl(mmio + HOST_CAP);
140 cap_save &= ((1 << 28) | (1 << 17));
141 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
143 /* global controller reset */
144 tmp = readl(mmio + HOST_CTL);
145 if ((tmp & HOST_RESET) == 0)
146 writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
148 /* reset must complete within 1 second, or
149 * the hardware should be considered fried.
154 tmp = readl(mmio + HOST_CTL);
156 debug("controller reset failed (0x%x)\n", tmp);
159 } while (tmp & HOST_RESET);
161 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
162 writel(cap_save, mmio + HOST_CAP);
163 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
165 #ifndef CONFIG_SCSI_AHCI_PLAT
166 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
168 if (vendor == PCI_VENDOR_ID_INTEL) {
170 pci_read_config_word(pdev, 0x92, &tmp16);
172 pci_write_config_word(pdev, 0x92, tmp16);
175 probe_ent->cap = readl(mmio + HOST_CAP);
176 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
177 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
179 debug("cap 0x%x port_map 0x%x n_ports %d\n",
180 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
182 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
183 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
185 for (i = 0; i < probe_ent->n_ports; i++) {
186 probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
187 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
188 ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
190 /* make sure port is not active */
191 tmp = readl(port_mmio + PORT_CMD);
192 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
193 PORT_CMD_FIS_RX | PORT_CMD_START)) {
194 debug("Port %d is active. Deactivating.\n", i);
195 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
196 PORT_CMD_FIS_RX | PORT_CMD_START);
197 writel_with_flush(tmp, port_mmio + PORT_CMD);
199 /* spec says 500 msecs for each bit, so
200 * this is slightly incorrect.
205 /* Add the spinup command to whatever mode bits may
206 * already be on in the command register.
208 cmd = readl(port_mmio + PORT_CMD);
209 cmd |= PORT_CMD_FIS_RX;
210 cmd |= PORT_CMD_SPIN_UP;
211 writel_with_flush(cmd, port_mmio + PORT_CMD);
213 /* Bring up SATA link.
214 * SATA link bringup time is usually less than 1 ms; only very
215 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
218 while (j < WAIT_MS_LINKUP) {
219 tmp = readl(port_mmio + PORT_SCR_STAT);
220 if ((tmp & 0xf) == 0x3)
225 if (j == WAIT_MS_LINKUP) {
226 printf("SATA link %d timeout.\n", i);
229 debug("SATA link ok.\n");
232 /* Clear error status */
233 tmp = readl(port_mmio + PORT_SCR_ERR);
235 writel(tmp, port_mmio + PORT_SCR_ERR);
237 debug("Spinning up device on SATA port %d... ", i);
240 while (j < WAIT_MS_SPINUP) {
241 tmp = readl(port_mmio + PORT_TFDATA);
242 if (!(tmp & (ATA_STAT_BUSY | ATA_STAT_DRQ)))
247 printf("Target spinup took %d ms.\n", j);
248 if (j == WAIT_MS_SPINUP)
253 tmp = readl(port_mmio + PORT_SCR_ERR);
254 debug("PORT_SCR_ERR 0x%x\n", tmp);
255 writel(tmp, port_mmio + PORT_SCR_ERR);
257 /* ack any pending irq events for this port */
258 tmp = readl(port_mmio + PORT_IRQ_STAT);
259 debug("PORT_IRQ_STAT 0x%x\n", tmp);
261 writel(tmp, port_mmio + PORT_IRQ_STAT);
263 writel(1 << i, mmio + HOST_IRQ_STAT);
265 /* set irq mask (enables interrupts) */
266 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
268 /* register linkup ports */
269 tmp = readl(port_mmio + PORT_SCR_STAT);
270 debug("Port %d status: 0x%x\n", i, tmp);
271 if ((tmp & 0xf) == 0x03)
272 probe_ent->link_port_map |= (0x01 << i);
275 tmp = readl(mmio + HOST_CTL);
276 debug("HOST_CTL 0x%x\n", tmp);
277 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
278 tmp = readl(mmio + HOST_CTL);
279 debug("HOST_CTL 0x%x\n", tmp);
280 #ifndef CONFIG_SCSI_AHCI_PLAT
281 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
282 tmp |= PCI_COMMAND_MASTER;
283 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
289 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
291 #ifndef CONFIG_SCSI_AHCI_PLAT
292 pci_dev_t pdev = probe_ent->dev;
295 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
296 u32 vers, cap, cap2, impl, speed;
300 vers = readl(mmio + HOST_VERSION);
301 cap = probe_ent->cap;
302 cap2 = readl(mmio + HOST_CAP2);
303 impl = probe_ent->port_map;
305 speed = (cap >> 20) & 0xf;
315 #ifdef CONFIG_SCSI_AHCI_PLAT
318 pci_read_config_word(pdev, 0x0a, &cc);
321 else if (cc == 0x0106)
323 else if (cc == 0x0104)
328 printf("AHCI %02x%02x.%02x%02x "
329 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
334 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
340 cap & (1 << 31) ? "64bit " : "",
341 cap & (1 << 30) ? "ncq " : "",
342 cap & (1 << 28) ? "ilck " : "",
343 cap & (1 << 27) ? "stag " : "",
344 cap & (1 << 26) ? "pm " : "",
345 cap & (1 << 25) ? "led " : "",
346 cap & (1 << 24) ? "clo " : "",
347 cap & (1 << 19) ? "nz " : "",
348 cap & (1 << 18) ? "only " : "",
349 cap & (1 << 17) ? "pmp " : "",
350 cap & (1 << 16) ? "fbss " : "",
351 cap & (1 << 15) ? "pio " : "",
352 cap & (1 << 14) ? "slum " : "",
353 cap & (1 << 13) ? "part " : "",
354 cap & (1 << 7) ? "ccc " : "",
355 cap & (1 << 6) ? "ems " : "",
356 cap & (1 << 5) ? "sxs " : "",
357 cap2 & (1 << 2) ? "apst " : "",
358 cap2 & (1 << 1) ? "nvmp " : "",
359 cap2 & (1 << 0) ? "boh " : "");
362 #ifndef CONFIG_SCSI_AHCI_PLAT
363 static int ahci_init_one(pci_dev_t pdev)
368 memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
370 probe_ent = malloc(sizeof(struct ahci_probe_ent));
371 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
372 probe_ent->dev = pdev;
374 probe_ent->host_flags = ATA_FLAG_SATA
379 probe_ent->pio_mask = 0x1f;
380 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
382 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
383 debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
386 * JMicron-specific fixup:
387 * make sure we're in AHCI mode
389 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
390 if (vendor == 0x197b)
391 pci_write_config_byte(pdev, 0x41, 0xa1);
393 /* initialize adapter */
394 rc = ahci_host_init(probe_ent);
398 ahci_print_info(probe_ent);
407 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
409 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
411 struct ahci_ioports *pp = &(probe_ent->port[port]);
412 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
416 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
417 if (sg_count > AHCI_MAX_SG) {
418 printf("Error:Too much sg!\n");
422 for (i = 0; i < sg_count; i++) {
424 cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
425 ahci_sg->addr_hi = 0;
426 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
427 (buf_len < MAX_DATA_BYTE_COUNT
429 : (MAX_DATA_BYTE_COUNT - 1)));
431 buf_len -= MAX_DATA_BYTE_COUNT;
438 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
440 pp->cmd_slot->opts = cpu_to_le32(opts);
441 pp->cmd_slot->status = 0;
442 pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
443 pp->cmd_slot->tbl_addr_hi = 0;
447 #ifdef CONFIG_AHCI_SETFEATURES_XFER
448 static void ahci_set_feature(u8 port)
450 struct ahci_ioports *pp = &(probe_ent->port[port]);
451 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
452 u32 cmd_fis_len = 5; /* five dwords */
456 memset(fis, 0, sizeof(fis));
459 fis[2] = ATA_CMD_SETF;
460 fis[3] = SETFEATURES_XFER;
461 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
463 memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis));
464 ahci_fill_cmd_slot(pp, cmd_fis_len);
465 ahci_dcache_flush_sata_cmd(pp);
466 writel(1, port_mmio + PORT_CMD_ISSUE);
467 readl(port_mmio + PORT_CMD_ISSUE);
469 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
470 WAIT_MS_DATAIO, 0x1)) {
471 printf("set feature error on port %d!\n", port);
477 static int ahci_port_start(u8 port)
479 struct ahci_ioports *pp = &(probe_ent->port[port]);
480 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
484 debug("Enter start port: %d\n", port);
485 port_status = readl(port_mmio + PORT_SCR_STAT);
486 debug("Port %d status: %x\n", port, port_status);
487 if ((port_status & 0xf) != 0x03) {
488 printf("No Link on this port!\n");
492 mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
495 printf("No mem for table!\n");
499 mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
500 memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
503 * First item in chunk of DMA memory: 32-slot command table,
504 * 32 bytes each in size
507 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
508 debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);
509 mem += (AHCI_CMD_SLOT_SZ + 224);
512 * Second item: Received-FIS area
514 pp->rx_fis = virt_to_phys((void *)mem);
515 mem += AHCI_RX_FIS_SZ;
518 * Third item: data area for storing a single command
519 * and its scatter-gather table
521 pp->cmd_tbl = virt_to_phys((void *)mem);
522 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
524 mem += AHCI_CMD_TBL_HDR;
526 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
528 writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
530 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
532 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
533 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
534 PORT_CMD_START, port_mmio + PORT_CMD);
536 debug("Exit start port %d\n", port);
542 static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,
543 int buf_len, u8 is_write)
546 struct ahci_ioports *pp = &(probe_ent->port[port]);
547 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
552 debug("Enter %s: for port %d\n", __func__, port);
554 if (port > probe_ent->n_ports) {
555 printf("Invalid port number %d\n", port);
559 port_status = readl(port_mmio + PORT_SCR_STAT);
560 if ((port_status & 0xf) != 0x03) {
561 debug("No Link on port %d!\n", port);
565 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
567 sg_count = ahci_fill_sg(port, buf, buf_len);
568 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
569 ahci_fill_cmd_slot(pp, opts);
571 ahci_dcache_flush_sata_cmd(pp);
572 ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len);
574 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
576 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
577 WAIT_MS_DATAIO, 0x1)) {
578 printf("timeout exit!\n");
582 ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len);
583 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
589 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
592 for (i = 0; i < len / 2; i++)
593 target[i] = swab16(src[i]);
594 return (char *)target;
598 static void dump_ataid(hd_driveid_t *ataid)
600 debug("(49)ataid->capability = 0x%x\n", ataid->capability);
601 debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
602 debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
603 debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
604 debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
605 debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
606 debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
607 debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
608 debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
609 debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
610 debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
611 debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
612 debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
613 debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
614 debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
619 * SCSI INQUIRY command operation.
621 static int ata_scsiop_inquiry(ccb *pccb)
626 0x5, /* claim SPC-3 version compatibility */
634 /* Clean ccb data buffer */
635 memset(pccb->pdata, 0, pccb->datalen);
637 memcpy(pccb->pdata, hdr, sizeof(hdr));
639 if (pccb->datalen <= 35)
642 memset(fis, 0, sizeof(fis));
643 /* Construct the FIS */
644 fis[0] = 0x27; /* Host to device FIS. */
645 fis[1] = 1 << 7; /* Command FIS. */
646 fis[2] = ATA_CMD_IDENT; /* Command byte. */
648 /* Read id from sata */
650 if (!(tmpid = malloc(sizeof(hd_driveid_t))))
653 if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), tmpid,
654 sizeof(hd_driveid_t), 0)) {
655 debug("scsi_ahci: SCSI inquiry command failure.\n");
661 ataid[port] = (hd_driveid_t *) tmpid;
663 memcpy(&pccb->pdata[8], "ATA ", 8);
664 ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
665 ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
667 dump_ataid(ataid[port]);
673 * SCSI READ10/WRITE10 command operation.
675 static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
680 u8 *user_buffer = pccb->pdata;
681 u32 user_buffer_size = pccb->datalen;
683 /* Retrieve the base LBA number from the ccb structure. */
684 memcpy(&lba, pccb->cmd + 2, sizeof(lba));
685 lba = be32_to_cpu(lba);
688 * And the number of blocks.
690 * For 10-byte and 16-byte SCSI R/W commands, transfer
691 * length 0 means transfer 0 block of data.
692 * However, for ATA R/W commands, sector count 0 means
693 * 256 or 65536 sectors, not 0 sectors as in SCSI.
695 * WARNING: one or two older ATA drives treat 0 as 0...
697 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
699 debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
700 is_write ? "write" : "read", (unsigned)lba, blocks);
703 memset(fis, 0, sizeof(fis));
704 fis[0] = 0x27; /* Host to device FIS. */
705 fis[1] = 1 << 7; /* Command FIS. */
706 /* Command byte (read/write). */
707 fis[2] = is_write ? ATA_CMD_WR_DMA : ATA_CMD_RD_DMA;
710 u16 now_blocks; /* number of blocks per iteration */
711 u32 transfer_size; /* number of bytes per iteration */
713 now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);
715 transfer_size = ATA_BLOCKSIZE * now_blocks;
716 if (transfer_size > user_buffer_size) {
717 printf("scsi_ahci: Error: buffer too small.\n");
721 /* LBA address, only support LBA28 in this driver */
722 fis[4] = (lba >> 0) & 0xff;
723 fis[5] = (lba >> 8) & 0xff;
724 fis[6] = (lba >> 16) & 0xff;
725 fis[7] = ((lba >> 24) & 0xf) | 0xe0;
727 /* Block (sector) count */
728 fis[12] = (now_blocks >> 0) & 0xff;
729 fis[13] = (now_blocks >> 8) & 0xff;
731 /* Read/Write from ahci */
732 if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
733 user_buffer, user_buffer_size,
735 debug("scsi_ahci: SCSI %s10 command failure.\n",
736 is_write ? "WRITE" : "READ");
739 user_buffer += transfer_size;
740 user_buffer_size -= transfer_size;
741 blocks -= now_blocks;
750 * SCSI READ CAPACITY10 command operation.
752 static int ata_scsiop_read_capacity10(ccb *pccb)
757 if (!ataid[pccb->target]) {
758 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
760 "\tPlease run SCSI commmand INQUIRY firstly!\n");
764 cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
765 if (cap == 0xfffffff) {
766 unsigned short *cap48 = ataid[pccb->target]->lba48_capacity;
767 if (cap48[2] || cap48[3]) {
770 cap = (le16_to_cpu(cap48[1]) << 16) |
771 (le16_to_cpu(cap48[0]));
775 cap = cpu_to_be32(cap);
776 memcpy(pccb->pdata, &cap, sizeof(cap));
778 block_size = cpu_to_be32((u32)512);
779 memcpy(&pccb->pdata[4], &block_size, 4);
786 * SCSI READ CAPACITY16 command operation.
788 static int ata_scsiop_read_capacity16(ccb *pccb)
793 if (!ataid[pccb->target]) {
794 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
796 "\tPlease run SCSI commmand INQUIRY firstly!\n");
800 cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
801 if (cap == 0xfffffff) {
802 memcpy(&cap, ataid[pccb->target]->lba48_capacity, sizeof(cap));
803 cap = le64_to_cpu(cap);
806 cap = cpu_to_be64(cap);
807 memcpy(pccb->pdata, &cap, sizeof(cap));
809 block_size = cpu_to_be64((u64)512);
810 memcpy(&pccb->pdata[8], &block_size, 8);
817 * SCSI TEST UNIT READY command operation.
819 static int ata_scsiop_test_unit_ready(ccb *pccb)
821 return (ataid[pccb->target]) ? 0 : -EPERM;
825 int scsi_exec(ccb *pccb)
829 switch (pccb->cmd[0]) {
831 ret = ata_scsiop_read_write(pccb, 0);
834 ret = ata_scsiop_read_write(pccb, 1);
836 case SCSI_RD_CAPAC10:
837 ret = ata_scsiop_read_capacity10(pccb);
839 case SCSI_RD_CAPAC16:
840 ret = ata_scsiop_read_capacity16(pccb);
843 ret = ata_scsiop_test_unit_ready(pccb);
846 ret = ata_scsiop_inquiry(pccb);
849 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
854 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
862 void scsi_low_level_init(int busdevfunc)
867 #ifndef CONFIG_SCSI_AHCI_PLAT
868 ahci_init_one(busdevfunc);
871 linkmap = probe_ent->link_port_map;
873 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
874 if (((linkmap >> i) & 0x01)) {
875 if (ahci_port_start((u8) i)) {
876 printf("Can not start port %d\n", i);
879 #ifdef CONFIG_AHCI_SETFEATURES_XFER
880 ahci_set_feature((u8) i);
886 #ifdef CONFIG_SCSI_AHCI_PLAT
887 int ahci_init(u32 base)
892 memset(ataid, 0, sizeof(ataid));
894 probe_ent = malloc(sizeof(struct ahci_probe_ent));
895 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
897 probe_ent->host_flags = ATA_FLAG_SATA
902 probe_ent->pio_mask = 0x1f;
903 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
905 probe_ent->mmio_base = base;
907 /* initialize adapter */
908 rc = ahci_host_init(probe_ent);
912 ahci_print_info(probe_ent);
914 linkmap = probe_ent->link_port_map;
916 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
917 if (((linkmap >> i) & 0x01)) {
918 if (ahci_port_start((u8) i)) {
919 printf("Can not start port %d\n", i);
922 #ifdef CONFIG_AHCI_SETFEATURES_XFER
923 ahci_set_feature((u8) i);
932 void scsi_bus_reset(void)
938 void scsi_print_error(ccb * pccb)
940 /*The ahci error info can be read in the ahci driver*/