2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/blkdev.h>
22 #include <linux/errno.h>
24 #include <linux/genhd.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/kdev_t.h>
29 #include <linux/kthread.h>
30 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/pci.h>
35 #include <linux/poison.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
38 #include <linux/types.h>
39 #include <linux/version.h>
41 #define NVME_Q_DEPTH 1024
42 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
43 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
44 #define NVME_MINORS 64
45 #define IO_TIMEOUT (5 * HZ)
46 #define ADMIN_TIMEOUT (60 * HZ)
48 static int nvme_major;
49 module_param(nvme_major, int, 0);
51 static int use_threaded_interrupts;
52 module_param(use_threaded_interrupts, int, 0);
54 static DEFINE_SPINLOCK(dev_list_lock);
55 static LIST_HEAD(dev_list);
56 static struct task_struct *nvme_thread;
59 * Represents an NVM Express device. Each nvme_dev is a PCI function.
62 struct list_head node;
63 struct nvme_queue **queues;
65 struct pci_dev *pci_dev;
66 struct dma_pool *prp_page_pool;
67 struct dma_pool *prp_small_pool;
71 struct msix_entry *entry;
72 struct nvme_bar __iomem *bar;
73 struct list_head namespaces;
80 * An NVM Express namespace is equivalent to a SCSI LUN
83 struct list_head list;
86 struct request_queue *queue;
94 * An NVM Express queue. Each device has at least two (one for admin
95 * commands and one for I/O commands).
98 struct device *q_dmadev;
101 struct nvme_command *sq_cmds;
102 volatile struct nvme_completion *cqes;
103 dma_addr_t sq_dma_addr;
104 dma_addr_t cq_dma_addr;
105 wait_queue_head_t sq_full;
106 wait_queue_t sq_cong_wait;
107 struct bio_list sq_cong;
115 unsigned long cmdid_data[];
119 * Check we didin't inadvertently grow the command struct
121 static inline void _nvme_check_size(void)
123 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
124 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
125 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
126 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
130 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
131 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
134 struct nvme_cmd_info {
136 unsigned long timeout;
139 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
141 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
145 * alloc_cmdid() - Allocate a Command ID
146 * @nvmeq: The queue that will be used for this command
147 * @ctx: A pointer that will be passed to the handler
148 * @handler: The ID of the handler to call
150 * Allocate a Command ID for a queue. The data passed in will
151 * be passed to the completion handler. This is implemented by using
152 * the bottom two bits of the ctx pointer to store the handler ID.
153 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
154 * We can change this if it becomes a problem.
156 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
159 int depth = nvmeq->q_depth - 1;
160 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
163 BUG_ON((unsigned long)ctx & 3);
166 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
169 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
171 info[cmdid].ctx = (unsigned long)ctx | handler;
172 info[cmdid].timeout = jiffies + timeout;
176 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
177 int handler, unsigned timeout)
180 wait_event_killable(nvmeq->sq_full,
181 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
182 return (cmdid < 0) ? -EINTR : cmdid;
186 * If you need more than four handlers, you'll need to change how
187 * alloc_cmdid and nvme_process_cq work. Consider using a special
188 * CMD_CTX value instead, if that works for your situation.
191 sync_completion_id = 0,
195 /* Special values must be a multiple of 4, and less than 0x1000 */
196 #define CMD_CTX_BASE (POISON_POINTER_DELTA + sync_completion_id)
197 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
198 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
199 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
200 #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
202 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
205 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
207 if (cmdid >= nvmeq->q_depth)
208 return CMD_CTX_INVALID;
209 data = info[cmdid].ctx;
210 info[cmdid].ctx = CMD_CTX_COMPLETED;
211 clear_bit(cmdid, nvmeq->cmdid_data);
212 wake_up(&nvmeq->sq_full);
216 static unsigned long cancel_cmdid(struct nvme_queue *nvmeq, int cmdid)
219 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
220 data = info[cmdid].ctx;
221 info[cmdid].ctx = CMD_CTX_CANCELLED;
225 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
227 return ns->dev->queues[get_cpu() + 1];
230 static void put_nvmeq(struct nvme_queue *nvmeq)
236 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
237 * @nvmeq: The queue to use
238 * @cmd: The command to send
240 * Safe to use from interrupt context
242 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
246 spin_lock_irqsave(&nvmeq->q_lock, flags);
247 tail = nvmeq->sq_tail;
248 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
249 if (++tail == nvmeq->q_depth)
251 writel(tail, nvmeq->q_db);
252 nvmeq->sq_tail = tail;
253 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
260 dma_addr_t first_dma;
264 static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
266 const int last_prp = PAGE_SIZE / 8 - 1;
273 prp_dma = prps->first_dma;
275 if (prps->npages == 0)
276 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
277 for (i = 0; i < prps->npages; i++) {
278 __le64 *prp_list = prps->list[i];
279 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
280 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
281 prp_dma = next_prp_dma;
289 struct nvme_prps *prps;
290 struct scatterlist sg[0];
293 /* XXX: use a mempool */
294 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
296 return kzalloc(sizeof(struct nvme_bio) +
297 sizeof(struct scatterlist) * nseg, gfp);
300 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
302 nvme_free_prps(nvmeq->dev, nbio->prps);
306 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
307 struct nvme_completion *cqe)
309 struct nvme_bio *nbio = ctx;
310 struct bio *bio = nbio->bio;
311 u16 status = le16_to_cpup(&cqe->status) >> 1;
313 dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
314 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
315 free_nbio(nvmeq, nbio);
317 bio_endio(bio, -EIO);
318 } else if (bio->bi_vcnt > bio->bi_idx) {
319 bio_list_add(&nvmeq->sq_cong, bio);
320 wake_up_process(nvme_thread);
326 /* length is in bytes */
327 static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
328 struct nvme_common_command *cmd,
329 struct scatterlist *sg, int length)
331 struct dma_pool *pool;
332 int dma_len = sg_dma_len(sg);
333 u64 dma_addr = sg_dma_address(sg);
334 int offset = offset_in_page(dma_addr);
337 int nprps, npages, i, prp_page;
338 struct nvme_prps *prps = NULL;
340 cmd->prp1 = cpu_to_le64(dma_addr);
341 length -= (PAGE_SIZE - offset);
345 dma_len -= (PAGE_SIZE - offset);
347 dma_addr += (PAGE_SIZE - offset);
350 dma_addr = sg_dma_address(sg);
351 dma_len = sg_dma_len(sg);
354 if (length <= PAGE_SIZE) {
355 cmd->prp2 = cpu_to_le64(dma_addr);
359 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
360 npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
361 prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
363 if (nprps <= (256 / 8)) {
364 pool = dev->prp_small_pool;
367 pool = dev->prp_page_pool;
368 prps->npages = npages;
371 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
372 prps->list[prp_page++] = prp_list;
373 prps->first_dma = prp_dma;
374 cmd->prp2 = cpu_to_le64(prp_dma);
377 if (i == PAGE_SIZE / 8) {
378 __le64 *old_prp_list = prp_list;
379 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
380 prps->list[prp_page++] = prp_list;
381 prp_list[0] = old_prp_list[i - 1];
382 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
385 prp_list[i++] = cpu_to_le64(dma_addr);
386 dma_len -= PAGE_SIZE;
387 dma_addr += PAGE_SIZE;
395 dma_addr = sg_dma_address(sg);
396 dma_len = sg_dma_len(sg);
402 /* NVMe scatterlists require no holes in the virtual address */
403 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
404 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
406 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
407 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
409 struct bio_vec *bvec, *bvprv = NULL;
410 struct scatterlist *sg = NULL;
411 int i, old_idx, length = 0, nsegs = 0;
413 sg_init_table(nbio->sg, psegs);
414 old_idx = bio->bi_idx;
415 bio_for_each_segment(bvec, bio, i) {
416 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
417 sg->length += bvec->bv_len;
419 if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
421 sg = sg ? sg + 1 : nbio->sg;
422 sg_set_page(sg, bvec->bv_page, bvec->bv_len,
426 length += bvec->bv_len;
432 if (dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir) == 0) {
433 bio->bi_idx = old_idx;
439 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
442 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
444 memset(cmnd, 0, sizeof(*cmnd));
445 cmnd->common.opcode = nvme_cmd_flush;
446 cmnd->common.command_id = cmdid;
447 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
449 if (++nvmeq->sq_tail == nvmeq->q_depth)
451 writel(nvmeq->sq_tail, nvmeq->q_db);
456 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
458 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
459 sync_completion_id, IO_TIMEOUT);
460 if (unlikely(cmdid < 0))
463 return nvme_submit_flush(nvmeq, ns, cmdid);
466 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
469 struct nvme_command *cmnd;
470 struct nvme_bio *nbio;
471 enum dma_data_direction dma_dir;
472 int cmdid, length, result = -ENOMEM;
475 int psegs = bio_phys_segments(ns->queue, bio);
477 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
478 result = nvme_submit_flush_data(nvmeq, ns);
483 nbio = alloc_nbio(psegs, GFP_ATOMIC);
489 cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
490 if (unlikely(cmdid < 0))
493 if ((bio->bi_rw & REQ_FLUSH) && !psegs)
494 return nvme_submit_flush(nvmeq, ns, cmdid);
497 if (bio->bi_rw & REQ_FUA)
498 control |= NVME_RW_FUA;
499 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
500 control |= NVME_RW_LR;
503 if (bio->bi_rw & REQ_RAHEAD)
504 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
506 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
508 memset(cmnd, 0, sizeof(*cmnd));
509 if (bio_data_dir(bio)) {
510 cmnd->rw.opcode = nvme_cmd_write;
511 dma_dir = DMA_TO_DEVICE;
513 cmnd->rw.opcode = nvme_cmd_read;
514 dma_dir = DMA_FROM_DEVICE;
517 result = nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
522 cmnd->rw.command_id = cmdid;
523 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
524 nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
526 cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
527 cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
528 cmnd->rw.control = cpu_to_le16(control);
529 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
531 bio->bi_sector += length >> 9;
533 if (++nvmeq->sq_tail == nvmeq->q_depth)
535 writel(nvmeq->sq_tail, nvmeq->q_db);
540 free_nbio(nvmeq, nbio);
546 * NB: return value of non-zero would mean that we were a stacking driver.
547 * make_request must always succeed.
549 static int nvme_make_request(struct request_queue *q, struct bio *bio)
551 struct nvme_ns *ns = q->queuedata;
552 struct nvme_queue *nvmeq = get_nvmeq(ns);
555 spin_lock_irq(&nvmeq->q_lock);
556 if (bio_list_empty(&nvmeq->sq_cong))
557 result = nvme_submit_bio_queue(nvmeq, ns, bio);
558 if (unlikely(result)) {
559 if (bio_list_empty(&nvmeq->sq_cong))
560 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
561 bio_list_add(&nvmeq->sq_cong, bio);
564 spin_unlock_irq(&nvmeq->q_lock);
570 struct sync_cmd_info {
571 struct task_struct *task;
576 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
577 struct nvme_completion *cqe)
579 struct sync_cmd_info *cmdinfo = ctx;
580 if (unlikely((unsigned long)cmdinfo == CMD_CTX_CANCELLED))
582 if ((unsigned long)cmdinfo == CMD_CTX_FLUSH)
584 if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
585 dev_warn(nvmeq->q_dmadev,
586 "completed id %d twice on queue %d\n",
587 cqe->command_id, le16_to_cpup(&cqe->sq_id));
590 if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
591 dev_warn(nvmeq->q_dmadev,
592 "invalid id %d completed on queue %d\n",
593 cqe->command_id, le16_to_cpup(&cqe->sq_id));
596 cmdinfo->result = le32_to_cpup(&cqe->result);
597 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
598 wake_up_process(cmdinfo->task);
601 typedef void (*completion_fn)(struct nvme_queue *, void *,
602 struct nvme_completion *);
604 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
608 static const completion_fn completions[4] = {
609 [sync_completion_id] = sync_completion,
610 [bio_completion_id] = bio_completion,
613 head = nvmeq->cq_head;
614 phase = nvmeq->cq_phase;
619 unsigned char handler;
620 struct nvme_completion cqe = nvmeq->cqes[head];
621 if ((le16_to_cpu(cqe.status) & 1) != phase)
623 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
624 if (++head == nvmeq->q_depth) {
629 data = free_cmdid(nvmeq, cqe.command_id);
631 ptr = (void *)(data & ~3UL);
632 completions[handler](nvmeq, ptr, &cqe);
635 /* If the controller ignores the cq head doorbell and continuously
636 * writes to the queue, it is theoretically possible to wrap around
637 * the queue twice and mistakenly return IRQ_NONE. Linux only
638 * requires that 0.1% of your interrupts are handled, so this isn't
641 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
644 writel(head, nvmeq->q_db + 1);
645 nvmeq->cq_head = head;
646 nvmeq->cq_phase = phase;
651 static irqreturn_t nvme_irq(int irq, void *data)
654 struct nvme_queue *nvmeq = data;
655 spin_lock(&nvmeq->q_lock);
656 result = nvme_process_cq(nvmeq);
657 spin_unlock(&nvmeq->q_lock);
661 static irqreturn_t nvme_irq_check(int irq, void *data)
663 struct nvme_queue *nvmeq = data;
664 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
665 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
667 return IRQ_WAKE_THREAD;
670 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
672 spin_lock_irq(&nvmeq->q_lock);
673 cancel_cmdid(nvmeq, cmdid);
674 spin_unlock_irq(&nvmeq->q_lock);
678 * Returns 0 on success. If the result is negative, it's a Linux error code;
679 * if the result is positive, it's an NVM Express status code
681 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
682 struct nvme_command *cmd, u32 *result, unsigned timeout)
685 struct sync_cmd_info cmdinfo;
687 cmdinfo.task = current;
688 cmdinfo.status = -EINTR;
690 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
694 cmd->common.command_id = cmdid;
696 set_current_state(TASK_KILLABLE);
697 nvme_submit_cmd(nvmeq, cmd);
700 if (cmdinfo.status == -EINTR) {
701 nvme_abort_command(nvmeq, cmdid);
706 *result = cmdinfo.result;
708 return cmdinfo.status;
711 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
714 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
717 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
720 struct nvme_command c;
722 memset(&c, 0, sizeof(c));
723 c.delete_queue.opcode = opcode;
724 c.delete_queue.qid = cpu_to_le16(id);
726 status = nvme_submit_admin_cmd(dev, &c, NULL);
732 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
733 struct nvme_queue *nvmeq)
736 struct nvme_command c;
737 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
739 memset(&c, 0, sizeof(c));
740 c.create_cq.opcode = nvme_admin_create_cq;
741 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
742 c.create_cq.cqid = cpu_to_le16(qid);
743 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
744 c.create_cq.cq_flags = cpu_to_le16(flags);
745 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
747 status = nvme_submit_admin_cmd(dev, &c, NULL);
753 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
754 struct nvme_queue *nvmeq)
757 struct nvme_command c;
758 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
760 memset(&c, 0, sizeof(c));
761 c.create_sq.opcode = nvme_admin_create_sq;
762 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
763 c.create_sq.sqid = cpu_to_le16(qid);
764 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
765 c.create_sq.sq_flags = cpu_to_le16(flags);
766 c.create_sq.cqid = cpu_to_le16(qid);
768 status = nvme_submit_admin_cmd(dev, &c, NULL);
774 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
776 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
779 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
781 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
784 static void nvme_free_queue(struct nvme_dev *dev, int qid)
786 struct nvme_queue *nvmeq = dev->queues[qid];
787 int vector = dev->entry[nvmeq->cq_vector].vector;
789 irq_set_affinity_hint(vector, NULL);
790 free_irq(vector, nvmeq);
792 /* Don't tell the adapter to delete the admin queue */
794 adapter_delete_sq(dev, qid);
795 adapter_delete_cq(dev, qid);
798 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
799 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
800 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
801 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
805 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
806 int depth, int vector)
808 struct device *dmadev = &dev->pci_dev->dev;
809 unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
810 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
814 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
815 &nvmeq->cq_dma_addr, GFP_KERNEL);
818 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
820 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
821 &nvmeq->sq_dma_addr, GFP_KERNEL);
825 nvmeq->q_dmadev = dmadev;
827 spin_lock_init(&nvmeq->q_lock);
830 init_waitqueue_head(&nvmeq->sq_full);
831 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
832 bio_list_init(&nvmeq->sq_cong);
833 nvmeq->q_db = &dev->dbs[qid * 2];
834 nvmeq->q_depth = depth;
835 nvmeq->cq_vector = vector;
840 dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
847 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
850 if (use_threaded_interrupts)
851 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
852 nvme_irq_check, nvme_irq,
853 IRQF_DISABLED | IRQF_SHARED,
855 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
856 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
859 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
860 int qid, int cq_size, int vector)
863 struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
868 result = adapter_alloc_cq(dev, qid, nvmeq);
872 result = adapter_alloc_sq(dev, qid, nvmeq);
876 result = queue_request_irq(dev, nvmeq, "nvme");
883 adapter_delete_sq(dev, qid);
885 adapter_delete_cq(dev, qid);
887 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
888 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
889 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
890 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
895 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
900 unsigned long timeout;
901 struct nvme_queue *nvmeq;
903 dev->dbs = ((void __iomem *)dev->bar) + 4096;
905 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
909 aqa = nvmeq->q_depth - 1;
912 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
913 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
914 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
915 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
917 writel(0, &dev->bar->cc);
918 writel(aqa, &dev->bar->aqa);
919 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
920 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
921 writel(dev->ctrl_config, &dev->bar->cc);
923 cap = readq(&dev->bar->cap);
924 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
926 while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
928 if (fatal_signal_pending(current))
930 if (time_after(jiffies, timeout)) {
931 dev_err(&dev->pci_dev->dev,
932 "Device not ready; aborting initialisation\n");
937 result = queue_request_irq(dev, nvmeq, "nvme admin");
938 dev->queues[0] = nvmeq;
942 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
943 unsigned long addr, unsigned length,
944 struct scatterlist **sgp)
946 int i, err, count, nents, offset;
947 struct scatterlist *sg;
955 offset = offset_in_page(addr);
956 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
957 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
959 err = get_user_pages_fast(addr, count, 1, pages);
966 sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
967 sg_init_table(sg, count);
968 sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
969 length -= (PAGE_SIZE - offset);
970 for (i = 1; i < count; i++) {
971 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
976 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
977 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
986 for (i = 0; i < count; i++)
992 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
993 unsigned long addr, int length,
994 struct scatterlist *sg, int nents)
998 count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
999 dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
1001 for (i = 0; i < count; i++)
1002 put_page(sg_page(&sg[i]));
1005 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
1006 unsigned long addr, unsigned length,
1007 struct nvme_command *cmd)
1010 struct scatterlist *sg;
1011 struct nvme_prps *prps;
1013 nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
1016 prps = nvme_setup_prps(dev, &cmd->common, sg, length);
1017 err = nvme_submit_admin_cmd(dev, cmd, NULL);
1018 nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
1019 nvme_free_prps(dev, prps);
1020 return err ? -EIO : 0;
1023 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
1025 struct nvme_command c;
1027 memset(&c, 0, sizeof(c));
1028 c.identify.opcode = nvme_admin_identify;
1029 c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
1030 c.identify.cns = cpu_to_le32(cns);
1032 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1035 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
1037 struct nvme_command c;
1039 memset(&c, 0, sizeof(c));
1040 c.features.opcode = nvme_admin_get_features;
1041 c.features.nsid = cpu_to_le32(ns->ns_id);
1042 c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1044 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1047 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1049 struct nvme_dev *dev = ns->dev;
1050 struct nvme_queue *nvmeq;
1051 struct nvme_user_io io;
1052 struct nvme_command c;
1055 struct scatterlist *sg;
1056 struct nvme_prps *prps;
1058 if (copy_from_user(&io, uio, sizeof(io)))
1060 length = (io.nblocks + 1) << ns->lba_shift;
1062 switch (io.opcode) {
1063 case nvme_cmd_write:
1065 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr,
1074 memset(&c, 0, sizeof(c));
1075 c.rw.opcode = io.opcode;
1076 c.rw.flags = io.flags;
1077 c.rw.nsid = cpu_to_le32(ns->ns_id);
1078 c.rw.slba = cpu_to_le64(io.slba);
1079 c.rw.length = cpu_to_le16(io.nblocks);
1080 c.rw.control = cpu_to_le16(io.control);
1081 c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1082 c.rw.reftag = io.reftag;
1083 c.rw.apptag = io.apptag;
1084 c.rw.appmask = io.appmask;
1086 prps = nvme_setup_prps(dev, &c.common, sg, length);
1088 nvmeq = get_nvmeq(ns);
1090 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1091 * disabled. We may be preempted at any point, and be rescheduled
1092 * to a different CPU. That will cause cacheline bouncing, but no
1093 * additional races since q_lock already protects against other CPUs.
1096 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, IO_TIMEOUT);
1098 nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
1099 nvme_free_prps(dev, prps);
1103 static int nvme_download_firmware(struct nvme_ns *ns,
1104 struct nvme_dlfw __user *udlfw)
1106 struct nvme_dev *dev = ns->dev;
1107 struct nvme_dlfw dlfw;
1108 struct nvme_command c;
1110 struct scatterlist *sg;
1111 struct nvme_prps *prps;
1113 if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1115 if (dlfw.length >= (1 << 30))
1118 nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1122 memset(&c, 0, sizeof(c));
1123 c.dlfw.opcode = nvme_admin_download_fw;
1124 c.dlfw.numd = cpu_to_le32(dlfw.length);
1125 c.dlfw.offset = cpu_to_le32(dlfw.offset);
1126 prps = nvme_setup_prps(dev, &c.common, sg, dlfw.length * 4);
1128 status = nvme_submit_admin_cmd(dev, &c, NULL);
1129 nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
1130 nvme_free_prps(dev, prps);
1134 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1136 struct nvme_dev *dev = ns->dev;
1137 struct nvme_command c;
1139 memset(&c, 0, sizeof(c));
1140 c.common.opcode = nvme_admin_activate_fw;
1141 c.common.rsvd10[0] = cpu_to_le32(arg);
1143 return nvme_submit_admin_cmd(dev, &c, NULL);
1146 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1149 struct nvme_ns *ns = bdev->bd_disk->private_data;
1152 case NVME_IOCTL_IDENTIFY_NS:
1153 return nvme_identify(ns, arg, 0);
1154 case NVME_IOCTL_IDENTIFY_CTRL:
1155 return nvme_identify(ns, arg, 1);
1156 case NVME_IOCTL_GET_RANGE_TYPE:
1157 return nvme_get_range_type(ns, arg);
1158 case NVME_IOCTL_SUBMIT_IO:
1159 return nvme_submit_io(ns, (void __user *)arg);
1160 case NVME_IOCTL_DOWNLOAD_FW:
1161 return nvme_download_firmware(ns, (void __user *)arg);
1162 case NVME_IOCTL_ACTIVATE_FW:
1163 return nvme_activate_firmware(ns, arg);
1169 static const struct block_device_operations nvme_fops = {
1170 .owner = THIS_MODULE,
1171 .ioctl = nvme_ioctl,
1172 .compat_ioctl = nvme_ioctl,
1175 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1177 while (bio_list_peek(&nvmeq->sq_cong)) {
1178 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1179 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1180 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1181 bio_list_add_head(&nvmeq->sq_cong, bio);
1184 if (bio_list_empty(&nvmeq->sq_cong))
1185 remove_wait_queue(&nvmeq->sq_full,
1186 &nvmeq->sq_cong_wait);
1190 static int nvme_kthread(void *data)
1192 struct nvme_dev *dev;
1194 while (!kthread_should_stop()) {
1195 __set_current_state(TASK_RUNNING);
1196 spin_lock(&dev_list_lock);
1197 list_for_each_entry(dev, &dev_list, node) {
1199 for (i = 0; i < dev->queue_count; i++) {
1200 struct nvme_queue *nvmeq = dev->queues[i];
1203 spin_lock_irq(&nvmeq->q_lock);
1204 if (nvme_process_cq(nvmeq))
1205 printk("process_cq did something\n");
1206 nvme_resubmit_bios(nvmeq);
1207 spin_unlock_irq(&nvmeq->q_lock);
1210 spin_unlock(&dev_list_lock);
1211 set_current_state(TASK_INTERRUPTIBLE);
1212 schedule_timeout(HZ);
1217 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1218 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1221 struct gendisk *disk;
1224 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1227 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1230 ns->queue = blk_alloc_queue(GFP_KERNEL);
1233 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1234 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1235 blk_queue_make_request(ns->queue, nvme_make_request);
1237 ns->queue->queuedata = ns;
1239 disk = alloc_disk(NVME_MINORS);
1241 goto out_free_queue;
1244 lbaf = id->flbas & 0xf;
1245 ns->lba_shift = id->lbaf[lbaf].ds;
1247 disk->major = nvme_major;
1248 disk->minors = NVME_MINORS;
1249 disk->first_minor = NVME_MINORS * index;
1250 disk->fops = &nvme_fops;
1251 disk->private_data = ns;
1252 disk->queue = ns->queue;
1253 disk->driverfs_dev = &dev->pci_dev->dev;
1254 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1255 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1260 blk_cleanup_queue(ns->queue);
1266 static void nvme_ns_free(struct nvme_ns *ns)
1269 blk_cleanup_queue(ns->queue);
1273 static int set_queue_count(struct nvme_dev *dev, int count)
1277 struct nvme_command c;
1278 u32 q_count = (count - 1) | ((count - 1) << 16);
1280 memset(&c, 0, sizeof(c));
1281 c.features.opcode = nvme_admin_get_features;
1282 c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1283 c.features.dword11 = cpu_to_le32(q_count);
1285 status = nvme_submit_admin_cmd(dev, &c, &result);
1288 return min(result & 0xffff, result >> 16) + 1;
1291 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1293 int result, cpu, i, nr_io_queues;
1295 nr_io_queues = num_online_cpus();
1296 result = set_queue_count(dev, nr_io_queues);
1299 if (result < nr_io_queues)
1300 nr_io_queues = result;
1302 /* Deregister the admin queue's interrupt */
1303 free_irq(dev->entry[0].vector, dev->queues[0]);
1305 for (i = 0; i < nr_io_queues; i++)
1306 dev->entry[i].entry = i;
1308 result = pci_enable_msix(dev->pci_dev, dev->entry,
1312 } else if (result > 0) {
1313 nr_io_queues = result;
1321 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1322 /* XXX: handle failure here */
1324 cpu = cpumask_first(cpu_online_mask);
1325 for (i = 0; i < nr_io_queues; i++) {
1326 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1327 cpu = cpumask_next(cpu, cpu_online_mask);
1330 for (i = 0; i < nr_io_queues; i++) {
1331 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1333 if (!dev->queues[i + 1])
1338 for (; i < num_possible_cpus(); i++) {
1339 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1340 dev->queues[i + 1] = dev->queues[target + 1];
1346 static void nvme_free_queues(struct nvme_dev *dev)
1350 for (i = dev->queue_count - 1; i >= 0; i--)
1351 nvme_free_queue(dev, i);
1354 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1357 struct nvme_ns *ns, *next;
1358 struct nvme_id_ctrl *ctrl;
1360 dma_addr_t dma_addr;
1361 struct nvme_command cid, crt;
1363 res = nvme_setup_io_queues(dev);
1367 /* XXX: Switch to a SG list once prp2 works */
1368 id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1371 memset(&cid, 0, sizeof(cid));
1372 cid.identify.opcode = nvme_admin_identify;
1373 cid.identify.nsid = 0;
1374 cid.identify.prp1 = cpu_to_le64(dma_addr);
1375 cid.identify.cns = cpu_to_le32(1);
1377 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1384 nn = le32_to_cpup(&ctrl->nn);
1385 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1386 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1387 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1389 cid.identify.cns = 0;
1390 memset(&crt, 0, sizeof(crt));
1391 crt.features.opcode = nvme_admin_get_features;
1392 crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1393 crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1395 for (i = 0; i <= nn; i++) {
1396 cid.identify.nsid = cpu_to_le32(i);
1397 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1401 if (((struct nvme_id_ns *)id)->ncap == 0)
1404 crt.features.nsid = cpu_to_le32(i);
1405 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1409 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1411 list_add_tail(&ns->list, &dev->namespaces);
1413 list_for_each_entry(ns, &dev->namespaces, list)
1416 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1420 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1421 list_del(&ns->list);
1425 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1429 static int nvme_dev_remove(struct nvme_dev *dev)
1431 struct nvme_ns *ns, *next;
1433 spin_lock(&dev_list_lock);
1434 list_del(&dev->node);
1435 spin_unlock(&dev_list_lock);
1437 /* TODO: wait all I/O finished or cancel them */
1439 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1440 list_del(&ns->list);
1441 del_gendisk(ns->disk);
1445 nvme_free_queues(dev);
1450 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1452 struct device *dmadev = &dev->pci_dev->dev;
1453 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1454 PAGE_SIZE, PAGE_SIZE, 0);
1455 if (!dev->prp_page_pool)
1458 /* Optimisation for I/Os between 4k and 128k */
1459 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1461 if (!dev->prp_small_pool) {
1462 dma_pool_destroy(dev->prp_page_pool);
1468 static void nvme_release_prp_pools(struct nvme_dev *dev)
1470 dma_pool_destroy(dev->prp_page_pool);
1471 dma_pool_destroy(dev->prp_small_pool);
1474 /* XXX: Use an ida or something to let remove / add work correctly */
1475 static void nvme_set_instance(struct nvme_dev *dev)
1477 static int instance;
1478 dev->instance = instance++;
1481 static void nvme_release_instance(struct nvme_dev *dev)
1485 static int __devinit nvme_probe(struct pci_dev *pdev,
1486 const struct pci_device_id *id)
1488 int bars, result = -ENOMEM;
1489 struct nvme_dev *dev;
1491 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1494 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1498 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1503 if (pci_enable_device_mem(pdev))
1505 pci_set_master(pdev);
1506 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1507 if (pci_request_selected_regions(pdev, bars, "nvme"))
1510 INIT_LIST_HEAD(&dev->namespaces);
1511 dev->pci_dev = pdev;
1512 pci_set_drvdata(pdev, dev);
1513 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1514 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1515 nvme_set_instance(dev);
1516 dev->entry[0].vector = pdev->irq;
1518 result = nvme_setup_prp_pools(dev);
1522 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1528 result = nvme_configure_admin_queue(dev);
1533 spin_lock(&dev_list_lock);
1534 list_add(&dev->node, &dev_list);
1535 spin_unlock(&dev_list_lock);
1537 result = nvme_dev_add(dev);
1544 spin_lock(&dev_list_lock);
1545 list_del(&dev->node);
1546 spin_unlock(&dev_list_lock);
1548 nvme_free_queues(dev);
1552 pci_disable_msix(pdev);
1553 nvme_release_instance(dev);
1554 nvme_release_prp_pools(dev);
1556 pci_disable_device(pdev);
1557 pci_release_regions(pdev);
1565 static void __devexit nvme_remove(struct pci_dev *pdev)
1567 struct nvme_dev *dev = pci_get_drvdata(pdev);
1568 nvme_dev_remove(dev);
1569 pci_disable_msix(pdev);
1571 nvme_release_instance(dev);
1572 nvme_release_prp_pools(dev);
1573 pci_disable_device(pdev);
1574 pci_release_regions(pdev);
1580 /* These functions are yet to be implemented */
1581 #define nvme_error_detected NULL
1582 #define nvme_dump_registers NULL
1583 #define nvme_link_reset NULL
1584 #define nvme_slot_reset NULL
1585 #define nvme_error_resume NULL
1586 #define nvme_suspend NULL
1587 #define nvme_resume NULL
1589 static struct pci_error_handlers nvme_err_handler = {
1590 .error_detected = nvme_error_detected,
1591 .mmio_enabled = nvme_dump_registers,
1592 .link_reset = nvme_link_reset,
1593 .slot_reset = nvme_slot_reset,
1594 .resume = nvme_error_resume,
1597 /* Move to pci_ids.h later */
1598 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1600 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1601 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1604 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1606 static struct pci_driver nvme_driver = {
1608 .id_table = nvme_id_table,
1609 .probe = nvme_probe,
1610 .remove = __devexit_p(nvme_remove),
1611 .suspend = nvme_suspend,
1612 .resume = nvme_resume,
1613 .err_handler = &nvme_err_handler,
1616 static int __init nvme_init(void)
1618 int result = -EBUSY;
1620 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1621 if (IS_ERR(nvme_thread))
1622 return PTR_ERR(nvme_thread);
1624 nvme_major = register_blkdev(nvme_major, "nvme");
1625 if (nvme_major <= 0)
1628 result = pci_register_driver(&nvme_driver);
1630 goto unregister_blkdev;
1634 unregister_blkdev(nvme_major, "nvme");
1636 kthread_stop(nvme_thread);
1640 static void __exit nvme_exit(void)
1642 pci_unregister_driver(&nvme_driver);
1643 unregister_blkdev(nvme_major, "nvme");
1644 kthread_stop(nvme_thread);
1647 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1648 MODULE_LICENSE("GPL");
1649 MODULE_VERSION("0.5");
1650 module_init(nvme_init);
1651 module_exit(nvme_exit);