2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/blkdev.h>
22 #include <linux/errno.h>
24 #include <linux/genhd.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/kdev_t.h>
29 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/moduleparam.h>
33 #include <linux/pci.h>
34 #include <linux/poison.h>
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/types.h>
38 #include <linux/version.h>
40 #define NVME_Q_DEPTH 1024
41 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
42 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
43 #define NVME_MINORS 64
44 #define IO_TIMEOUT (5 * HZ)
45 #define ADMIN_TIMEOUT (60 * HZ)
47 static int nvme_major;
48 module_param(nvme_major, int, 0);
50 static int use_threaded_interrupts;
51 module_param(use_threaded_interrupts, int, 0);
54 * Represents an NVM Express device. Each nvme_dev is a PCI function.
57 struct nvme_queue **queues;
59 struct pci_dev *pci_dev;
60 struct dma_pool *prp_page_pool;
64 struct msix_entry *entry;
65 struct nvme_bar __iomem *bar;
66 struct list_head namespaces;
73 * An NVM Express namespace is equivalent to a SCSI LUN
76 struct list_head list;
79 struct request_queue *queue;
87 * An NVM Express queue. Each device has at least two (one for admin
88 * commands and one for I/O commands).
91 struct device *q_dmadev;
94 struct nvme_command *sq_cmds;
95 volatile struct nvme_completion *cqes;
96 dma_addr_t sq_dma_addr;
97 dma_addr_t cq_dma_addr;
98 wait_queue_head_t sq_full;
99 struct bio_list sq_cong;
107 unsigned long cmdid_data[];
110 static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio);
113 * Check we didin't inadvertently grow the command struct
115 static inline void _nvme_check_size(void)
117 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
118 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
119 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
120 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
121 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
122 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
123 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
124 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
125 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
128 struct nvme_cmd_info {
130 unsigned long timeout;
133 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
135 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
139 * alloc_cmdid - Allocate a Command ID
140 * @param nvmeq The queue that will be used for this command
141 * @param ctx A pointer that will be passed to the handler
142 * @param handler The ID of the handler to call
144 * Allocate a Command ID for a queue. The data passed in will
145 * be passed to the completion handler. This is implemented by using
146 * the bottom two bits of the ctx pointer to store the handler ID.
147 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
148 * We can change this if it becomes a problem.
150 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
153 int depth = nvmeq->q_depth;
154 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
157 BUG_ON((unsigned long)ctx & 3);
160 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
163 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
165 info[cmdid].ctx = (unsigned long)ctx | handler;
166 info[cmdid].timeout = jiffies + timeout;
170 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
171 int handler, unsigned timeout)
174 wait_event_killable(nvmeq->sq_full,
175 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
176 return (cmdid < 0) ? -EINTR : cmdid;
179 /* If you need more than four handlers, you'll need to change how
180 * alloc_cmdid and nvme_process_cq work. Consider using a special
181 * CMD_CTX value instead, if that works for your situation.
184 sync_completion_id = 0,
188 #define CMD_CTX_BASE (POISON_POINTER_DELTA + sync_completion_id)
189 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
190 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
191 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
193 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
196 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
198 if (cmdid >= nvmeq->q_depth)
199 return CMD_CTX_INVALID;
200 data = info[cmdid].ctx;
201 info[cmdid].ctx = CMD_CTX_COMPLETED;
202 clear_bit(cmdid, nvmeq->cmdid_data);
203 wake_up(&nvmeq->sq_full);
207 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
209 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
210 info[cmdid].ctx = CMD_CTX_CANCELLED;
213 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
215 int qid, cpu = get_cpu();
216 if (cpu < ns->dev->queue_count)
219 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
220 return ns->dev->queues[qid];
223 static void put_nvmeq(struct nvme_queue *nvmeq)
229 * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
230 * @nvmeq: The queue to use
231 * @cmd: The command to send
233 * Safe to use from interrupt context
235 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
239 /* XXX: Need to check tail isn't going to overrun head */
240 spin_lock_irqsave(&nvmeq->q_lock, flags);
241 tail = nvmeq->sq_tail;
242 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
243 writel(tail, nvmeq->q_db);
244 if (++tail == nvmeq->q_depth)
246 nvmeq->sq_tail = tail;
247 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
252 static __le64 *alloc_prp_list(struct nvme_dev *dev, dma_addr_t *addr)
254 return dma_pool_alloc(dev->prp_page_pool, GFP_ATOMIC, addr);
259 dma_addr_t first_dma;
263 static void nvme_free_prps(struct nvme_queue *nvmeq, struct nvme_prps *prps)
265 const int last_prp = PAGE_SIZE / 8 - 1;
266 struct nvme_dev *dev = nvmeq->dev;
273 prp_dma = prps->first_dma;
274 for (i = 0; i < prps->npages; i++) {
275 __le64 *prp_list = prps->list[i];
276 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
277 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
278 prp_dma = next_prp_dma;
286 struct nvme_prps *prps;
287 struct scatterlist sg[0];
290 /* XXX: use a mempool */
291 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
293 return kzalloc(sizeof(struct nvme_bio) +
294 sizeof(struct scatterlist) * nseg, gfp);
297 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
299 nvme_free_prps(nvmeq, nbio->prps);
303 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
304 struct nvme_completion *cqe)
306 struct nvme_bio *nbio = ctx;
307 struct bio *bio = nbio->bio;
308 u16 status = le16_to_cpup(&cqe->status) >> 1;
310 dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
311 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
312 free_nbio(nvmeq, nbio);
313 bio_endio(bio, status ? -EIO : 0);
314 bio = bio_list_pop(&nvmeq->sq_cong);
316 nvme_resubmit_bio(nvmeq, bio);
319 /* length is in bytes */
320 static struct nvme_prps *nvme_setup_prps(struct nvme_queue *nvmeq,
321 struct nvme_common_command *cmd,
322 struct scatterlist *sg, int length)
324 struct nvme_dev *dev = nvmeq->dev;
325 int dma_len = sg_dma_len(sg);
326 u64 dma_addr = sg_dma_address(sg);
327 int offset = offset_in_page(dma_addr);
330 int nprps, npages, i, prp_page;
331 struct nvme_prps *prps = NULL;
333 cmd->prp1 = cpu_to_le64(dma_addr);
334 length -= (PAGE_SIZE - offset);
338 dma_len -= (PAGE_SIZE - offset);
340 dma_addr += (PAGE_SIZE - offset);
343 dma_addr = sg_dma_address(sg);
344 dma_len = sg_dma_len(sg);
347 if (length <= PAGE_SIZE) {
348 cmd->prp2 = cpu_to_le64(dma_addr);
352 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
353 npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
354 prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
355 prps->npages = npages;
357 prp_list = alloc_prp_list(dev, &prp_dma);
358 prps->list[prp_page++] = prp_list;
359 prps->first_dma = prp_dma;
360 cmd->prp2 = cpu_to_le64(prp_dma);
363 if (i == PAGE_SIZE / 8 - 1) {
364 __le64 *old_prp_list = prp_list;
365 prp_list = alloc_prp_list(dev, &prp_dma);
366 prps->list[prp_page++] = prp_list;
367 old_prp_list[i] = cpu_to_le64(prp_dma);
370 prp_list[i++] = cpu_to_le64(dma_addr);
371 dma_len -= PAGE_SIZE;
372 dma_addr += PAGE_SIZE;
380 dma_addr = sg_dma_address(sg);
381 dma_len = sg_dma_len(sg);
387 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
388 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
390 struct bio_vec *bvec;
391 struct scatterlist *sg = nbio->sg;
394 sg_init_table(sg, psegs);
395 bio_for_each_segment(bvec, bio, i) {
396 sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset);
398 /* XXX: handle non-mergable here */
403 return dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir);
406 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
409 struct nvme_command *cmnd;
410 struct nvme_bio *nbio;
411 enum dma_data_direction dma_dir;
416 int psegs = bio_phys_segments(ns->queue, bio);
418 nbio = alloc_nbio(psegs, GFP_NOIO);
423 cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
424 if (unlikely(cmdid < 0))
428 if (bio->bi_rw & REQ_FUA)
429 control |= NVME_RW_FUA;
430 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
431 control |= NVME_RW_LR;
434 if (bio->bi_rw & REQ_RAHEAD)
435 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
437 spin_lock_irqsave(&nvmeq->q_lock, flags);
438 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
440 memset(cmnd, 0, sizeof(*cmnd));
441 if (bio_data_dir(bio)) {
442 cmnd->rw.opcode = nvme_cmd_write;
443 dma_dir = DMA_TO_DEVICE;
445 cmnd->rw.opcode = nvme_cmd_read;
446 dma_dir = DMA_FROM_DEVICE;
449 nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
452 cmnd->rw.command_id = cmdid;
453 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
454 nbio->prps = nvme_setup_prps(nvmeq, &cmnd->common, nbio->sg,
456 cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
457 cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
458 cmnd->rw.control = cpu_to_le16(control);
459 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
461 writel(nvmeq->sq_tail, nvmeq->q_db);
462 if (++nvmeq->sq_tail == nvmeq->q_depth)
465 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
470 free_nbio(nvmeq, nbio);
475 static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio)
477 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
478 if (nvme_submit_bio_queue(nvmeq, ns, bio))
479 bio_list_add_head(&nvmeq->sq_cong, bio);
480 else if (bio_list_empty(&nvmeq->sq_cong))
481 blk_clear_queue_congested(ns->queue, rw_is_sync(bio->bi_rw));
482 /* XXX: Need to duplicate the logic from __freed_request here */
486 * NB: return value of non-zero would mean that we were a stacking driver.
487 * make_request must always succeed.
489 static int nvme_make_request(struct request_queue *q, struct bio *bio)
491 struct nvme_ns *ns = q->queuedata;
492 struct nvme_queue *nvmeq = get_nvmeq(ns);
494 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
495 blk_set_queue_congested(q, rw_is_sync(bio->bi_rw));
496 spin_lock_irq(&nvmeq->q_lock);
497 bio_list_add(&nvmeq->sq_cong, bio);
498 spin_unlock_irq(&nvmeq->q_lock);
505 struct sync_cmd_info {
506 struct task_struct *task;
511 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
512 struct nvme_completion *cqe)
514 struct sync_cmd_info *cmdinfo = ctx;
515 if ((unsigned long)cmdinfo == CMD_CTX_CANCELLED)
517 if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
518 dev_warn(nvmeq->q_dmadev,
519 "completed id %d twice on queue %d\n",
520 cqe->command_id, le16_to_cpup(&cqe->sq_id));
523 if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
524 dev_warn(nvmeq->q_dmadev,
525 "invalid id %d completed on queue %d\n",
526 cqe->command_id, le16_to_cpup(&cqe->sq_id));
529 cmdinfo->result = le32_to_cpup(&cqe->result);
530 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
531 wake_up_process(cmdinfo->task);
534 typedef void (*completion_fn)(struct nvme_queue *, void *,
535 struct nvme_completion *);
537 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
541 static const completion_fn completions[4] = {
542 [sync_completion_id] = sync_completion,
543 [bio_completion_id] = bio_completion,
546 head = nvmeq->cq_head;
547 phase = nvmeq->cq_phase;
552 unsigned char handler;
553 struct nvme_completion cqe = nvmeq->cqes[head];
554 if ((le16_to_cpu(cqe.status) & 1) != phase)
556 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
557 if (++head == nvmeq->q_depth) {
562 data = free_cmdid(nvmeq, cqe.command_id);
564 ptr = (void *)(data & ~3UL);
565 completions[handler](nvmeq, ptr, &cqe);
568 /* If the controller ignores the cq head doorbell and continuously
569 * writes to the queue, it is theoretically possible to wrap around
570 * the queue twice and mistakenly return IRQ_NONE. Linux only
571 * requires that 0.1% of your interrupts are handled, so this isn't
574 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
577 writel(head, nvmeq->q_db + 1);
578 nvmeq->cq_head = head;
579 nvmeq->cq_phase = phase;
584 static irqreturn_t nvme_irq(int irq, void *data)
587 struct nvme_queue *nvmeq = data;
588 spin_lock(&nvmeq->q_lock);
589 result = nvme_process_cq(nvmeq);
590 spin_unlock(&nvmeq->q_lock);
594 static irqreturn_t nvme_irq_check(int irq, void *data)
596 struct nvme_queue *nvmeq = data;
597 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
598 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
600 return IRQ_WAKE_THREAD;
603 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
605 spin_lock_irq(&nvmeq->q_lock);
606 cancel_cmdid_data(nvmeq, cmdid);
607 spin_unlock_irq(&nvmeq->q_lock);
611 * Returns 0 on success. If the result is negative, it's a Linux error code;
612 * if the result is positive, it's an NVM Express status code
614 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
615 struct nvme_command *cmd, u32 *result, unsigned timeout)
618 struct sync_cmd_info cmdinfo;
620 cmdinfo.task = current;
621 cmdinfo.status = -EINTR;
623 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
627 cmd->common.command_id = cmdid;
629 set_current_state(TASK_KILLABLE);
630 nvme_submit_cmd(nvmeq, cmd);
633 if (cmdinfo.status == -EINTR) {
634 nvme_abort_command(nvmeq, cmdid);
639 *result = cmdinfo.result;
641 return cmdinfo.status;
644 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
647 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
650 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
653 struct nvme_command c;
655 memset(&c, 0, sizeof(c));
656 c.delete_queue.opcode = opcode;
657 c.delete_queue.qid = cpu_to_le16(id);
659 status = nvme_submit_admin_cmd(dev, &c, NULL);
665 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
666 struct nvme_queue *nvmeq)
669 struct nvme_command c;
670 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
672 memset(&c, 0, sizeof(c));
673 c.create_cq.opcode = nvme_admin_create_cq;
674 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
675 c.create_cq.cqid = cpu_to_le16(qid);
676 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
677 c.create_cq.cq_flags = cpu_to_le16(flags);
678 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
680 status = nvme_submit_admin_cmd(dev, &c, NULL);
686 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
687 struct nvme_queue *nvmeq)
690 struct nvme_command c;
691 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
693 memset(&c, 0, sizeof(c));
694 c.create_sq.opcode = nvme_admin_create_sq;
695 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
696 c.create_sq.sqid = cpu_to_le16(qid);
697 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
698 c.create_sq.sq_flags = cpu_to_le16(flags);
699 c.create_sq.cqid = cpu_to_le16(qid);
701 status = nvme_submit_admin_cmd(dev, &c, NULL);
707 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
709 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
712 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
714 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
717 static void nvme_free_queue(struct nvme_dev *dev, int qid)
719 struct nvme_queue *nvmeq = dev->queues[qid];
721 free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
723 /* Don't tell the adapter to delete the admin queue */
725 adapter_delete_sq(dev, qid);
726 adapter_delete_cq(dev, qid);
729 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
730 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
731 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
732 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
736 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
737 int depth, int vector)
739 struct device *dmadev = &dev->pci_dev->dev;
740 unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
741 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
745 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
746 &nvmeq->cq_dma_addr, GFP_KERNEL);
749 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
751 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
752 &nvmeq->sq_dma_addr, GFP_KERNEL);
756 nvmeq->q_dmadev = dmadev;
758 spin_lock_init(&nvmeq->q_lock);
761 init_waitqueue_head(&nvmeq->sq_full);
762 bio_list_init(&nvmeq->sq_cong);
763 nvmeq->q_db = &dev->dbs[qid * 2];
764 nvmeq->q_depth = depth;
765 nvmeq->cq_vector = vector;
770 dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
777 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
780 if (use_threaded_interrupts)
781 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
782 nvme_irq_check, nvme_irq,
783 IRQF_DISABLED | IRQF_SHARED,
785 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
786 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
789 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
790 int qid, int cq_size, int vector)
793 struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
798 result = adapter_alloc_cq(dev, qid, nvmeq);
802 result = adapter_alloc_sq(dev, qid, nvmeq);
806 result = queue_request_irq(dev, nvmeq, "nvme");
813 adapter_delete_sq(dev, qid);
815 adapter_delete_cq(dev, qid);
817 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
818 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
819 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
820 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
825 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
829 struct nvme_queue *nvmeq;
831 dev->dbs = ((void __iomem *)dev->bar) + 4096;
833 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
837 aqa = nvmeq->q_depth - 1;
840 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
841 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
842 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
844 writel(0, &dev->bar->cc);
845 writel(aqa, &dev->bar->aqa);
846 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
847 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
848 writel(dev->ctrl_config, &dev->bar->cc);
850 while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
852 if (fatal_signal_pending(current))
856 result = queue_request_irq(dev, nvmeq, "nvme admin");
857 dev->queues[0] = nvmeq;
861 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
862 unsigned long addr, unsigned length,
863 struct scatterlist **sgp)
865 int i, err, count, nents, offset;
866 struct scatterlist *sg;
874 offset = offset_in_page(addr);
875 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
876 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
878 err = get_user_pages_fast(addr, count, 1, pages);
885 sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
886 sg_init_table(sg, count);
887 sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
888 length -= (PAGE_SIZE - offset);
889 for (i = 1; i < count; i++) {
890 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
895 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
896 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
905 for (i = 0; i < count; i++)
911 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
912 unsigned long addr, int length,
913 struct scatterlist *sg, int nents)
917 count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
918 dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
920 for (i = 0; i < count; i++)
921 put_page(sg_page(&sg[i]));
924 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
925 unsigned long addr, unsigned length,
926 struct nvme_command *cmd)
929 struct scatterlist *sg;
930 struct nvme_prps *prps;
932 nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
935 prps = nvme_setup_prps(dev->queues[0], &cmd->common, sg, length);
936 err = nvme_submit_admin_cmd(dev, cmd, NULL);
937 nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
938 nvme_free_prps(dev->queues[0], prps);
939 return err ? -EIO : 0;
942 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
944 struct nvme_command c;
946 memset(&c, 0, sizeof(c));
947 c.identify.opcode = nvme_admin_identify;
948 c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
949 c.identify.cns = cpu_to_le32(cns);
951 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
954 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
956 struct nvme_command c;
958 memset(&c, 0, sizeof(c));
959 c.features.opcode = nvme_admin_get_features;
960 c.features.nsid = cpu_to_le32(ns->ns_id);
961 c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
963 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
966 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
968 struct nvme_dev *dev = ns->dev;
969 struct nvme_queue *nvmeq;
970 struct nvme_user_io io;
971 struct nvme_command c;
975 struct scatterlist *sg;
976 struct nvme_prps *prps;
978 if (copy_from_user(&io, uio, sizeof(io)))
980 length = io.nblocks << io.block_shift;
981 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
985 memset(&c, 0, sizeof(c));
986 c.rw.opcode = io.opcode;
987 c.rw.flags = io.flags;
988 c.rw.nsid = cpu_to_le32(io.nsid);
989 c.rw.slba = cpu_to_le64(io.slba);
990 c.rw.length = cpu_to_le16(io.nblocks - 1);
991 c.rw.control = cpu_to_le16(io.control);
992 c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
993 c.rw.reftag = cpu_to_le32(io.reftag); /* XXX: endian? */
994 c.rw.apptag = cpu_to_le16(io.apptag);
995 c.rw.appmask = cpu_to_le16(io.appmask);
996 nvmeq = get_nvmeq(ns);
998 prps = nvme_setup_prps(nvmeq, &c.common, sg, length);
1000 /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1001 * disabled. We may be preempted at any point, and be rescheduled
1002 * to a different CPU. That will cause cacheline bouncing, but no
1003 * additional races since q_lock already protects against other CPUs.
1006 status = nvme_submit_sync_cmd(nvmeq, &c, &result, IO_TIMEOUT);
1008 nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
1009 nvme_free_prps(nvmeq, prps);
1010 put_user(result, &uio->result);
1014 static int nvme_download_firmware(struct nvme_ns *ns,
1015 struct nvme_dlfw __user *udlfw)
1017 struct nvme_dev *dev = ns->dev;
1018 struct nvme_dlfw dlfw;
1019 struct nvme_command c;
1021 struct scatterlist *sg;
1022 struct nvme_prps *prps;
1024 if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1026 if (dlfw.length >= (1 << 30))
1029 nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1033 memset(&c, 0, sizeof(c));
1034 c.dlfw.opcode = nvme_admin_download_fw;
1035 c.dlfw.numd = cpu_to_le32(dlfw.length);
1036 c.dlfw.offset = cpu_to_le32(dlfw.offset);
1037 prps = nvme_setup_prps(dev->queues[0], &c.common, sg, dlfw.length * 4);
1039 status = nvme_submit_admin_cmd(dev, &c, NULL);
1040 nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
1041 nvme_free_prps(dev->queues[0], prps);
1045 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1047 struct nvme_dev *dev = ns->dev;
1048 struct nvme_command c;
1050 memset(&c, 0, sizeof(c));
1051 c.common.opcode = nvme_admin_activate_fw;
1052 c.common.rsvd10[0] = cpu_to_le32(arg);
1054 return nvme_submit_admin_cmd(dev, &c, NULL);
1057 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1060 struct nvme_ns *ns = bdev->bd_disk->private_data;
1063 case NVME_IOCTL_IDENTIFY_NS:
1064 return nvme_identify(ns, arg, 0);
1065 case NVME_IOCTL_IDENTIFY_CTRL:
1066 return nvme_identify(ns, arg, 1);
1067 case NVME_IOCTL_GET_RANGE_TYPE:
1068 return nvme_get_range_type(ns, arg);
1069 case NVME_IOCTL_SUBMIT_IO:
1070 return nvme_submit_io(ns, (void __user *)arg);
1071 case NVME_IOCTL_DOWNLOAD_FW:
1072 return nvme_download_firmware(ns, (void __user *)arg);
1073 case NVME_IOCTL_ACTIVATE_FW:
1074 return nvme_activate_firmware(ns, arg);
1080 static const struct block_device_operations nvme_fops = {
1081 .owner = THIS_MODULE,
1082 .ioctl = nvme_ioctl,
1085 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1086 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1089 struct gendisk *disk;
1092 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1095 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1098 ns->queue = blk_alloc_queue(GFP_KERNEL);
1101 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1102 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1103 blk_queue_make_request(ns->queue, nvme_make_request);
1105 ns->queue->queuedata = ns;
1107 disk = alloc_disk(NVME_MINORS);
1109 goto out_free_queue;
1112 lbaf = id->flbas & 0xf;
1113 ns->lba_shift = id->lbaf[lbaf].ds;
1115 disk->major = nvme_major;
1116 disk->minors = NVME_MINORS;
1117 disk->first_minor = NVME_MINORS * index;
1118 disk->fops = &nvme_fops;
1119 disk->private_data = ns;
1120 disk->queue = ns->queue;
1121 disk->driverfs_dev = &dev->pci_dev->dev;
1122 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1123 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1128 blk_cleanup_queue(ns->queue);
1134 static void nvme_ns_free(struct nvme_ns *ns)
1137 blk_cleanup_queue(ns->queue);
1141 static int set_queue_count(struct nvme_dev *dev, int count)
1145 struct nvme_command c;
1146 u32 q_count = (count - 1) | ((count - 1) << 16);
1148 memset(&c, 0, sizeof(c));
1149 c.features.opcode = nvme_admin_get_features;
1150 c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1151 c.features.dword11 = cpu_to_le32(q_count);
1153 status = nvme_submit_admin_cmd(dev, &c, &result);
1156 return min(result & 0xffff, result >> 16) + 1;
1159 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1161 int result, cpu, i, nr_queues;
1163 nr_queues = num_online_cpus();
1164 result = set_queue_count(dev, nr_queues);
1167 if (result < nr_queues)
1170 /* Deregister the admin queue's interrupt */
1171 free_irq(dev->entry[0].vector, dev->queues[0]);
1173 for (i = 0; i < nr_queues; i++)
1174 dev->entry[i].entry = i;
1176 result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
1179 } else if (result > 0) {
1188 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1189 /* XXX: handle failure here */
1191 cpu = cpumask_first(cpu_online_mask);
1192 for (i = 0; i < nr_queues; i++) {
1193 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1194 cpu = cpumask_next(cpu, cpu_online_mask);
1197 for (i = 0; i < nr_queues; i++) {
1198 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1200 if (!dev->queues[i + 1])
1208 static void nvme_free_queues(struct nvme_dev *dev)
1212 for (i = dev->queue_count - 1; i >= 0; i--)
1213 nvme_free_queue(dev, i);
1216 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1219 struct nvme_ns *ns, *next;
1220 struct nvme_id_ctrl *ctrl;
1222 dma_addr_t dma_addr;
1223 struct nvme_command cid, crt;
1225 res = nvme_setup_io_queues(dev);
1229 /* XXX: Switch to a SG list once prp2 works */
1230 id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1233 memset(&cid, 0, sizeof(cid));
1234 cid.identify.opcode = nvme_admin_identify;
1235 cid.identify.nsid = 0;
1236 cid.identify.prp1 = cpu_to_le64(dma_addr);
1237 cid.identify.cns = cpu_to_le32(1);
1239 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1246 nn = le32_to_cpup(&ctrl->nn);
1247 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1248 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1249 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1251 cid.identify.cns = 0;
1252 memset(&crt, 0, sizeof(crt));
1253 crt.features.opcode = nvme_admin_get_features;
1254 crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1255 crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1257 for (i = 0; i < nn; i++) {
1258 cid.identify.nsid = cpu_to_le32(i);
1259 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1263 if (((struct nvme_id_ns *)id)->ncap == 0)
1266 crt.features.nsid = cpu_to_le32(i);
1267 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1271 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1273 list_add_tail(&ns->list, &dev->namespaces);
1275 list_for_each_entry(ns, &dev->namespaces, list)
1278 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1282 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1283 list_del(&ns->list);
1287 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1291 static int nvme_dev_remove(struct nvme_dev *dev)
1293 struct nvme_ns *ns, *next;
1295 /* TODO: wait all I/O finished or cancel them */
1297 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1298 list_del(&ns->list);
1299 del_gendisk(ns->disk);
1303 nvme_free_queues(dev);
1308 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1310 struct device *dmadev = &dev->pci_dev->dev;
1311 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1312 PAGE_SIZE, PAGE_SIZE, 0);
1313 if (!dev->prp_page_pool)
1319 static void nvme_release_prp_pools(struct nvme_dev *dev)
1321 dma_pool_destroy(dev->prp_page_pool);
1324 /* XXX: Use an ida or something to let remove / add work correctly */
1325 static void nvme_set_instance(struct nvme_dev *dev)
1327 static int instance;
1328 dev->instance = instance++;
1331 static void nvme_release_instance(struct nvme_dev *dev)
1335 static int __devinit nvme_probe(struct pci_dev *pdev,
1336 const struct pci_device_id *id)
1338 int bars, result = -ENOMEM;
1339 struct nvme_dev *dev;
1341 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1344 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1348 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1353 if (pci_enable_device_mem(pdev))
1355 pci_set_master(pdev);
1356 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1357 if (pci_request_selected_regions(pdev, bars, "nvme"))
1360 INIT_LIST_HEAD(&dev->namespaces);
1361 dev->pci_dev = pdev;
1362 pci_set_drvdata(pdev, dev);
1363 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1364 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1365 nvme_set_instance(dev);
1366 dev->entry[0].vector = pdev->irq;
1368 result = nvme_setup_prp_pools(dev);
1372 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1378 result = nvme_configure_admin_queue(dev);
1383 result = nvme_dev_add(dev);
1389 nvme_free_queues(dev);
1393 pci_disable_msix(pdev);
1394 nvme_release_instance(dev);
1395 nvme_release_prp_pools(dev);
1397 pci_disable_device(pdev);
1398 pci_release_regions(pdev);
1406 static void __devexit nvme_remove(struct pci_dev *pdev)
1408 struct nvme_dev *dev = pci_get_drvdata(pdev);
1409 nvme_dev_remove(dev);
1410 pci_disable_msix(pdev);
1412 nvme_release_instance(dev);
1413 nvme_release_prp_pools(dev);
1414 pci_disable_device(pdev);
1415 pci_release_regions(pdev);
1421 /* These functions are yet to be implemented */
1422 #define nvme_error_detected NULL
1423 #define nvme_dump_registers NULL
1424 #define nvme_link_reset NULL
1425 #define nvme_slot_reset NULL
1426 #define nvme_error_resume NULL
1427 #define nvme_suspend NULL
1428 #define nvme_resume NULL
1430 static struct pci_error_handlers nvme_err_handler = {
1431 .error_detected = nvme_error_detected,
1432 .mmio_enabled = nvme_dump_registers,
1433 .link_reset = nvme_link_reset,
1434 .slot_reset = nvme_slot_reset,
1435 .resume = nvme_error_resume,
1438 /* Move to pci_ids.h later */
1439 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1441 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1442 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1445 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1447 static struct pci_driver nvme_driver = {
1449 .id_table = nvme_id_table,
1450 .probe = nvme_probe,
1451 .remove = __devexit_p(nvme_remove),
1452 .suspend = nvme_suspend,
1453 .resume = nvme_resume,
1454 .err_handler = &nvme_err_handler,
1457 static int __init nvme_init(void)
1461 nvme_major = register_blkdev(nvme_major, "nvme");
1462 if (nvme_major <= 0)
1465 result = pci_register_driver(&nvme_driver);
1469 unregister_blkdev(nvme_major, "nvme");
1473 static void __exit nvme_exit(void)
1475 pci_unregister_driver(&nvme_driver);
1476 unregister_blkdev(nvme_major, "nvme");
1479 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1480 MODULE_LICENSE("GPL");
1481 MODULE_VERSION("0.2");
1482 module_init(nvme_init);
1483 module_exit(nvme_exit);