drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/blkdev.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kernel.h>
  30 #include <linux/mm.h>
  31 #include <linux/module.h>
  32 #include <linux/moduleparam.h>
  33 #include <linux/pci.h>
  34 #include <linux/sched.h>
  35 #include <linux/slab.h>
  36 #include <linux/types.h>
  37 #include <linux/version.h>
  38
  39 #define NVME_Q_DEPTH 1024
  40 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  41 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  42 #define NVME_MINORS 64
  43
  44 static int nvme_major;
  45 module_param(nvme_major, int, 0);
  46
  47 /*
  48  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  49  */
  50 struct nvme_dev {
  51         struct list_head node;
  52         struct nvme_queue **queues;
  53         u32 __iomem *dbs;
  54         struct pci_dev *pci_dev;
  55         int instance;
  56         int queue_count;
  57         u32 ctrl_config;
  58         struct msix_entry *entry;
  59         struct nvme_bar __iomem *bar;
  60         struct list_head namespaces;
  61         char serial[20];
  62         char model[40];
  63         char firmware_rev[8];
  64 };
  65
  66 /*
  67  * An NVM Express namespace is equivalent to a SCSI LUN
  68  */
  69 struct nvme_ns {
  70         struct list_head list;
  71
  72         struct nvme_dev *dev;
  73         struct request_queue *queue;
  74         struct gendisk *disk;
  75
  76         int ns_id;
  77         int lba_shift;
  78 };
  79
  80 /*
  81  * An NVM Express queue.  Each device has at least two (one for admin
  82  * commands and one for I/O commands).
  83  */
  84 struct nvme_queue {
  85         struct device *q_dmadev;
  86         spinlock_t q_lock;
  87         struct nvme_command *sq_cmds;
  88         volatile struct nvme_completion *cqes;
  89         dma_addr_t sq_dma_addr;
  90         dma_addr_t cq_dma_addr;
  91         wait_queue_head_t sq_full;
  92         struct bio_list sq_cong;
  93         u32 __iomem *q_db;
  94         u16 q_depth;
  95         u16 cq_vector;
  96         u16 sq_head;
  97         u16 sq_tail;
  98         u16 cq_head;
  99         u16 cq_phase;
 100         unsigned long cmdid_data[];
 101 };
 102
 103 /*
 104  * Check we didin't inadvertently grow the command struct
 105  */
 106 static inline void _nvme_check_size(void)
 107 {
 108         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 109         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 110         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 111         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 112         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 113         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 114         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 115         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 116         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 117 }
 118
 119 /**
 120  * alloc_cmdid - Allocate a Command ID
 121  * @param nvmeq The queue that will be used for this command
 122  * @param ctx A pointer that will be passed to the handler
 123  * @param handler The ID of the handler to call
 124  *
 125  * Allocate a Command ID for a queue.  The data passed in will
 126  * be passed to the completion handler.  This is implemented by using
 127  * the bottom two bits of the ctx pointer to store the handler ID.
 128  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 129  * We can change this if it becomes a problem.
 130  */
 131 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler)
 132 {
 133         int depth = nvmeq->q_depth;
 134         unsigned long data = (unsigned long)ctx | handler;
 135         int cmdid;
 136
 137         BUG_ON((unsigned long)ctx & 3);
 138
 139         do {
 140                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 141                 if (cmdid >= depth)
 142                         return -EBUSY;
 143         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 144
 145         nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(depth)] = data;
 146         return cmdid;
 147 }
 148
 149 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 150                                                                 int handler)
 151 {
 152         int cmdid;
 153         wait_event_killable(nvmeq->sq_full,
 154                         (cmdid = alloc_cmdid(nvmeq, ctx, handler)) >= 0);
 155         return (cmdid < 0) ? -EINTR : cmdid;
 156 }
 157
 158 /* If you need more than four handlers, you'll need to change how
 159  * alloc_cmdid and nvme_process_cq work
 160  */
 161 enum {
 162         sync_completion_id = 0,
 163         bio_completion_id,
 164 };
 165
 166 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 167 {
 168         unsigned long data;
 169
 170         data = nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(nvmeq->q_depth)];
 171         clear_bit(cmdid, nvmeq->cmdid_data);
 172         wake_up(&nvmeq->sq_full);
 173         return data;
 174 }
 175
 176 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 177 {
 178         int qid, cpu = get_cpu();
 179         if (cpu < ns->dev->queue_count)
 180                 qid = cpu + 1;
 181         else
 182                 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
 183         return ns->dev->queues[qid];
 184 }
 185
 186 static void put_nvmeq(struct nvme_queue *nvmeq)
 187 {
 188         put_cpu();
 189 }
 190
 191 /**
 192  * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
 193  * @nvmeq: The queue to use
 194  * @cmd: The command to send
 195  *
 196  * Safe to use from interrupt context
 197  */
 198 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 199 {
 200         unsigned long flags;
 201         u16 tail;
 202         /* XXX: Need to check tail isn't going to overrun head */
 203         spin_lock_irqsave(&nvmeq->q_lock, flags);
 204         tail = nvmeq->sq_tail;
 205         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 206         writel(tail, nvmeq->q_db);
 207         if (++tail == nvmeq->q_depth)
 208                 tail = 0;
 209         nvmeq->sq_tail = tail;
 210         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 211
 212         return 0;
 213 }
 214
 215 struct nvme_req_info {
 216         struct bio *bio;
 217         int nents;
 218         struct scatterlist sg[0];
 219 };
 220
 221 /* XXX: use a mempool */
 222 static struct nvme_req_info *alloc_info(unsigned nseg, gfp_t gfp)
 223 {
 224         return kmalloc(sizeof(struct nvme_req_info) +
 225                         sizeof(struct scatterlist) * nseg, gfp);
 226 }
 227
 228 static void free_info(struct nvme_req_info *info)
 229 {
 230         kfree(info);
 231 }
 232
 233 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 234                                                 struct nvme_completion *cqe)
 235 {
 236         struct nvme_req_info *info = ctx;
 237         struct bio *bio = info->bio;
 238         u16 status = le16_to_cpup(&cqe->status) >> 1;
 239
 240         dma_unmap_sg(nvmeq->q_dmadev, info->sg, info->nents,
 241                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 242         free_info(info);
 243         bio_endio(bio, status ? -EIO : 0);
 244 }
 245
 246 /* length is in bytes */
 247 static void nvme_setup_prps(struct nvme_common_command *cmd,
 248                                         struct scatterlist *sg, int length)
 249 {
 250         int dma_len = sg_dma_len(sg);
 251         u64 dma_addr = sg_dma_address(sg);
 252         int offset = offset_in_page(dma_addr);
 253
 254         cmd->prp1 = cpu_to_le64(dma_addr);
 255         length -= (PAGE_SIZE - offset);
 256         if (length <= 0)
 257                 return;
 258
 259         dma_len -= (PAGE_SIZE - offset);
 260         if (dma_len) {
 261                 dma_addr += (PAGE_SIZE - offset);
 262         } else {
 263                 sg = sg_next(sg);
 264                 dma_addr = sg_dma_address(sg);
 265                 dma_len = sg_dma_len(sg);
 266         }
 267
 268         if (length <= PAGE_SIZE) {
 269                 cmd->prp2 = cpu_to_le64(dma_addr);
 270                 return;
 271         }
 272
 273         /* XXX: support PRP lists */
 274 }
 275
 276 static int nvme_map_bio(struct device *dev, struct nvme_req_info *info,
 277                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 278 {
 279         struct bio_vec *bvec;
 280         struct scatterlist *sg = info->sg;
 281         int i, nsegs;
 282
 283         sg_init_table(sg, psegs);
 284         bio_for_each_segment(bvec, bio, i) {
 285                 sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset);
 286                 /* XXX: handle non-mergable here */
 287                 nsegs++;
 288         }
 289         info->nents = nsegs;
 290
 291         return dma_map_sg(dev, info->sg, info->nents, dma_dir);
 292 }
 293
 294 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 295                                                                 struct bio *bio)
 296 {
 297         struct nvme_command *cmnd;
 298         struct nvme_req_info *info;
 299         enum dma_data_direction dma_dir;
 300         int cmdid;
 301         u16 control;
 302         u32 dsmgmt;
 303         unsigned long flags;
 304         int psegs = bio_phys_segments(ns->queue, bio);
 305
 306         info = alloc_info(psegs, GFP_NOIO);
 307         if (!info)
 308                 goto congestion;
 309         info->bio = bio;
 310
 311         cmdid = alloc_cmdid(nvmeq, info, bio_completion_id);
 312         if (unlikely(cmdid < 0))
 313                 goto free_info;
 314
 315         control = 0;
 316         if (bio->bi_rw & REQ_FUA)
 317                 control |= NVME_RW_FUA;
 318         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 319                 control |= NVME_RW_LR;
 320
 321         dsmgmt = 0;
 322         if (bio->bi_rw & REQ_RAHEAD)
 323                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 324
 325         spin_lock_irqsave(&nvmeq->q_lock, flags);
 326         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 327
 328         memset(cmnd, 0, sizeof(*cmnd));
 329         if (bio_data_dir(bio)) {
 330                 cmnd->rw.opcode = nvme_cmd_write;
 331                 dma_dir = DMA_TO_DEVICE;
 332         } else {
 333                 cmnd->rw.opcode = nvme_cmd_read;
 334                 dma_dir = DMA_FROM_DEVICE;
 335         }
 336
 337         nvme_map_bio(nvmeq->q_dmadev, info, bio, dma_dir, psegs);
 338
 339         cmnd->rw.flags = 1;
 340         cmnd->rw.command_id = cmdid;
 341         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 342         nvme_setup_prps(&cmnd->common, info->sg, bio->bi_size);
 343         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 344         cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
 345         cmnd->rw.control = cpu_to_le16(control);
 346         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 347
 348         writel(nvmeq->sq_tail, nvmeq->q_db);
 349         if (++nvmeq->sq_tail == nvmeq->q_depth)
 350                 nvmeq->sq_tail = 0;
 351
 352         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 353
 354         return 0;
 355
 356  free_info:
 357         free_info(info);
 358  congestion:
 359         return -EBUSY;
 360 }
 361
 362 /*
 363  * NB: return value of non-zero would mean that we were a stacking driver.
 364  * make_request must always succeed.
 365  */
 366 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 367 {
 368         struct nvme_ns *ns = q->queuedata;
 369         struct nvme_queue *nvmeq = get_nvmeq(ns);
 370
 371         if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
 372                 blk_set_queue_congested(q, rw_is_sync(bio->bi_rw));
 373                 bio_list_add(&nvmeq->sq_cong, bio);
 374         }
 375         put_nvmeq(nvmeq);
 376
 377         return 0;
 378 }
 379
 380 struct sync_cmd_info {
 381         struct task_struct *task;
 382         u32 result;
 383         int status;
 384 };
 385
 386 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 387                                                 struct nvme_completion *cqe)
 388 {
 389         struct sync_cmd_info *cmdinfo = ctx;
 390         cmdinfo->result = le32_to_cpup(&cqe->result);
 391         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 392         wake_up_process(cmdinfo->task);
 393 }
 394
 395 typedef void (*completion_fn)(struct nvme_queue *, void *,
 396                                                 struct nvme_completion *);
 397
 398 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 399 {
 400         u16 head, phase;
 401
 402         static const completion_fn completions[4] = {
 403                 [sync_completion_id] = sync_completion,
 404                 [bio_completion_id]  = bio_completion,
 405         };
 406
 407         head = nvmeq->cq_head;
 408         phase = nvmeq->cq_phase;
 409
 410         for (;;) {
 411                 unsigned long data;
 412                 void *ptr;
 413                 unsigned char handler;
 414                 struct nvme_completion cqe = nvmeq->cqes[head];
 415                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 416                         break;
 417                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 418                 if (++head == nvmeq->q_depth) {
 419                         head = 0;
 420                         phase = !phase;
 421                 }
 422
 423                 data = free_cmdid(nvmeq, cqe.command_id);
 424                 handler = data & 3;
 425                 ptr = (void *)(data & ~3UL);
 426                 completions[handler](nvmeq, ptr, &cqe);
 427         }
 428
 429         /* If the controller ignores the cq head doorbell and continuously
 430          * writes to the queue, it is theoretically possible to wrap around
 431          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 432          * requires that 0.1% of your interrupts are handled, so this isn't
 433          * a big problem.
 434          */
 435         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 436                 return IRQ_NONE;
 437
 438         writel(head, nvmeq->q_db + 1);
 439         nvmeq->cq_head = head;
 440         nvmeq->cq_phase = phase;
 441
 442         return IRQ_HANDLED;
 443 }
 444
 445 static irqreturn_t nvme_irq(int irq, void *data)
 446 {
 447         return nvme_process_cq(data);
 448 }
 449
 450 /*
 451  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 452  * if the result is positive, it's an NVM Express status code
 453  */
 454 static int nvme_submit_sync_cmd(struct nvme_queue *q, struct nvme_command *cmd,
 455                                                                 u32 *result)
 456 {
 457         int cmdid;
 458         struct sync_cmd_info cmdinfo;
 459
 460         cmdinfo.task = current;
 461         cmdinfo.status = -EINTR;
 462
 463         cmdid = alloc_cmdid_killable(q, &cmdinfo, sync_completion_id);
 464         if (cmdid < 0)
 465                 return cmdid;
 466         cmd->common.command_id = cmdid;
 467
 468         set_current_state(TASK_UNINTERRUPTIBLE);
 469         nvme_submit_cmd(q, cmd);
 470         schedule();
 471
 472         if (result)
 473                 *result = cmdinfo.result;
 474
 475         return cmdinfo.status;
 476 }
 477
 478 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 479                                                                 u32 *result)
 480 {
 481         return nvme_submit_sync_cmd(dev->queues[0], cmd, result);
 482 }
 483
 484 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 485 {
 486         int status;
 487         struct nvme_command c;
 488
 489         memset(&c, 0, sizeof(c));
 490         c.delete_queue.opcode = opcode;
 491         c.delete_queue.qid = cpu_to_le16(id);
 492
 493         status = nvme_submit_admin_cmd(dev, &c, NULL);
 494         if (status)
 495                 return -EIO;
 496         return 0;
 497 }
 498
 499 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 500                                                 struct nvme_queue *nvmeq)
 501 {
 502         int status;
 503         struct nvme_command c;
 504         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 505
 506         memset(&c, 0, sizeof(c));
 507         c.create_cq.opcode = nvme_admin_create_cq;
 508         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 509         c.create_cq.cqid = cpu_to_le16(qid);
 510         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 511         c.create_cq.cq_flags = cpu_to_le16(flags);
 512         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 513
 514         status = nvme_submit_admin_cmd(dev, &c, NULL);
 515         if (status)
 516                 return -EIO;
 517         return 0;
 518 }
 519
 520 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 521                                                 struct nvme_queue *nvmeq)
 522 {
 523         int status;
 524         struct nvme_command c;
 525         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 526
 527         memset(&c, 0, sizeof(c));
 528         c.create_sq.opcode = nvme_admin_create_sq;
 529         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 530         c.create_sq.sqid = cpu_to_le16(qid);
 531         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 532         c.create_sq.sq_flags = cpu_to_le16(flags);
 533         c.create_sq.cqid = cpu_to_le16(qid);
 534
 535         status = nvme_submit_admin_cmd(dev, &c, NULL);
 536         if (status)
 537                 return -EIO;
 538         return 0;
 539 }
 540
 541 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 542 {
 543         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 544 }
 545
 546 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 547 {
 548         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 549 }
 550
 551 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 552 {
 553         struct nvme_queue *nvmeq = dev->queues[qid];
 554
 555         free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
 556
 557         /* Don't tell the adapter to delete the admin queue */
 558         if (qid) {
 559                 adapter_delete_sq(dev, qid);
 560                 adapter_delete_cq(dev, qid);
 561         }
 562
 563         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 564                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 565         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 566                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 567         kfree(nvmeq);
 568 }
 569
 570 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 571                                                         int depth, int vector)
 572 {
 573         struct device *dmadev = &dev->pci_dev->dev;
 574         unsigned extra = (depth + BITS_TO_LONGS(depth)) * sizeof(long);
 575         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 576         if (!nvmeq)
 577                 return NULL;
 578
 579         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 580                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 581         if (!nvmeq->cqes)
 582                 goto free_nvmeq;
 583         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 584
 585         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 586                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 587         if (!nvmeq->sq_cmds)
 588                 goto free_cqdma;
 589
 590         nvmeq->q_dmadev = dmadev;
 591         spin_lock_init(&nvmeq->q_lock);
 592         nvmeq->cq_head = 0;
 593         nvmeq->cq_phase = 1;
 594         init_waitqueue_head(&nvmeq->sq_full);
 595         bio_list_init(&nvmeq->sq_cong);
 596         nvmeq->q_db = &dev->dbs[qid * 2];
 597         nvmeq->q_depth = depth;
 598         nvmeq->cq_vector = vector;
 599
 600         return nvmeq;
 601
 602  free_cqdma:
 603         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 604                                                         nvmeq->cq_dma_addr);
 605  free_nvmeq:
 606         kfree(nvmeq);
 607         return NULL;
 608 }
 609
 610 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 611                                                         const char *name)
 612 {
 613         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 614                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 615 }
 616
 617 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 618                                         int qid, int cq_size, int vector)
 619 {
 620         int result;
 621         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 622
 623         result = adapter_alloc_cq(dev, qid, nvmeq);
 624         if (result < 0)
 625                 goto free_nvmeq;
 626
 627         result = adapter_alloc_sq(dev, qid, nvmeq);
 628         if (result < 0)
 629                 goto release_cq;
 630
 631         result = queue_request_irq(dev, nvmeq, "nvme");
 632         if (result < 0)
 633                 goto release_sq;
 634
 635         return nvmeq;
 636
 637  release_sq:
 638         adapter_delete_sq(dev, qid);
 639  release_cq:
 640         adapter_delete_cq(dev, qid);
 641  free_nvmeq:
 642         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 643                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 644         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 645                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 646         kfree(nvmeq);
 647         return NULL;
 648 }
 649
 650 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 651 {
 652         int result;
 653         u32 aqa;
 654         struct nvme_queue *nvmeq;
 655
 656         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 657
 658         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 659
 660         aqa = nvmeq->q_depth - 1;
 661         aqa |= aqa << 16;
 662
 663         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 664         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 665         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 666
 667         writel(aqa, &dev->bar->aqa);
 668         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 669         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 670         writel(dev->ctrl_config, &dev->bar->cc);
 671
 672         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 673                 msleep(100);
 674                 if (fatal_signal_pending(current))
 675                         return -EINTR;
 676         }
 677
 678         result = queue_request_irq(dev, nvmeq, "nvme admin");
 679         dev->queues[0] = nvmeq;
 680         return result;
 681 }
 682
 683 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
 684                                 unsigned long addr, unsigned length,
 685                                 struct scatterlist **sgp)
 686 {
 687         int i, err, count, nents, offset;
 688         struct scatterlist *sg;
 689         struct page **pages;
 690
 691         if (addr & 3)
 692                 return -EINVAL;
 693         if (!length)
 694                 return -EINVAL;
 695
 696         offset = offset_in_page(addr);
 697         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
 698         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
 699
 700         err = get_user_pages_fast(addr, count, 1, pages);
 701         if (err < count) {
 702                 count = err;
 703                 err = -EFAULT;
 704                 goto put_pages;
 705         }
 706
 707         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
 708         sg_init_table(sg, count);
 709         sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
 710         length -= (PAGE_SIZE - offset);
 711         for (i = 1; i < count; i++) {
 712                 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
 713                 length -= PAGE_SIZE;
 714         }
 715
 716         err = -ENOMEM;
 717         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
 718                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 719         if (!nents)
 720                 goto put_pages;
 721
 722         kfree(pages);
 723         *sgp = sg;
 724         return nents;
 725
 726  put_pages:
 727         for (i = 0; i < count; i++)
 728                 put_page(pages[i]);
 729         kfree(pages);
 730         return err;
 731 }
 732
 733 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
 734                                 unsigned long addr, int length,
 735                                 struct scatterlist *sg, int nents)
 736 {
 737         int i, count;
 738
 739         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
 740         dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
 741
 742         for (i = 0; i < count; i++)
 743                 put_page(sg_page(&sg[i]));
 744 }
 745
 746 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
 747                                         unsigned long addr, unsigned length,
 748                                         struct nvme_command *cmd)
 749 {
 750         int err, nents;
 751         struct scatterlist *sg;
 752
 753         nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
 754         if (nents < 0)
 755                 return nents;
 756         nvme_setup_prps(&cmd->common, sg, length);
 757         err = nvme_submit_admin_cmd(dev, cmd, NULL);
 758         nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
 759         return err ? -EIO : 0;
 760 }
 761
 762 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
 763 {
 764         struct nvme_command c;
 765
 766         memset(&c, 0, sizeof(c));
 767         c.identify.opcode = nvme_admin_identify;
 768         c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
 769         c.identify.cns = cpu_to_le32(cns);
 770
 771         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 772 }
 773
 774 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
 775 {
 776         struct nvme_command c;
 777
 778         memset(&c, 0, sizeof(c));
 779         c.features.opcode = nvme_admin_get_features;
 780         c.features.nsid = cpu_to_le32(ns->ns_id);
 781         c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
 782
 783         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 784 }
 785
 786 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
 787 {
 788         struct nvme_dev *dev = ns->dev;
 789         struct nvme_queue *nvmeq;
 790         struct nvme_user_io io;
 791         struct nvme_command c;
 792         unsigned length;
 793         u32 result;
 794         int nents, status;
 795         struct scatterlist *sg;
 796
 797         if (copy_from_user(&io, uio, sizeof(io)))
 798                 return -EFAULT;
 799         length = io.nblocks << io.block_shift;
 800         nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
 801         if (nents < 0)
 802                 return nents;
 803
 804         memset(&c, 0, sizeof(c));
 805         c.rw.opcode = io.opcode;
 806         c.rw.flags = io.flags;
 807         c.rw.nsid = cpu_to_le32(io.nsid);
 808         c.rw.slba = cpu_to_le64(io.slba);
 809         c.rw.length = cpu_to_le16(io.nblocks - 1);
 810         c.rw.control = cpu_to_le16(io.control);
 811         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
 812         c.rw.reftag = cpu_to_le32(io.reftag);   /* XXX: endian? */
 813         c.rw.apptag = cpu_to_le16(io.apptag);
 814         c.rw.appmask = cpu_to_le16(io.appmask);
 815         /* XXX: metadata */
 816         nvme_setup_prps(&c.common, sg, length);
 817
 818         nvmeq = get_nvmeq(ns);
 819         status = nvme_submit_sync_cmd(nvmeq, &c, &result);
 820         put_nvmeq(nvmeq);
 821
 822         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
 823         put_user(result, &uio->result);
 824         return status;
 825 }
 826
 827 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
 828                                                         unsigned long arg)
 829 {
 830         struct nvme_ns *ns = bdev->bd_disk->private_data;
 831
 832         switch (cmd) {
 833         case NVME_IOCTL_IDENTIFY_NS:
 834                 return nvme_identify(ns, arg, 0);
 835         case NVME_IOCTL_IDENTIFY_CTRL:
 836                 return nvme_identify(ns, arg, 1);
 837         case NVME_IOCTL_GET_RANGE_TYPE:
 838                 return nvme_get_range_type(ns, arg);
 839         case NVME_IOCTL_SUBMIT_IO:
 840                 return nvme_submit_io(ns, (void __user *)arg);
 841         default:
 842                 return -ENOTTY;
 843         }
 844 }
 845
 846 static const struct block_device_operations nvme_fops = {
 847         .owner          = THIS_MODULE,
 848         .ioctl          = nvme_ioctl,
 849 };
 850
 851 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
 852                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
 853 {
 854         struct nvme_ns *ns;
 855         struct gendisk *disk;
 856         int lbaf;
 857
 858         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
 859                 return NULL;
 860
 861         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
 862         if (!ns)
 863                 return NULL;
 864         ns->queue = blk_alloc_queue(GFP_KERNEL);
 865         if (!ns->queue)
 866                 goto out_free_ns;
 867         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
 868                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
 869         blk_queue_make_request(ns->queue, nvme_make_request);
 870         ns->dev = dev;
 871         ns->queue->queuedata = ns;
 872
 873         disk = alloc_disk(NVME_MINORS);
 874         if (!disk)
 875                 goto out_free_queue;
 876         ns->ns_id = index;
 877         ns->disk = disk;
 878         lbaf = id->flbas & 0xf;
 879         ns->lba_shift = id->lbaf[lbaf].ds;
 880
 881         disk->major = nvme_major;
 882         disk->minors = NVME_MINORS;
 883         disk->first_minor = NVME_MINORS * index;
 884         disk->fops = &nvme_fops;
 885         disk->private_data = ns;
 886         disk->queue = ns->queue;
 887         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
 888         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
 889
 890         return ns;
 891
 892  out_free_queue:
 893         blk_cleanup_queue(ns->queue);
 894  out_free_ns:
 895         kfree(ns);
 896         return NULL;
 897 }
 898
 899 static void nvme_ns_free(struct nvme_ns *ns)
 900 {
 901         put_disk(ns->disk);
 902         blk_cleanup_queue(ns->queue);
 903         kfree(ns);
 904 }
 905
 906 static int set_queue_count(struct nvme_dev *dev, int count)
 907 {
 908         int status;
 909         u32 result;
 910         struct nvme_command c;
 911         u32 q_count = (count - 1) | ((count - 1) << 16);
 912
 913         memset(&c, 0, sizeof(c));
 914         c.features.opcode = nvme_admin_get_features;
 915         c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
 916         c.features.dword11 = cpu_to_le32(q_count);
 917
 918         status = nvme_submit_admin_cmd(dev, &c, &result);
 919         if (status)
 920                 return -EIO;
 921         return min(result & 0xffff, result >> 16) + 1;
 922 }
 923
 924 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
 925 {
 926         int result, cpu, i, nr_queues;
 927
 928         nr_queues = num_online_cpus();
 929         result = set_queue_count(dev, nr_queues);
 930         if (result < 0)
 931                 return result;
 932         if (result < nr_queues)
 933                 nr_queues = result;
 934
 935         /* Deregister the admin queue's interrupt */
 936         free_irq(dev->entry[0].vector, dev->queues[0]);
 937
 938         for (i = 0; i < nr_queues; i++)
 939                 dev->entry[i].entry = i;
 940         for (;;) {
 941                 result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
 942                 if (result == 0) {
 943                         break;
 944                 } else if (result > 0) {
 945                         nr_queues = result;
 946                         continue;
 947                 } else {
 948                         nr_queues = 1;
 949                         break;
 950                 }
 951         }
 952
 953         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
 954         /* XXX: handle failure here */
 955
 956         cpu = cpumask_first(cpu_online_mask);
 957         for (i = 0; i < nr_queues; i++) {
 958                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
 959                 cpu = cpumask_next(cpu, cpu_online_mask);
 960         }
 961
 962         for (i = 0; i < nr_queues; i++) {
 963                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
 964                                                         NVME_Q_DEPTH, i);
 965                 if (!dev->queues[i + 1])
 966                         return -ENOMEM;
 967                 dev->queue_count++;
 968         }
 969
 970         return 0;
 971 }
 972
 973 static void nvme_free_queues(struct nvme_dev *dev)
 974 {
 975         int i;
 976
 977         for (i = dev->queue_count - 1; i >= 0; i--)
 978                 nvme_free_queue(dev, i);
 979 }
 980
 981 static int __devinit nvme_dev_add(struct nvme_dev *dev)
 982 {
 983         int res, nn, i;
 984         struct nvme_ns *ns, *next;
 985         struct nvme_id_ctrl *ctrl;
 986         void *id;
 987         dma_addr_t dma_addr;
 988         struct nvme_command cid, crt;
 989
 990         res = nvme_setup_io_queues(dev);
 991         if (res)
 992                 return res;
 993
 994         /* XXX: Switch to a SG list once prp2 works */
 995         id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
 996                                                                 GFP_KERNEL);
 997
 998         memset(&cid, 0, sizeof(cid));
 999         cid.identify.opcode = nvme_admin_identify;
1000         cid.identify.nsid = 0;
1001         cid.identify.prp1 = cpu_to_le64(dma_addr);
1002         cid.identify.cns = cpu_to_le32(1);
1003
1004         res = nvme_submit_admin_cmd(dev, &cid, NULL);
1005         if (res) {
1006                 res = -EIO;
1007                 goto out_free;
1008         }
1009
1010         ctrl = id;
1011         nn = le32_to_cpup(&ctrl->nn);
1012         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1013         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1014         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1015
1016         cid.identify.cns = 0;
1017         memset(&crt, 0, sizeof(crt));
1018         crt.features.opcode = nvme_admin_get_features;
1019         crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1020         crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1021
1022         for (i = 0; i < nn; i++) {
1023                 cid.identify.nsid = cpu_to_le32(i);
1024                 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1025                 if (res)
1026                         continue;
1027
1028                 if (((struct nvme_id_ns *)id)->ncap == 0)
1029                         continue;
1030
1031                 crt.features.nsid = cpu_to_le32(i);
1032                 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1033                 if (res)
1034                         continue;
1035
1036                 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1037                 if (ns)
1038                         list_add_tail(&ns->list, &dev->namespaces);
1039         }
1040         list_for_each_entry(ns, &dev->namespaces, list)
1041                 add_disk(ns->disk);
1042
1043         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1044         return 0;
1045
1046  out_free:
1047         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1048                 list_del(&ns->list);
1049                 nvme_ns_free(ns);
1050         }
1051
1052         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1053         return res;
1054 }
1055
1056 static int nvme_dev_remove(struct nvme_dev *dev)
1057 {
1058         struct nvme_ns *ns, *next;
1059
1060         /* TODO: wait all I/O finished or cancel them */
1061
1062         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1063                 list_del(&ns->list);
1064                 del_gendisk(ns->disk);
1065                 nvme_ns_free(ns);
1066         }
1067
1068         nvme_free_queues(dev);
1069
1070         return 0;
1071 }
1072
1073 /* XXX: Use an ida or something to let remove / add work correctly */
1074 static void nvme_set_instance(struct nvme_dev *dev)
1075 {
1076         static int instance;
1077         dev->instance = instance++;
1078 }
1079
1080 static void nvme_release_instance(struct nvme_dev *dev)
1081 {
1082 }
1083
1084 static int __devinit nvme_probe(struct pci_dev *pdev,
1085                                                 const struct pci_device_id *id)
1086 {
1087         int result = -ENOMEM;
1088         struct nvme_dev *dev;
1089
1090         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1091         if (!dev)
1092                 return -ENOMEM;
1093         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1094                                                                 GFP_KERNEL);
1095         if (!dev->entry)
1096                 goto free;
1097         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1098                                                                 GFP_KERNEL);
1099         if (!dev->queues)
1100                 goto free;
1101
1102         INIT_LIST_HEAD(&dev->namespaces);
1103         dev->pci_dev = pdev;
1104         pci_set_drvdata(pdev, dev);
1105         dma_set_mask(&dev->pci_dev->dev, DMA_BIT_MASK(64));
1106         nvme_set_instance(dev);
1107         dev->entry[0].vector = pdev->irq;
1108
1109         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1110         if (!dev->bar) {
1111                 result = -ENOMEM;
1112                 goto disable;
1113         }
1114
1115         result = nvme_configure_admin_queue(dev);
1116         if (result)
1117                 goto unmap;
1118         dev->queue_count++;
1119
1120         result = nvme_dev_add(dev);
1121         if (result)
1122                 goto delete;
1123         return 0;
1124
1125  delete:
1126         nvme_free_queues(dev);
1127  unmap:
1128         iounmap(dev->bar);
1129  disable:
1130         pci_disable_msix(pdev);
1131         nvme_release_instance(dev);
1132  free:
1133         kfree(dev->queues);
1134         kfree(dev->entry);
1135         kfree(dev);
1136         return result;
1137 }
1138
1139 static void __devexit nvme_remove(struct pci_dev *pdev)
1140 {
1141         struct nvme_dev *dev = pci_get_drvdata(pdev);
1142         nvme_dev_remove(dev);
1143         pci_disable_msix(pdev);
1144         iounmap(dev->bar);
1145         nvme_release_instance(dev);
1146         kfree(dev->queues);
1147         kfree(dev->entry);
1148         kfree(dev);
1149 }
1150
1151 /* These functions are yet to be implemented */
1152 #define nvme_error_detected NULL
1153 #define nvme_dump_registers NULL
1154 #define nvme_link_reset NULL
1155 #define nvme_slot_reset NULL
1156 #define nvme_error_resume NULL
1157 #define nvme_suspend NULL
1158 #define nvme_resume NULL
1159
1160 static struct pci_error_handlers nvme_err_handler = {
1161         .error_detected = nvme_error_detected,
1162         .mmio_enabled   = nvme_dump_registers,
1163         .link_reset     = nvme_link_reset,
1164         .slot_reset     = nvme_slot_reset,
1165         .resume         = nvme_error_resume,
1166 };
1167
1168 /* Move to pci_ids.h later */
1169 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1170
1171 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1172         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1173         { 0, }
1174 };
1175 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1176
1177 static struct pci_driver nvme_driver = {
1178         .name           = "nvme",
1179         .id_table       = nvme_id_table,
1180         .probe          = nvme_probe,
1181         .remove         = __devexit_p(nvme_remove),
1182         .suspend        = nvme_suspend,
1183         .resume         = nvme_resume,
1184         .err_handler    = &nvme_err_handler,
1185 };
1186
1187 static int __init nvme_init(void)
1188 {
1189         int result;
1190
1191         nvme_major = register_blkdev(nvme_major, "nvme");
1192         if (nvme_major <= 0)
1193                 return -EBUSY;
1194
1195         result = pci_register_driver(&nvme_driver);
1196         if (!result)
1197                 return 0;
1198
1199         unregister_blkdev(nvme_major, "nvme");
1200         return result;
1201 }
1202
1203 static void __exit nvme_exit(void)
1204 {
1205         pci_unregister_driver(&nvme_driver);
1206         unregister_blkdev(nvme_major, "nvme");
1207 }
1208
1209 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1210 MODULE_LICENSE("GPL");
1211 MODULE_VERSION("0.1");
1212 module_init(nvme_init);
1213 module_exit(nvme_exit);