drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/blkdev.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kernel.h>
  30 #include <linux/mm.h>
  31 #include <linux/module.h>
  32 #include <linux/moduleparam.h>
  33 #include <linux/pci.h>
  34 #include <linux/poison.h>
  35 #include <linux/sched.h>
  36 #include <linux/slab.h>
  37 #include <linux/types.h>
  38 #include <linux/version.h>
  39
  40 #define NVME_Q_DEPTH 1024
  41 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  42 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  43 #define NVME_MINORS 64
  44
  45 static int nvme_major;
  46 module_param(nvme_major, int, 0);
  47
  48 static int use_threaded_interrupts;
  49 module_param(use_threaded_interrupts, int, 0);
  50
  51 /*
  52  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  53  */
  54 struct nvme_dev {
  55         struct nvme_queue **queues;
  56         u32 __iomem *dbs;
  57         struct pci_dev *pci_dev;
  58         int instance;
  59         int queue_count;
  60         u32 ctrl_config;
  61         struct msix_entry *entry;
  62         struct nvme_bar __iomem *bar;
  63         struct list_head namespaces;
  64         char serial[20];
  65         char model[40];
  66         char firmware_rev[8];
  67 };
  68
  69 /*
  70  * An NVM Express namespace is equivalent to a SCSI LUN
  71  */
  72 struct nvme_ns {
  73         struct list_head list;
  74
  75         struct nvme_dev *dev;
  76         struct request_queue *queue;
  77         struct gendisk *disk;
  78
  79         int ns_id;
  80         int lba_shift;
  81 };
  82
  83 /*
  84  * An NVM Express queue.  Each device has at least two (one for admin
  85  * commands and one for I/O commands).
  86  */
  87 struct nvme_queue {
  88         struct device *q_dmadev;
  89         spinlock_t q_lock;
  90         struct nvme_command *sq_cmds;
  91         volatile struct nvme_completion *cqes;
  92         dma_addr_t sq_dma_addr;
  93         dma_addr_t cq_dma_addr;
  94         wait_queue_head_t sq_full;
  95         struct bio_list sq_cong;
  96         u32 __iomem *q_db;
  97         u16 q_depth;
  98         u16 cq_vector;
  99         u16 sq_head;
 100         u16 sq_tail;
 101         u16 cq_head;
 102         u16 cq_phase;
 103         unsigned long cmdid_data[];
 104 };
 105
 106 /*
 107  * Check we didin't inadvertently grow the command struct
 108  */
 109 static inline void _nvme_check_size(void)
 110 {
 111         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 112         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 113         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 114         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 115         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 116         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 117         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 118         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 119         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 120 }
 121
 122 /**
 123  * alloc_cmdid - Allocate a Command ID
 124  * @param nvmeq The queue that will be used for this command
 125  * @param ctx A pointer that will be passed to the handler
 126  * @param handler The ID of the handler to call
 127  *
 128  * Allocate a Command ID for a queue.  The data passed in will
 129  * be passed to the completion handler.  This is implemented by using
 130  * the bottom two bits of the ctx pointer to store the handler ID.
 131  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 132  * We can change this if it becomes a problem.
 133  */
 134 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler)
 135 {
 136         int depth = nvmeq->q_depth;
 137         unsigned long data = (unsigned long)ctx | handler;
 138         int cmdid;
 139
 140         BUG_ON((unsigned long)ctx & 3);
 141
 142         do {
 143                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 144                 if (cmdid >= depth)
 145                         return -EBUSY;
 146         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 147
 148         nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(depth)] = data;
 149         return cmdid;
 150 }
 151
 152 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 153                                                                 int handler)
 154 {
 155         int cmdid;
 156         wait_event_killable(nvmeq->sq_full,
 157                         (cmdid = alloc_cmdid(nvmeq, ctx, handler)) >= 0);
 158         return (cmdid < 0) ? -EINTR : cmdid;
 159 }
 160
 161 /* If you need more than four handlers, you'll need to change how
 162  * alloc_cmdid and nvme_process_cq work.  Consider using a special
 163  * CMD_CTX value instead, if that works for your situation.
 164  */
 165 enum {
 166         sync_completion_id = 0,
 167         bio_completion_id,
 168 };
 169
 170 #define CMD_CTX_BASE            (POISON_POINTER_DELTA + sync_completion_id)
 171 #define CMD_CTX_CANCELLED       (0x2008 + CMD_CTX_BASE)
 172
 173 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 174 {
 175         unsigned long data;
 176
 177         data = nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(nvmeq->q_depth)];
 178         clear_bit(cmdid, nvmeq->cmdid_data);
 179         wake_up(&nvmeq->sq_full);
 180         return data;
 181 }
 182
 183 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
 184 {
 185         nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(nvmeq->q_depth)] =
 186                                                         CMD_CTX_CANCELLED;
 187 }
 188
 189 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 190 {
 191         int qid, cpu = get_cpu();
 192         if (cpu < ns->dev->queue_count)
 193                 qid = cpu + 1;
 194         else
 195                 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
 196         return ns->dev->queues[qid];
 197 }
 198
 199 static void put_nvmeq(struct nvme_queue *nvmeq)
 200 {
 201         put_cpu();
 202 }
 203
 204 /**
 205  * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
 206  * @nvmeq: The queue to use
 207  * @cmd: The command to send
 208  *
 209  * Safe to use from interrupt context
 210  */
 211 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 212 {
 213         unsigned long flags;
 214         u16 tail;
 215         /* XXX: Need to check tail isn't going to overrun head */
 216         spin_lock_irqsave(&nvmeq->q_lock, flags);
 217         tail = nvmeq->sq_tail;
 218         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 219         writel(tail, nvmeq->q_db);
 220         if (++tail == nvmeq->q_depth)
 221                 tail = 0;
 222         nvmeq->sq_tail = tail;
 223         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 224
 225         return 0;
 226 }
 227
 228 struct nvme_req_info {
 229         struct bio *bio;
 230         int nents;
 231         struct scatterlist sg[0];
 232 };
 233
 234 /* XXX: use a mempool */
 235 static struct nvme_req_info *alloc_info(unsigned nseg, gfp_t gfp)
 236 {
 237         return kmalloc(sizeof(struct nvme_req_info) +
 238                         sizeof(struct scatterlist) * nseg, gfp);
 239 }
 240
 241 static void free_info(struct nvme_req_info *info)
 242 {
 243         kfree(info);
 244 }
 245
 246 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 247                                                 struct nvme_completion *cqe)
 248 {
 249         struct nvme_req_info *info = ctx;
 250         struct bio *bio = info->bio;
 251         u16 status = le16_to_cpup(&cqe->status) >> 1;
 252
 253         dma_unmap_sg(nvmeq->q_dmadev, info->sg, info->nents,
 254                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 255         free_info(info);
 256         bio_endio(bio, status ? -EIO : 0);
 257 }
 258
 259 /* length is in bytes */
 260 static void nvme_setup_prps(struct nvme_common_command *cmd,
 261                                         struct scatterlist *sg, int length)
 262 {
 263         int dma_len = sg_dma_len(sg);
 264         u64 dma_addr = sg_dma_address(sg);
 265         int offset = offset_in_page(dma_addr);
 266
 267         cmd->prp1 = cpu_to_le64(dma_addr);
 268         length -= (PAGE_SIZE - offset);
 269         if (length <= 0)
 270                 return;
 271
 272         dma_len -= (PAGE_SIZE - offset);
 273         if (dma_len) {
 274                 dma_addr += (PAGE_SIZE - offset);
 275         } else {
 276                 sg = sg_next(sg);
 277                 dma_addr = sg_dma_address(sg);
 278                 dma_len = sg_dma_len(sg);
 279         }
 280
 281         if (length <= PAGE_SIZE) {
 282                 cmd->prp2 = cpu_to_le64(dma_addr);
 283                 return;
 284         }
 285
 286         /* XXX: support PRP lists */
 287 }
 288
 289 static int nvme_map_bio(struct device *dev, struct nvme_req_info *info,
 290                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 291 {
 292         struct bio_vec *bvec;
 293         struct scatterlist *sg = info->sg;
 294         int i, nsegs;
 295
 296         sg_init_table(sg, psegs);
 297         bio_for_each_segment(bvec, bio, i) {
 298                 sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset);
 299                 /* XXX: handle non-mergable here */
 300                 nsegs++;
 301         }
 302         info->nents = nsegs;
 303
 304         return dma_map_sg(dev, info->sg, info->nents, dma_dir);
 305 }
 306
 307 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 308                                                                 struct bio *bio)
 309 {
 310         struct nvme_command *cmnd;
 311         struct nvme_req_info *info;
 312         enum dma_data_direction dma_dir;
 313         int cmdid;
 314         u16 control;
 315         u32 dsmgmt;
 316         unsigned long flags;
 317         int psegs = bio_phys_segments(ns->queue, bio);
 318
 319         info = alloc_info(psegs, GFP_NOIO);
 320         if (!info)
 321                 goto congestion;
 322         info->bio = bio;
 323
 324         cmdid = alloc_cmdid(nvmeq, info, bio_completion_id);
 325         if (unlikely(cmdid < 0))
 326                 goto free_info;
 327
 328         control = 0;
 329         if (bio->bi_rw & REQ_FUA)
 330                 control |= NVME_RW_FUA;
 331         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 332                 control |= NVME_RW_LR;
 333
 334         dsmgmt = 0;
 335         if (bio->bi_rw & REQ_RAHEAD)
 336                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 337
 338         spin_lock_irqsave(&nvmeq->q_lock, flags);
 339         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 340
 341         memset(cmnd, 0, sizeof(*cmnd));
 342         if (bio_data_dir(bio)) {
 343                 cmnd->rw.opcode = nvme_cmd_write;
 344                 dma_dir = DMA_TO_DEVICE;
 345         } else {
 346                 cmnd->rw.opcode = nvme_cmd_read;
 347                 dma_dir = DMA_FROM_DEVICE;
 348         }
 349
 350         nvme_map_bio(nvmeq->q_dmadev, info, bio, dma_dir, psegs);
 351
 352         cmnd->rw.flags = 1;
 353         cmnd->rw.command_id = cmdid;
 354         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 355         nvme_setup_prps(&cmnd->common, info->sg, bio->bi_size);
 356         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 357         cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
 358         cmnd->rw.control = cpu_to_le16(control);
 359         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 360
 361         writel(nvmeq->sq_tail, nvmeq->q_db);
 362         if (++nvmeq->sq_tail == nvmeq->q_depth)
 363                 nvmeq->sq_tail = 0;
 364
 365         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 366
 367         return 0;
 368
 369  free_info:
 370         free_info(info);
 371  congestion:
 372         return -EBUSY;
 373 }
 374
 375 /*
 376  * NB: return value of non-zero would mean that we were a stacking driver.
 377  * make_request must always succeed.
 378  */
 379 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 380 {
 381         struct nvme_ns *ns = q->queuedata;
 382         struct nvme_queue *nvmeq = get_nvmeq(ns);
 383
 384         if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
 385                 blk_set_queue_congested(q, rw_is_sync(bio->bi_rw));
 386                 bio_list_add(&nvmeq->sq_cong, bio);
 387         }
 388         put_nvmeq(nvmeq);
 389
 390         return 0;
 391 }
 392
 393 struct sync_cmd_info {
 394         struct task_struct *task;
 395         u32 result;
 396         int status;
 397 };
 398
 399 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 400                                                 struct nvme_completion *cqe)
 401 {
 402         struct sync_cmd_info *cmdinfo = ctx;
 403         if ((unsigned long)cmdinfo == CMD_CTX_CANCELLED)
 404                 return;
 405         cmdinfo->result = le32_to_cpup(&cqe->result);
 406         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 407         wake_up_process(cmdinfo->task);
 408 }
 409
 410 typedef void (*completion_fn)(struct nvme_queue *, void *,
 411                                                 struct nvme_completion *);
 412
 413 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 414 {
 415         u16 head, phase;
 416
 417         static const completion_fn completions[4] = {
 418                 [sync_completion_id] = sync_completion,
 419                 [bio_completion_id]  = bio_completion,
 420         };
 421
 422         head = nvmeq->cq_head;
 423         phase = nvmeq->cq_phase;
 424
 425         for (;;) {
 426                 unsigned long data;
 427                 void *ptr;
 428                 unsigned char handler;
 429                 struct nvme_completion cqe = nvmeq->cqes[head];
 430                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 431                         break;
 432                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 433                 if (++head == nvmeq->q_depth) {
 434                         head = 0;
 435                         phase = !phase;
 436                 }
 437
 438                 data = free_cmdid(nvmeq, cqe.command_id);
 439                 handler = data & 3;
 440                 ptr = (void *)(data & ~3UL);
 441                 completions[handler](nvmeq, ptr, &cqe);
 442         }
 443
 444         /* If the controller ignores the cq head doorbell and continuously
 445          * writes to the queue, it is theoretically possible to wrap around
 446          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 447          * requires that 0.1% of your interrupts are handled, so this isn't
 448          * a big problem.
 449          */
 450         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 451                 return IRQ_NONE;
 452
 453         writel(head, nvmeq->q_db + 1);
 454         nvmeq->cq_head = head;
 455         nvmeq->cq_phase = phase;
 456
 457         return IRQ_HANDLED;
 458 }
 459
 460 static irqreturn_t nvme_irq(int irq, void *data)
 461 {
 462         return nvme_process_cq(data);
 463 }
 464
 465 static irqreturn_t nvme_irq_thread(int irq, void *data)
 466 {
 467         irqreturn_t result;
 468         struct nvme_queue *nvmeq = data;
 469         spin_lock(&nvmeq->q_lock);
 470         result = nvme_process_cq(nvmeq);
 471         spin_unlock(&nvmeq->q_lock);
 472         return result;
 473 }
 474
 475 static irqreturn_t nvme_irq_check(int irq, void *data)
 476 {
 477         struct nvme_queue *nvmeq = data;
 478         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 479         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 480                 return IRQ_NONE;
 481         return IRQ_WAKE_THREAD;
 482 }
 483
 484 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 485 {
 486         spin_lock_irq(&nvmeq->q_lock);
 487         cancel_cmdid_data(nvmeq, cmdid);
 488         spin_unlock_irq(&nvmeq->q_lock);
 489 }
 490
 491 /*
 492  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 493  * if the result is positive, it's an NVM Express status code
 494  */
 495 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 496                                         struct nvme_command *cmd, u32 *result)
 497 {
 498         int cmdid;
 499         struct sync_cmd_info cmdinfo;
 500
 501         cmdinfo.task = current;
 502         cmdinfo.status = -EINTR;
 503
 504         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id);
 505         if (cmdid < 0)
 506                 return cmdid;
 507         cmd->common.command_id = cmdid;
 508
 509         set_current_state(TASK_KILLABLE);
 510         nvme_submit_cmd(nvmeq, cmd);
 511         schedule();
 512
 513         if (cmdinfo.status == -EINTR) {
 514                 nvme_abort_command(nvmeq, cmdid);
 515                 return -EINTR;
 516         }
 517
 518         if (result)
 519                 *result = cmdinfo.result;
 520
 521         return cmdinfo.status;
 522 }
 523
 524 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 525                                                                 u32 *result)
 526 {
 527         return nvme_submit_sync_cmd(dev->queues[0], cmd, result);
 528 }
 529
 530 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 531 {
 532         int status;
 533         struct nvme_command c;
 534
 535         memset(&c, 0, sizeof(c));
 536         c.delete_queue.opcode = opcode;
 537         c.delete_queue.qid = cpu_to_le16(id);
 538
 539         status = nvme_submit_admin_cmd(dev, &c, NULL);
 540         if (status)
 541                 return -EIO;
 542         return 0;
 543 }
 544
 545 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 546                                                 struct nvme_queue *nvmeq)
 547 {
 548         int status;
 549         struct nvme_command c;
 550         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 551
 552         memset(&c, 0, sizeof(c));
 553         c.create_cq.opcode = nvme_admin_create_cq;
 554         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 555         c.create_cq.cqid = cpu_to_le16(qid);
 556         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 557         c.create_cq.cq_flags = cpu_to_le16(flags);
 558         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 559
 560         status = nvme_submit_admin_cmd(dev, &c, NULL);
 561         if (status)
 562                 return -EIO;
 563         return 0;
 564 }
 565
 566 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 567                                                 struct nvme_queue *nvmeq)
 568 {
 569         int status;
 570         struct nvme_command c;
 571         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 572
 573         memset(&c, 0, sizeof(c));
 574         c.create_sq.opcode = nvme_admin_create_sq;
 575         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 576         c.create_sq.sqid = cpu_to_le16(qid);
 577         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 578         c.create_sq.sq_flags = cpu_to_le16(flags);
 579         c.create_sq.cqid = cpu_to_le16(qid);
 580
 581         status = nvme_submit_admin_cmd(dev, &c, NULL);
 582         if (status)
 583                 return -EIO;
 584         return 0;
 585 }
 586
 587 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 588 {
 589         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 590 }
 591
 592 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 593 {
 594         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 595 }
 596
 597 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 598 {
 599         struct nvme_queue *nvmeq = dev->queues[qid];
 600
 601         free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
 602
 603         /* Don't tell the adapter to delete the admin queue */
 604         if (qid) {
 605                 adapter_delete_sq(dev, qid);
 606                 adapter_delete_cq(dev, qid);
 607         }
 608
 609         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 610                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 611         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 612                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 613         kfree(nvmeq);
 614 }
 615
 616 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 617                                                         int depth, int vector)
 618 {
 619         struct device *dmadev = &dev->pci_dev->dev;
 620         unsigned extra = (depth + BITS_TO_LONGS(depth)) * sizeof(long);
 621         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 622         if (!nvmeq)
 623                 return NULL;
 624
 625         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 626                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 627         if (!nvmeq->cqes)
 628                 goto free_nvmeq;
 629         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 630
 631         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 632                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 633         if (!nvmeq->sq_cmds)
 634                 goto free_cqdma;
 635
 636         nvmeq->q_dmadev = dmadev;
 637         spin_lock_init(&nvmeq->q_lock);
 638         nvmeq->cq_head = 0;
 639         nvmeq->cq_phase = 1;
 640         init_waitqueue_head(&nvmeq->sq_full);
 641         bio_list_init(&nvmeq->sq_cong);
 642         nvmeq->q_db = &dev->dbs[qid * 2];
 643         nvmeq->q_depth = depth;
 644         nvmeq->cq_vector = vector;
 645
 646         return nvmeq;
 647
 648  free_cqdma:
 649         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 650                                                         nvmeq->cq_dma_addr);
 651  free_nvmeq:
 652         kfree(nvmeq);
 653         return NULL;
 654 }
 655
 656 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 657                                                         const char *name)
 658 {
 659         if (use_threaded_interrupts)
 660                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 661                                         nvme_irq_check, nvme_irq_thread,
 662                                         IRQF_DISABLED | IRQF_SHARED,
 663                                         name, nvmeq);
 664         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 665                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 666 }
 667
 668 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 669                                         int qid, int cq_size, int vector)
 670 {
 671         int result;
 672         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 673
 674         if (!nvmeq)
 675                 return NULL;
 676
 677         result = adapter_alloc_cq(dev, qid, nvmeq);
 678         if (result < 0)
 679                 goto free_nvmeq;
 680
 681         result = adapter_alloc_sq(dev, qid, nvmeq);
 682         if (result < 0)
 683                 goto release_cq;
 684
 685         result = queue_request_irq(dev, nvmeq, "nvme");
 686         if (result < 0)
 687                 goto release_sq;
 688
 689         return nvmeq;
 690
 691  release_sq:
 692         adapter_delete_sq(dev, qid);
 693  release_cq:
 694         adapter_delete_cq(dev, qid);
 695  free_nvmeq:
 696         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 697                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 698         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 699                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 700         kfree(nvmeq);
 701         return NULL;
 702 }
 703
 704 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 705 {
 706         int result;
 707         u32 aqa;
 708         struct nvme_queue *nvmeq;
 709
 710         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 711
 712         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 713         if (!nvmeq)
 714                 return -ENOMEM;
 715
 716         aqa = nvmeq->q_depth - 1;
 717         aqa |= aqa << 16;
 718
 719         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 720         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 721         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 722
 723         writel(0, &dev->bar->cc);
 724         writel(aqa, &dev->bar->aqa);
 725         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 726         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 727         writel(dev->ctrl_config, &dev->bar->cc);
 728
 729         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 730                 msleep(100);
 731                 if (fatal_signal_pending(current))
 732                         return -EINTR;
 733         }
 734
 735         result = queue_request_irq(dev, nvmeq, "nvme admin");
 736         dev->queues[0] = nvmeq;
 737         return result;
 738 }
 739
 740 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
 741                                 unsigned long addr, unsigned length,
 742                                 struct scatterlist **sgp)
 743 {
 744         int i, err, count, nents, offset;
 745         struct scatterlist *sg;
 746         struct page **pages;
 747
 748         if (addr & 3)
 749                 return -EINVAL;
 750         if (!length)
 751                 return -EINVAL;
 752
 753         offset = offset_in_page(addr);
 754         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
 755         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
 756
 757         err = get_user_pages_fast(addr, count, 1, pages);
 758         if (err < count) {
 759                 count = err;
 760                 err = -EFAULT;
 761                 goto put_pages;
 762         }
 763
 764         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
 765         sg_init_table(sg, count);
 766         sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
 767         length -= (PAGE_SIZE - offset);
 768         for (i = 1; i < count; i++) {
 769                 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
 770                 length -= PAGE_SIZE;
 771         }
 772
 773         err = -ENOMEM;
 774         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
 775                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 776         if (!nents)
 777                 goto put_pages;
 778
 779         kfree(pages);
 780         *sgp = sg;
 781         return nents;
 782
 783  put_pages:
 784         for (i = 0; i < count; i++)
 785                 put_page(pages[i]);
 786         kfree(pages);
 787         return err;
 788 }
 789
 790 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
 791                                 unsigned long addr, int length,
 792                                 struct scatterlist *sg, int nents)
 793 {
 794         int i, count;
 795
 796         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
 797         dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
 798
 799         for (i = 0; i < count; i++)
 800                 put_page(sg_page(&sg[i]));
 801 }
 802
 803 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
 804                                         unsigned long addr, unsigned length,
 805                                         struct nvme_command *cmd)
 806 {
 807         int err, nents;
 808         struct scatterlist *sg;
 809
 810         nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
 811         if (nents < 0)
 812                 return nents;
 813         nvme_setup_prps(&cmd->common, sg, length);
 814         err = nvme_submit_admin_cmd(dev, cmd, NULL);
 815         nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
 816         return err ? -EIO : 0;
 817 }
 818
 819 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
 820 {
 821         struct nvme_command c;
 822
 823         memset(&c, 0, sizeof(c));
 824         c.identify.opcode = nvme_admin_identify;
 825         c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
 826         c.identify.cns = cpu_to_le32(cns);
 827
 828         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 829 }
 830
 831 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
 832 {
 833         struct nvme_command c;
 834
 835         memset(&c, 0, sizeof(c));
 836         c.features.opcode = nvme_admin_get_features;
 837         c.features.nsid = cpu_to_le32(ns->ns_id);
 838         c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
 839
 840         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 841 }
 842
 843 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
 844 {
 845         struct nvme_dev *dev = ns->dev;
 846         struct nvme_queue *nvmeq;
 847         struct nvme_user_io io;
 848         struct nvme_command c;
 849         unsigned length;
 850         u32 result;
 851         int nents, status;
 852         struct scatterlist *sg;
 853
 854         if (copy_from_user(&io, uio, sizeof(io)))
 855                 return -EFAULT;
 856         length = io.nblocks << io.block_shift;
 857         nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
 858         if (nents < 0)
 859                 return nents;
 860
 861         memset(&c, 0, sizeof(c));
 862         c.rw.opcode = io.opcode;
 863         c.rw.flags = io.flags;
 864         c.rw.nsid = cpu_to_le32(io.nsid);
 865         c.rw.slba = cpu_to_le64(io.slba);
 866         c.rw.length = cpu_to_le16(io.nblocks - 1);
 867         c.rw.control = cpu_to_le16(io.control);
 868         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
 869         c.rw.reftag = cpu_to_le32(io.reftag);   /* XXX: endian? */
 870         c.rw.apptag = cpu_to_le16(io.apptag);
 871         c.rw.appmask = cpu_to_le16(io.appmask);
 872         /* XXX: metadata */
 873         nvme_setup_prps(&c.common, sg, length);
 874
 875         nvmeq = get_nvmeq(ns);
 876         /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption
 877          * disabled.  We may be preempted at any point, and be rescheduled
 878          * to a different CPU.  That will cause cacheline bouncing, but no
 879          * additional races since q_lock already protects against other CPUs.
 880          */
 881         put_nvmeq(nvmeq);
 882         status = nvme_submit_sync_cmd(nvmeq, &c, &result);
 883
 884         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
 885         put_user(result, &uio->result);
 886         return status;
 887 }
 888
 889 static int nvme_download_firmware(struct nvme_ns *ns,
 890                                                 struct nvme_dlfw __user *udlfw)
 891 {
 892         struct nvme_dev *dev = ns->dev;
 893         struct nvme_dlfw dlfw;
 894         struct nvme_command c;
 895         int nents, status;
 896         struct scatterlist *sg;
 897
 898         if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
 899                 return -EFAULT;
 900         if (dlfw.length >= (1 << 30))
 901                 return -EINVAL;
 902
 903         nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
 904         if (nents < 0)
 905                 return nents;
 906
 907         memset(&c, 0, sizeof(c));
 908         c.dlfw.opcode = nvme_admin_download_fw;
 909         c.dlfw.numd = cpu_to_le32(dlfw.length);
 910         c.dlfw.offset = cpu_to_le32(dlfw.offset);
 911         nvme_setup_prps(&c.common, sg, dlfw.length * 4);
 912
 913         status = nvme_submit_admin_cmd(dev, &c, NULL);
 914         nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
 915         return status;
 916 }
 917
 918 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
 919 {
 920         struct nvme_dev *dev = ns->dev;
 921         struct nvme_command c;
 922
 923         memset(&c, 0, sizeof(c));
 924         c.common.opcode = nvme_admin_activate_fw;
 925         c.common.rsvd10[0] = cpu_to_le32(arg);
 926
 927         return nvme_submit_admin_cmd(dev, &c, NULL);
 928 }
 929
 930 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
 931                                                         unsigned long arg)
 932 {
 933         struct nvme_ns *ns = bdev->bd_disk->private_data;
 934
 935         switch (cmd) {
 936         case NVME_IOCTL_IDENTIFY_NS:
 937                 return nvme_identify(ns, arg, 0);
 938         case NVME_IOCTL_IDENTIFY_CTRL:
 939                 return nvme_identify(ns, arg, 1);
 940         case NVME_IOCTL_GET_RANGE_TYPE:
 941                 return nvme_get_range_type(ns, arg);
 942         case NVME_IOCTL_SUBMIT_IO:
 943                 return nvme_submit_io(ns, (void __user *)arg);
 944         case NVME_IOCTL_DOWNLOAD_FW:
 945                 return nvme_download_firmware(ns, (void __user *)arg);
 946         case NVME_IOCTL_ACTIVATE_FW:
 947                 return nvme_activate_firmware(ns, arg);
 948         default:
 949                 return -ENOTTY;
 950         }
 951 }
 952
 953 static const struct block_device_operations nvme_fops = {
 954         .owner          = THIS_MODULE,
 955         .ioctl          = nvme_ioctl,
 956 };
 957
 958 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
 959                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
 960 {
 961         struct nvme_ns *ns;
 962         struct gendisk *disk;
 963         int lbaf;
 964
 965         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
 966                 return NULL;
 967
 968         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
 969         if (!ns)
 970                 return NULL;
 971         ns->queue = blk_alloc_queue(GFP_KERNEL);
 972         if (!ns->queue)
 973                 goto out_free_ns;
 974         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
 975                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
 976         blk_queue_make_request(ns->queue, nvme_make_request);
 977         ns->dev = dev;
 978         ns->queue->queuedata = ns;
 979
 980         disk = alloc_disk(NVME_MINORS);
 981         if (!disk)
 982                 goto out_free_queue;
 983         ns->ns_id = index;
 984         ns->disk = disk;
 985         lbaf = id->flbas & 0xf;
 986         ns->lba_shift = id->lbaf[lbaf].ds;
 987
 988         disk->major = nvme_major;
 989         disk->minors = NVME_MINORS;
 990         disk->first_minor = NVME_MINORS * index;
 991         disk->fops = &nvme_fops;
 992         disk->private_data = ns;
 993         disk->queue = ns->queue;
 994         disk->driverfs_dev = &dev->pci_dev->dev;
 995         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
 996         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
 997
 998         return ns;
 999
1000  out_free_queue:
1001         blk_cleanup_queue(ns->queue);
1002  out_free_ns:
1003         kfree(ns);
1004         return NULL;
1005 }
1006
1007 static void nvme_ns_free(struct nvme_ns *ns)
1008 {
1009         put_disk(ns->disk);
1010         blk_cleanup_queue(ns->queue);
1011         kfree(ns);
1012 }
1013
1014 static int set_queue_count(struct nvme_dev *dev, int count)
1015 {
1016         int status;
1017         u32 result;
1018         struct nvme_command c;
1019         u32 q_count = (count - 1) | ((count - 1) << 16);
1020
1021         memset(&c, 0, sizeof(c));
1022         c.features.opcode = nvme_admin_get_features;
1023         c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1024         c.features.dword11 = cpu_to_le32(q_count);
1025
1026         status = nvme_submit_admin_cmd(dev, &c, &result);
1027         if (status)
1028                 return -EIO;
1029         return min(result & 0xffff, result >> 16) + 1;
1030 }
1031
1032 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1033 {
1034         int result, cpu, i, nr_queues;
1035
1036         nr_queues = num_online_cpus();
1037         result = set_queue_count(dev, nr_queues);
1038         if (result < 0)
1039                 return result;
1040         if (result < nr_queues)
1041                 nr_queues = result;
1042
1043         /* Deregister the admin queue's interrupt */
1044         free_irq(dev->entry[0].vector, dev->queues[0]);
1045
1046         for (i = 0; i < nr_queues; i++)
1047                 dev->entry[i].entry = i;
1048         for (;;) {
1049                 result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
1050                 if (result == 0) {
1051                         break;
1052                 } else if (result > 0) {
1053                         nr_queues = result;
1054                         continue;
1055                 } else {
1056                         nr_queues = 1;
1057                         break;
1058                 }
1059         }
1060
1061         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1062         /* XXX: handle failure here */
1063
1064         cpu = cpumask_first(cpu_online_mask);
1065         for (i = 0; i < nr_queues; i++) {
1066                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1067                 cpu = cpumask_next(cpu, cpu_online_mask);
1068         }
1069
1070         for (i = 0; i < nr_queues; i++) {
1071                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1072                                                         NVME_Q_DEPTH, i);
1073                 if (!dev->queues[i + 1])
1074                         return -ENOMEM;
1075                 dev->queue_count++;
1076         }
1077
1078         return 0;
1079 }
1080
1081 static void nvme_free_queues(struct nvme_dev *dev)
1082 {
1083         int i;
1084
1085         for (i = dev->queue_count - 1; i >= 0; i--)
1086                 nvme_free_queue(dev, i);
1087 }
1088
1089 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1090 {
1091         int res, nn, i;
1092         struct nvme_ns *ns, *next;
1093         struct nvme_id_ctrl *ctrl;
1094         void *id;
1095         dma_addr_t dma_addr;
1096         struct nvme_command cid, crt;
1097
1098         res = nvme_setup_io_queues(dev);
1099         if (res)
1100                 return res;
1101
1102         /* XXX: Switch to a SG list once prp2 works */
1103         id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1104                                                                 GFP_KERNEL);
1105
1106         memset(&cid, 0, sizeof(cid));
1107         cid.identify.opcode = nvme_admin_identify;
1108         cid.identify.nsid = 0;
1109         cid.identify.prp1 = cpu_to_le64(dma_addr);
1110         cid.identify.cns = cpu_to_le32(1);
1111
1112         res = nvme_submit_admin_cmd(dev, &cid, NULL);
1113         if (res) {
1114                 res = -EIO;
1115                 goto out_free;
1116         }
1117
1118         ctrl = id;
1119         nn = le32_to_cpup(&ctrl->nn);
1120         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1121         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1122         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1123
1124         cid.identify.cns = 0;
1125         memset(&crt, 0, sizeof(crt));
1126         crt.features.opcode = nvme_admin_get_features;
1127         crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1128         crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1129
1130         for (i = 0; i < nn; i++) {
1131                 cid.identify.nsid = cpu_to_le32(i);
1132                 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1133                 if (res)
1134                         continue;
1135
1136                 if (((struct nvme_id_ns *)id)->ncap == 0)
1137                         continue;
1138
1139                 crt.features.nsid = cpu_to_le32(i);
1140                 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1141                 if (res)
1142                         continue;
1143
1144                 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1145                 if (ns)
1146                         list_add_tail(&ns->list, &dev->namespaces);
1147         }
1148         list_for_each_entry(ns, &dev->namespaces, list)
1149                 add_disk(ns->disk);
1150
1151         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1152         return 0;
1153
1154  out_free:
1155         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1156                 list_del(&ns->list);
1157                 nvme_ns_free(ns);
1158         }
1159
1160         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1161         return res;
1162 }
1163
1164 static int nvme_dev_remove(struct nvme_dev *dev)
1165 {
1166         struct nvme_ns *ns, *next;
1167
1168         /* TODO: wait all I/O finished or cancel them */
1169
1170         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1171                 list_del(&ns->list);
1172                 del_gendisk(ns->disk);
1173                 nvme_ns_free(ns);
1174         }
1175
1176         nvme_free_queues(dev);
1177
1178         return 0;
1179 }
1180
1181 /* XXX: Use an ida or something to let remove / add work correctly */
1182 static void nvme_set_instance(struct nvme_dev *dev)
1183 {
1184         static int instance;
1185         dev->instance = instance++;
1186 }
1187
1188 static void nvme_release_instance(struct nvme_dev *dev)
1189 {
1190 }
1191
1192 static int __devinit nvme_probe(struct pci_dev *pdev,
1193                                                 const struct pci_device_id *id)
1194 {
1195         int bars, result = -ENOMEM;
1196         struct nvme_dev *dev;
1197
1198         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1199         if (!dev)
1200                 return -ENOMEM;
1201         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1202                                                                 GFP_KERNEL);
1203         if (!dev->entry)
1204                 goto free;
1205         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1206                                                                 GFP_KERNEL);
1207         if (!dev->queues)
1208                 goto free;
1209
1210         if (pci_enable_device_mem(pdev))
1211                 goto free;
1212         pci_set_master(pdev);
1213         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1214         if (pci_request_selected_regions(pdev, bars, "nvme"))
1215                 goto disable;
1216
1217         INIT_LIST_HEAD(&dev->namespaces);
1218         dev->pci_dev = pdev;
1219         pci_set_drvdata(pdev, dev);
1220         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1221         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1222         nvme_set_instance(dev);
1223         dev->entry[0].vector = pdev->irq;
1224
1225         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1226         if (!dev->bar) {
1227                 result = -ENOMEM;
1228                 goto disable_msix;
1229         }
1230
1231         result = nvme_configure_admin_queue(dev);
1232         if (result)
1233                 goto unmap;
1234         dev->queue_count++;
1235
1236         result = nvme_dev_add(dev);
1237         if (result)
1238                 goto delete;
1239         return 0;
1240
1241  delete:
1242         nvme_free_queues(dev);
1243  unmap:
1244         iounmap(dev->bar);
1245  disable_msix:
1246         pci_disable_msix(pdev);
1247         nvme_release_instance(dev);
1248  disable:
1249         pci_disable_device(pdev);
1250         pci_release_regions(pdev);
1251  free:
1252         kfree(dev->queues);
1253         kfree(dev->entry);
1254         kfree(dev);
1255         return result;
1256 }
1257
1258 static void __devexit nvme_remove(struct pci_dev *pdev)
1259 {
1260         struct nvme_dev *dev = pci_get_drvdata(pdev);
1261         nvme_dev_remove(dev);
1262         pci_disable_msix(pdev);
1263         iounmap(dev->bar);
1264         nvme_release_instance(dev);
1265         pci_disable_device(pdev);
1266         pci_release_regions(pdev);
1267         kfree(dev->queues);
1268         kfree(dev->entry);
1269         kfree(dev);
1270 }
1271
1272 /* These functions are yet to be implemented */
1273 #define nvme_error_detected NULL
1274 #define nvme_dump_registers NULL
1275 #define nvme_link_reset NULL
1276 #define nvme_slot_reset NULL
1277 #define nvme_error_resume NULL
1278 #define nvme_suspend NULL
1279 #define nvme_resume NULL
1280
1281 static struct pci_error_handlers nvme_err_handler = {
1282         .error_detected = nvme_error_detected,
1283         .mmio_enabled   = nvme_dump_registers,
1284         .link_reset     = nvme_link_reset,
1285         .slot_reset     = nvme_slot_reset,
1286         .resume         = nvme_error_resume,
1287 };
1288
1289 /* Move to pci_ids.h later */
1290 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1291
1292 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1293         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1294         { 0, }
1295 };
1296 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1297
1298 static struct pci_driver nvme_driver = {
1299         .name           = "nvme",
1300         .id_table       = nvme_id_table,
1301         .probe          = nvme_probe,
1302         .remove         = __devexit_p(nvme_remove),
1303         .suspend        = nvme_suspend,
1304         .resume         = nvme_resume,
1305         .err_handler    = &nvme_err_handler,
1306 };
1307
1308 static int __init nvme_init(void)
1309 {
1310         int result;
1311
1312         nvme_major = register_blkdev(nvme_major, "nvme");
1313         if (nvme_major <= 0)
1314                 return -EBUSY;
1315
1316         result = pci_register_driver(&nvme_driver);
1317         if (!result)
1318                 return 0;
1319
1320         unregister_blkdev(nvme_major, "nvme");
1321         return result;
1322 }
1323
1324 static void __exit nvme_exit(void)
1325 {
1326         pci_unregister_driver(&nvme_driver);
1327         unregister_blkdev(nvme_major, "nvme");
1328 }
1329
1330 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1331 MODULE_LICENSE("GPL");
1332 MODULE_VERSION("0.2");
1333 module_init(nvme_init);
1334 module_exit(nvme_exit);