2 * Filename: rsxx_priv.h
5 * Authors: Joshua Morris <josh.h.morris@us.ibm.com>
6 * Philip Kelleher <pjk1939@linux.vnet.ibm.com>
8 * (C) Copyright 2013 IBM Corporation
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software Foundation,
22 * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #ifndef __RSXX_PRIV_H__
26 #define __RSXX_PRIV_H__
28 #include <linux/version.h>
29 #include <linux/semaphore.h>
32 #include <linux/interrupt.h>
33 #include <linux/mutex.h>
34 #include <linux/pci.h>
35 #include <linux/spinlock.h>
36 #include <linux/sysfs.h>
37 #include <linux/workqueue.h>
38 #include <linux/bio.h>
39 #include <linux/vmalloc.h>
40 #include <linux/timer.h>
41 #include <linux/ioctl.h>
48 #define PCI_DEVICE_ID_FS70_FLASH 0x04A9
49 #define PCI_DEVICE_ID_FS80_FLASH 0x04AA
51 #define RS70_PCI_REV_SUPPORTED 4
53 #define DRIVER_NAME "rsxx"
54 #define DRIVER_VERSION "4.0"
56 /* Block size is 4096 */
57 #define RSXX_HW_BLK_SHIFT 12
58 #define RSXX_HW_BLK_SIZE (1 << RSXX_HW_BLK_SHIFT)
59 #define RSXX_HW_BLK_MASK (RSXX_HW_BLK_SIZE - 1)
61 #define MAX_CREG_DATA8 32
62 #define LOG_BUF_SIZE8 128
64 #define RSXX_MAX_OUTSTANDING_CMDS 255
65 #define RSXX_CS_IDX_MASK 0xff
67 #define STATUS_BUFFER_SIZE8 4096
68 #define COMMAND_BUFFER_SIZE8 4096
70 #define RSXX_MAX_TARGETS 8
72 struct dma_tracker_list;
74 /* DMA Command/Status Buffer structure */
75 struct rsxx_cs_buffer {
81 struct rsxx_dma_stats {
93 u32 issue_rescheduled;
97 u32 sw_q_depth; /* Number of DMAs on the SW queue. */
98 atomic_t hw_q_depth; /* Number of DMAs queued to HW. */
101 struct rsxx_dma_ctrl {
102 struct rsxx_cardinfo *card;
104 void __iomem *regmap;
105 struct rsxx_cs_buffer status;
106 struct rsxx_cs_buffer cmd;
108 spinlock_t queue_lock;
109 struct list_head queue;
110 struct workqueue_struct *issue_wq;
111 struct work_struct issue_dma_work;
112 struct workqueue_struct *done_wq;
113 struct work_struct dma_done_work;
114 struct timer_list activity_timer;
115 struct dma_tracker_list *trackers;
116 struct rsxx_dma_stats stats;
119 struct rsxx_cardinfo {
122 unsigned int eeh_state;
124 void __iomem *regmap;
126 unsigned int isr_mask;
127 unsigned int ier_mask;
129 struct rsxx_card_cfg config;
132 /* Embedded CPU Communication */
136 struct creg_cmd *active_cmd;
137 struct work_struct done_work;
138 struct list_head queue;
139 unsigned int q_depth;
140 /* Cache the creg status to prevent ioreads */
143 u32 failed_cancel_timer;
146 struct timer_list cmd_timer;
147 struct mutex reset_lock;
152 char tmp[MAX_CREG_DATA8];
153 char buf[LOG_BUF_SIZE8]; /* terminated */
157 struct work_struct event_work;
161 /* Lock the device attach/detach function */
162 struct mutex dev_lock;
164 /* Block Device Variables */
168 struct request_queue *queue;
169 struct gendisk *gendisk;
171 /* Used to convert a byte address to a device address. */
178 unsigned int dma_fault;
183 struct rsxx_dma_ctrl *ctrl;
186 enum rsxx_pci_regmap {
187 HWID = 0x00, /* Hardware Identification Register */
188 SCRATCH = 0x04, /* Scratch/Debug Register */
189 RESET = 0x08, /* Reset Register */
190 ISR = 0x10, /* Interrupt Status Register */
191 IER = 0x14, /* Interrupt Enable Register */
192 IPR = 0x18, /* Interrupt Poll Register */
193 CB_ADD_LO = 0x20, /* Command Host Buffer Address [31:0] */
194 CB_ADD_HI = 0x24, /* Command Host Buffer Address [63:32]*/
195 HW_CMD_IDX = 0x28, /* Hardware Processed Command Index */
196 SW_CMD_IDX = 0x2C, /* Software Processed Command Index */
197 SB_ADD_LO = 0x30, /* Status Host Buffer Address [31:0] */
198 SB_ADD_HI = 0x34, /* Status Host Buffer Address [63:32] */
199 HW_STATUS_CNT = 0x38, /* Hardware Status Counter */
200 SW_STATUS_CNT = 0x3C, /* Deprecated */
201 CREG_CMD = 0x40, /* CPU Command Register */
202 CREG_ADD = 0x44, /* CPU Address Register */
203 CREG_CNT = 0x48, /* CPU Count Register */
204 CREG_STAT = 0x4C, /* CPU Status Register */
205 CREG_DATA0 = 0x50, /* CPU Data Registers */
213 INTR_COAL = 0x70, /* Interrupt Coalescing Register */
214 HW_ERROR = 0x74, /* Card Error Register */
215 PCI_DEBUG0 = 0x78, /* PCI Debug Registers */
223 PCI_POWER_THROTTLE = 0x98,
225 PERF_TIMER_LO = 0xa0,
226 PERF_TIMER_HI = 0xa4,
227 PERF_RD512_LO = 0xa8,
228 PERF_RD512_HI = 0xac,
229 PERF_WR512_LO = 0xb0,
230 PERF_WR512_HI = 0xb4,
235 CR_INTR_DMA0 = 0x00000001,
236 CR_INTR_CREG = 0x00000002,
237 CR_INTR_DMA1 = 0x00000004,
238 CR_INTR_EVENT = 0x00000008,
239 CR_INTR_DMA2 = 0x00000010,
240 CR_INTR_DMA3 = 0x00000020,
241 CR_INTR_DMA4 = 0x00000040,
242 CR_INTR_DMA5 = 0x00000080,
243 CR_INTR_DMA6 = 0x00000100,
244 CR_INTR_DMA7 = 0x00000200,
245 CR_INTR_ALL_C = 0x0000003f,
246 CR_INTR_ALL_G = 0x000003ff,
247 CR_INTR_DMA_ALL = 0x000003f5,
248 CR_INTR_ALL = 0xffffffff,
251 static inline int CR_INTR_DMA(int N)
253 static const unsigned int _CR_INTR_DMA[] = {
254 CR_INTR_DMA0, CR_INTR_DMA1, CR_INTR_DMA2, CR_INTR_DMA3,
255 CR_INTR_DMA4, CR_INTR_DMA5, CR_INTR_DMA6, CR_INTR_DMA7
257 return _CR_INTR_DMA[N];
259 enum rsxx_pci_reset {
260 DMA_QUEUE_RESET = 0x00000001,
263 enum rsxx_hw_fifo_flush {
264 RSXX_FLUSH_BUSY = 0x00000002,
265 RSXX_FLUSH_TIMEOUT = 0x00000004,
268 enum rsxx_pci_revision {
269 RSXX_DISCARD_SUPPORT = 2,
270 RSXX_EEH_SUPPORT = 3,
274 CREG_CMD_TAG_MASK = 0x0000FF00,
275 CREG_OP_WRITE = 0x000000C0,
276 CREG_OP_READ = 0x000000E0,
279 enum rsxx_creg_addr {
280 CREG_ADD_CARD_CMD = 0x80001000,
281 CREG_ADD_CARD_STATE = 0x80001004,
282 CREG_ADD_CARD_SIZE = 0x8000100c,
283 CREG_ADD_CAPABILITIES = 0x80001050,
284 CREG_ADD_LOG = 0x80002000,
285 CREG_ADD_NUM_TARGETS = 0x80003000,
286 CREG_ADD_CONFIG = 0xB0000000,
289 enum rsxx_creg_card_cmd {
290 CARD_CMD_STARTUP = 1,
291 CARD_CMD_SHUTDOWN = 2,
292 CARD_CMD_LOW_LEVEL_FORMAT = 3,
293 CARD_CMD_FPGA_RECONFIG_BR = 4,
294 CARD_CMD_FPGA_RECONFIG_MAIN = 5,
297 CARD_CMD_deprecated = 8,
298 CARD_CMD_UNINITIALIZE = 9,
299 CARD_CMD_DSTROY_EMERGENCY = 10,
300 CARD_CMD_DSTROY_NORMAL = 11,
301 CARD_CMD_DSTROY_EXTENDED = 12,
302 CARD_CMD_DSTROY_ABORT = 13,
305 enum rsxx_card_state {
306 CARD_STATE_SHUTDOWN = 0x00000001,
307 CARD_STATE_STARTING = 0x00000002,
308 CARD_STATE_FORMATTING = 0x00000004,
309 CARD_STATE_UNINITIALIZED = 0x00000008,
310 CARD_STATE_GOOD = 0x00000010,
311 CARD_STATE_SHUTTING_DOWN = 0x00000020,
312 CARD_STATE_FAULT = 0x00000040,
313 CARD_STATE_RD_ONLY_FAULT = 0x00000080,
314 CARD_STATE_DSTROYING = 0x00000100,
323 enum rsxx_creg_flash_lock {
325 CREG_FLASH_UNLOCK = 2,
328 enum rsxx_card_capabilities {
329 CARD_CAP_SUBPAGE_WRITES = 0x00000080,
332 enum rsxx_creg_stat {
333 CREG_STAT_STATUS_MASK = 0x00000003,
334 CREG_STAT_SUCCESS = 0x1,
335 CREG_STAT_ERROR = 0x2,
336 CREG_STAT_CHAR_PENDING = 0x00000004, /* Character I/O pending bit */
337 CREG_STAT_LOG_PENDING = 0x00000008, /* HW log message pending bit */
338 CREG_STAT_TAG_MASK = 0x0000ff00,
341 static inline unsigned int CREG_DATA(int N)
343 return CREG_DATA0 + (N << 2);
346 /*----------------- Convenient Log Wrappers -------------------*/
347 #define CARD_TO_DEV(__CARD) (&(__CARD)->dev->dev)
349 /***** config.c *****/
350 int rsxx_load_config(struct rsxx_cardinfo *card);
353 void rsxx_enable_ier(struct rsxx_cardinfo *card, unsigned int intr);
354 void rsxx_disable_ier(struct rsxx_cardinfo *card, unsigned int intr);
355 void rsxx_enable_ier_and_isr(struct rsxx_cardinfo *card,
357 void rsxx_disable_ier_and_isr(struct rsxx_cardinfo *card,
361 int rsxx_attach_dev(struct rsxx_cardinfo *card);
362 void rsxx_detach_dev(struct rsxx_cardinfo *card);
363 int rsxx_setup_dev(struct rsxx_cardinfo *card);
364 void rsxx_destroy_dev(struct rsxx_cardinfo *card);
365 int rsxx_dev_init(void);
366 void rsxx_dev_cleanup(void);
369 typedef void (*rsxx_dma_cb)(struct rsxx_cardinfo *card,
371 unsigned int status);
372 int rsxx_dma_setup(struct rsxx_cardinfo *card);
373 void rsxx_dma_destroy(struct rsxx_cardinfo *card);
374 int rsxx_dma_init(void);
375 void rsxx_dma_cleanup(void);
376 void rsxx_dma_queue_reset(struct rsxx_cardinfo *card);
377 int rsxx_dma_configure(struct rsxx_cardinfo *card);
378 int rsxx_dma_queue_bio(struct rsxx_cardinfo *card,
383 int rsxx_hw_buffers_init(struct pci_dev *dev, struct rsxx_dma_ctrl *ctrl);
384 int rsxx_eeh_save_issued_dmas(struct rsxx_cardinfo *card);
385 void rsxx_eeh_cancel_dmas(struct rsxx_cardinfo *card);
386 int rsxx_eeh_remap_dmas(struct rsxx_cardinfo *card);
388 /***** cregs.c *****/
389 int rsxx_creg_write(struct rsxx_cardinfo *card, u32 addr,
393 int rsxx_creg_read(struct rsxx_cardinfo *card,
398 int rsxx_read_hw_log(struct rsxx_cardinfo *card);
399 int rsxx_get_card_state(struct rsxx_cardinfo *card,
400 unsigned int *state);
401 int rsxx_get_card_size8(struct rsxx_cardinfo *card, u64 *size8);
402 int rsxx_get_num_targets(struct rsxx_cardinfo *card,
403 unsigned int *n_targets);
404 int rsxx_get_card_capabilities(struct rsxx_cardinfo *card,
406 int rsxx_issue_card_cmd(struct rsxx_cardinfo *card, u32 cmd);
407 int rsxx_creg_setup(struct rsxx_cardinfo *card);
408 void rsxx_creg_destroy(struct rsxx_cardinfo *card);
409 int rsxx_creg_init(void);
410 void rsxx_creg_cleanup(void);
411 int rsxx_reg_access(struct rsxx_cardinfo *card,
412 struct rsxx_reg_access __user *ucmd,
414 void rsxx_eeh_save_issued_creg(struct rsxx_cardinfo *card);
415 void rsxx_kick_creg_queue(struct rsxx_cardinfo *card);
419 #endif /* __DRIVERS_BLOCK_RSXX_H__ */