2 * OMAP L3 Interconnect error handling driver
4 * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Sricharan <r.sricharan@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
27 #include "omap_l3_noc.h"
30 * l3_handle_target() - Handle Target specific parse and reporting
31 * @l3: pointer to l3 struct
32 * @base: base address of clkdm
33 * @flag_mux: flagmux corresponding to the event
34 * @err_src: error source index of the slave (target)
36 * This does the second part of the error interrupt handling:
37 * 3) Parse in the slave information
38 * 4) Print the logged information.
39 * 5) Add dump stack to provide kernel trace.
40 * 6) Clear the source if known.
42 * This handles two types of errors:
43 * 1) Custom errors in L3 :
44 * Target like DMM/FW/EMIF generates SRESP=ERR error
45 * 2) Standard L3 error:
47 * L3 tries to access target while it is idle
49 * - Address hole error:
50 * If DSS/ISS/FDIF/USBHOSTFS access a target where they
51 * do not have connectivity, the error is logged in
52 * their default target which is DMM2.
54 * On High Secure devices, firewall errors are possible and those
55 * can be trapped as well. But the trapping is implemented as part
56 * secure software and hence need not be implemented here.
58 static int l3_handle_target(struct omap_l3 *l3, void __iomem *base,
59 struct l3_flagmux_data *flag_mux, int err_src)
62 u32 std_err_main, clear, masterid;
63 void __iomem *l3_targ_base;
64 void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr;
65 struct l3_target_data *l3_targ_inst;
66 struct l3_masters_data *master;
67 char *target_name, *master_name = "UN IDENTIFIED";
68 char *err_description;
69 char err_string[30] = { 0 };
71 /* We DONOT expect err_src to go out of bounds */
72 BUG_ON(err_src > MAX_CLKDM_TARGETS);
74 if (err_src < flag_mux->num_targ_data) {
75 l3_targ_inst = &flag_mux->l3_targ[err_src];
76 target_name = l3_targ_inst->name;
77 l3_targ_base = base + l3_targ_inst->offset;
79 target_name = L3_TARGET_NOT_SUPPORTED;
82 if (target_name == L3_TARGET_NOT_SUPPORTED)
85 /* Read the stderrlog_main_source from clk domain */
86 l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;
87 l3_targ_slvofslsb = l3_targ_base + L3_TARG_STDERRLOG_SLVOFSLSB;
89 std_err_main = readl_relaxed(l3_targ_stderr);
91 switch (std_err_main & CUSTOM_ERROR) {
93 err_description = "Standard";
94 snprintf(err_string, sizeof(err_string),
95 ": At Address: 0x%08X ",
96 readl_relaxed(l3_targ_slvofslsb));
98 l3_targ_mstaddr = l3_targ_base + L3_TARG_STDERRLOG_MSTADDR;
102 err_description = "Custom";
104 l3_targ_mstaddr = l3_targ_base +
105 L3_TARG_STDERRLOG_CINFO_MSTADDR;
109 /* Nothing to be handled here as of now */
113 /* STDERRLOG_MSTADDR Stores the NTTP master address. */
114 masterid = (readl_relaxed(l3_targ_mstaddr) &
115 l3->mst_addr_mask) >> __ffs(l3->mst_addr_mask);
117 for (k = 0, master = l3->l3_masters; k < l3->num_masters;
119 if (masterid == master->id) {
120 master_name = master->name;
126 "%s:L3 %s Error: MASTER %s TARGET %s%s\n",
129 master_name, target_name,
132 /* clear the std error log*/
133 clear = std_err_main | CLEAR_STDERR_LOG;
134 writel_relaxed(clear, l3_targ_stderr);
140 * l3_interrupt_handler() - interrupt handler for l3 events
142 * @_l3: pointer to l3 structure
144 * Interrupt Handler for L3 error detection.
145 * 1) Identify the L3 clockdomain partition to which the error belongs to.
146 * 2) Identify the slave where the error information is logged
147 * ... handle the slave event..
148 * 7) if the slave is unknown, mask out the slave.
150 static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
152 struct omap_l3 *l3 = _l3;
155 u32 err_reg, mask_val;
156 void __iomem *base, *mask_reg;
157 struct l3_flagmux_data *flag_mux;
159 /* Get the Type of interrupt */
160 inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
162 for (i = 0; i < l3->num_modules; i++) {
164 * Read the regerr register of the clock domain
165 * to determine the source
167 base = l3->l3_base[i];
168 flag_mux = l3->l3_flagmux[i];
169 err_reg = readl_relaxed(base + flag_mux->offset +
170 L3_FLAGMUX_REGERR0 + (inttype << 3));
172 /* Get the corresponding error and analyse */
174 /* Identify the source from control status register */
175 err_src = __ffs(err_reg);
177 ret = l3_handle_target(l3, base, flag_mux, err_src);
180 * Certain plaforms may have "undocumented" status
181 * pending on boot. So dont generate a severe warning
182 * here. Just mask it off to prevent the error from
183 * reoccuring and locking up the system.
187 "L3 %s error: target %d mod:%d %s\n",
188 inttype ? "debug" : "application",
189 err_src, i, "(unclearable)");
191 mask_reg = base + flag_mux->offset +
192 L3_FLAGMUX_MASK0 + (inttype << 3);
193 mask_val = readl_relaxed(mask_reg);
194 mask_val &= ~(1 << err_src);
195 writel_relaxed(mask_val, mask_reg);
198 /* Error found so break the for loop */
205 static const struct of_device_id l3_noc_match[] = {
206 {.compatible = "ti,omap4-l3-noc", .data = &omap_l3_data},
209 MODULE_DEVICE_TABLE(of, l3_noc_match);
211 static int omap_l3_probe(struct platform_device *pdev)
213 const struct of_device_id *of_id;
214 static struct omap_l3 *l3;
217 of_id = of_match_device(l3_noc_match, &pdev->dev);
219 dev_err(&pdev->dev, "OF data missing\n");
223 l3 = devm_kzalloc(&pdev->dev, sizeof(*l3), GFP_KERNEL);
227 memcpy(l3, of_id->data, sizeof(*l3));
228 l3->dev = &pdev->dev;
229 platform_set_drvdata(pdev, l3);
231 /* Get mem resources */
232 for (i = 0; i < l3->num_modules; i++) {
233 struct resource *res = platform_get_resource(pdev,
236 l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
237 if (IS_ERR(l3->l3_base[i])) {
238 dev_err(l3->dev, "ioremap %d failed\n", i);
239 return PTR_ERR(l3->l3_base[i]);
244 * Setup interrupt Handlers
246 l3->debug_irq = platform_get_irq(pdev, 0);
247 ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler,
248 IRQF_DISABLED, "l3-dbg-irq", l3);
250 dev_err(l3->dev, "request_irq failed for %d\n",
255 l3->app_irq = platform_get_irq(pdev, 1);
256 ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler,
257 IRQF_DISABLED, "l3-app-irq", l3);
259 dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq);
264 static struct platform_driver omap_l3_driver = {
265 .probe = omap_l3_probe,
267 .name = "omap_l3_noc",
268 .owner = THIS_MODULE,
269 .of_match_table = of_match_ptr(l3_noc_match),
273 static int __init omap_l3_init(void)
275 return platform_driver_register(&omap_l3_driver);
277 postcore_initcall_sync(omap_l3_init);
279 static void __exit omap_l3_exit(void)
281 platform_driver_unregister(&omap_l3_driver);
283 module_exit(omap_l3_exit);