2 * Copyright 2001-2003 SuSE Labs.
3 * Distributed under the GNU public license, v2.
5 * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge.
6 * It also includes support for the AMD 8151 AGP bridge,
7 * although it doesn't actually do much, as all the real
8 * work is done in the northbridge(s).
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/init.h>
14 #include <linux/agp_backend.h>
15 #include <linux/mmzone.h>
16 #include <asm/page.h> /* PAGE_SIZE */
18 #include <asm/amd_nb.h>
22 /* NVIDIA K8 registers */
23 #define NVIDIA_X86_64_0_APBASE 0x10
24 #define NVIDIA_X86_64_1_APBASE1 0x50
25 #define NVIDIA_X86_64_1_APLIMIT1 0x54
26 #define NVIDIA_X86_64_1_APSIZE 0xa8
27 #define NVIDIA_X86_64_1_APBASE2 0xd8
28 #define NVIDIA_X86_64_1_APLIMIT2 0xdc
30 /* ULi K8 registers */
31 #define ULI_X86_64_BASE_ADDR 0x10
32 #define ULI_X86_64_HTT_FEA_REG 0x50
33 #define ULI_X86_64_ENU_SCR_REG 0x54
35 static struct resource *aperture_resource;
36 static int __initdata agp_try_unsupported = 1;
37 static int agp_bridges_found;
39 static void amd64_tlbflush(struct agp_memory *temp)
44 static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
46 int i, j, num_entries;
49 struct agp_bridge_data *bridge = mem->bridge;
52 num_entries = agp_num_entries();
54 if (type != mem->type)
56 mask_type = bridge->driver->agp_type_to_mask_type(bridge, type);
61 /* Make sure we can fit the range in the gatt table. */
62 /* FIXME: could wrap */
63 if (((unsigned long)pg_start + mem->page_count) > num_entries)
68 /* gatt table should be empty. */
69 while (j < (pg_start + mem->page_count)) {
70 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
75 if (!mem->is_flushed) {
77 mem->is_flushed = true;
80 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
81 tmp = agp_bridge->driver->mask_memory(agp_bridge,
82 page_to_phys(mem->pages[i]),
85 BUG_ON(tmp & 0xffffff0000000ffcULL);
86 pte = (tmp & 0x000000ff00000000ULL) >> 28;
87 pte |=(tmp & 0x00000000fffff000ULL);
88 pte |= GPTE_VALID | GPTE_COHERENT;
90 writel(pte, agp_bridge->gatt_table+j);
91 readl(agp_bridge->gatt_table+j); /* PCI Posting. */
98 * This hack alters the order element according
99 * to the size of a long. It sucks. I totally disown this, even
100 * though it does appear to work for the most part.
102 static struct aper_size_info_32 amd64_aperture_sizes[7] =
104 {32, 8192, 3+(sizeof(long)/8), 0 },
105 {64, 16384, 4+(sizeof(long)/8), 1<<1 },
106 {128, 32768, 5+(sizeof(long)/8), 1<<2 },
107 {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 },
108 {512, 131072, 7+(sizeof(long)/8), 1<<3 },
109 {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3},
110 {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3}
115 * Get the current Aperture size from the x86-64.
116 * Note, that there may be multiple x86-64's, but we just return
117 * the value from the first one we find. The set_size functions
118 * keep the rest coherent anyway. Or at least should do.
120 static int amd64_fetch_size(void)
125 struct aper_size_info_32 *values;
127 dev = k8_northbridges.nb_misc[0];
131 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp);
133 values = A_SIZE_32(amd64_aperture_sizes);
135 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
136 if (temp == values[i].size_value) {
137 agp_bridge->previous_size =
138 agp_bridge->current_size = (void *) (values + i);
140 agp_bridge->aperture_size_idx = i;
141 return values[i].size;
148 * In a multiprocessor x86-64 system, this function gets
149 * called once for each CPU.
151 static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table)
157 /* Address to map to */
158 pci_read_config_dword(hammer, AMD64_GARTAPERTUREBASE, &tmp);
159 aperturebase = tmp << 25;
160 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
162 enable_gart_translation(hammer, gatt_table);
168 static const struct aper_size_info_32 amd_8151_sizes[7] =
170 {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */
171 {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */
172 {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */
173 {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */
174 {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */
175 {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */
176 {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */
179 static int amd_8151_configure(void)
181 unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real);
184 if (!k8_northbridges.gart_supported)
187 /* Configure AGP regs in each x86-64 host bridge. */
188 for (i = 0; i < k8_northbridges.num; i++) {
189 agp_bridge->gart_bus_addr =
190 amd64_configure(k8_northbridges.nb_misc[i],
198 static void amd64_cleanup(void)
203 if (!k8_northbridges.gart_supported)
206 for (i = 0; i < k8_northbridges.num; i++) {
207 struct pci_dev *dev = k8_northbridges.nb_misc[i];
208 /* disable gart translation */
209 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
211 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp);
216 static const struct agp_bridge_driver amd_8151_driver = {
217 .owner = THIS_MODULE,
218 .aperture_sizes = amd_8151_sizes,
219 .size_type = U32_APER_SIZE,
220 .num_aperture_sizes = 7,
221 .needs_scratch_page = true,
222 .configure = amd_8151_configure,
223 .fetch_size = amd64_fetch_size,
224 .cleanup = amd64_cleanup,
225 .tlb_flush = amd64_tlbflush,
226 .mask_memory = agp_generic_mask_memory,
228 .agp_enable = agp_generic_enable,
229 .cache_flush = global_cache_flush,
230 .create_gatt_table = agp_generic_create_gatt_table,
231 .free_gatt_table = agp_generic_free_gatt_table,
232 .insert_memory = amd64_insert_memory,
233 .remove_memory = agp_generic_remove_memory,
234 .alloc_by_type = agp_generic_alloc_by_type,
235 .free_by_type = agp_generic_free_by_type,
236 .agp_alloc_page = agp_generic_alloc_page,
237 .agp_alloc_pages = agp_generic_alloc_pages,
238 .agp_destroy_page = agp_generic_destroy_page,
239 .agp_destroy_pages = agp_generic_destroy_pages,
240 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
243 /* Some basic sanity checks for the aperture. */
244 static int __devinit agp_aperture_valid(u64 aper, u32 size)
246 if (!aperture_valid(aper, size, 32*1024*1024))
249 /* Request the Aperture. This catches cases when someone else
250 already put a mapping in there - happens with some very broken BIOS
252 Maybe better to use pci_assign_resource/pci_enable_device instead
253 trusting the bridges? */
254 if (!aperture_resource &&
255 !(aperture_resource = request_mem_region(aper, size, "aperture"))) {
256 printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n");
263 * W*s centric BIOS sometimes only set up the aperture in the AGP
264 * bridge, not the northbridge. On AMD64 this is handled early
265 * in aperture.c, but when IOMMU is not enabled or we run
266 * on a 32bit kernel this needs to be redone.
267 * Unfortunately it is impossible to fix the aperture here because it's too late
268 * to allocate that much memory. But at least error out cleanly instead of
271 static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
274 u32 aper_low, aper_hi;
277 u32 nb_order, nb_base;
280 pci_read_config_dword(nb, AMD64_GARTAPERTURECTL, &nb_order);
281 nb_order = (nb_order >> 1) & 7;
282 pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base);
283 nb_aper = nb_base << 25;
285 /* Northbridge seems to contain crap. Try the AGP bridge. */
287 pci_read_config_word(agp, cap+0x14, &apsize);
288 if (apsize == 0xffff) {
289 if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order))
295 /* Some BIOS use weird encodings not in the AGPv3 table. */
298 order = 7 - hweight16(apsize);
300 pci_read_config_dword(agp, 0x10, &aper_low);
301 pci_read_config_dword(agp, 0x14, &aper_hi);
302 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
305 * On some sick chips APSIZE is 0. This means it wants 4G
306 * so let double check that order, and lets trust the AMD NB settings
308 if (order >=0 && aper + (32ULL<<(20 + order)) > 0x100000000ULL) {
309 dev_info(&agp->dev, "aperture size %u MB is not right, using settings from NB\n",
314 if (nb_order >= order) {
315 if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order))
319 dev_info(&agp->dev, "aperture from AGP @ %Lx size %u MB\n",
321 if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order))
324 gart_set_size_and_enable(nb, order);
325 pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25);
330 static __devinit int cache_nbs(struct pci_dev *pdev, u32 cap_ptr)
334 if (cache_k8_northbridges() < 0)
337 if (!k8_northbridges.gart_supported)
341 for (i = 0; i < k8_northbridges.num; i++) {
342 struct pci_dev *dev = k8_northbridges.nb_misc[i];
343 if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
344 dev_err(&dev->dev, "no usable aperture found\n");
346 /* should port this to i386 */
347 dev_err(&dev->dev, "consider rebooting with iommu=memaper=2 to get a good aperture\n");
355 /* Handle AMD 8151 quirks */
356 static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
360 switch (pdev->revision) {
361 case 0x01: revstring="A0"; break;
362 case 0x02: revstring="A1"; break;
363 case 0x11: revstring="B0"; break;
364 case 0x12: revstring="B1"; break;
365 case 0x13: revstring="B2"; break;
366 case 0x14: revstring="B3"; break;
367 default: revstring="??"; break;
370 dev_info(&pdev->dev, "AMD 8151 AGP Bridge rev %s\n", revstring);
373 * Work around errata.
374 * Chips before B2 stepping incorrectly reporting v3.5
376 if (pdev->revision < 0x13) {
377 dev_info(&pdev->dev, "correcting AGP revision (reports 3.5, is really 3.0)\n");
378 bridge->major_version = 3;
379 bridge->minor_version = 0;
384 static const struct aper_size_info_32 uli_sizes[7] =
394 static int __devinit uli_agp_init(struct pci_dev *pdev)
396 u32 httfea,baseaddr,enuscr;
397 struct pci_dev *dev1;
399 unsigned size = amd64_fetch_size();
401 dev_info(&pdev->dev, "setting up ULi AGP\n");
402 dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0));
404 dev_info(&pdev->dev, "can't find ULi secondary device\n");
408 for (i = 0; i < ARRAY_SIZE(uli_sizes); i++)
409 if (uli_sizes[i].size == size)
412 if (i == ARRAY_SIZE(uli_sizes)) {
413 dev_info(&pdev->dev, "no ULi size found for %d\n", size);
418 /* shadow x86-64 registers into ULi registers */
419 pci_read_config_dword (k8_northbridges.nb_misc[0], AMD64_GARTAPERTUREBASE,
422 /* if x86-64 aperture base is beyond 4G, exit here */
423 if ((httfea & 0x7fff) >> (32 - 25)) {
428 httfea = (httfea& 0x7fff) << 25;
430 pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr);
431 baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
433 pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr);
435 enuscr= httfea+ (size * 1024 * 1024) - 1;
436 pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);
437 pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);
445 static const struct aper_size_info_32 nforce3_sizes[5] =
447 {512, 131072, 7, 0x00000000 },
448 {256, 65536, 6, 0x00000008 },
449 {128, 32768, 5, 0x0000000C },
450 {64, 16384, 4, 0x0000000E },
451 {32, 8192, 3, 0x0000000F }
454 /* Handle shadow device of the Nvidia NForce3 */
455 /* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */
456 static int nforce3_agp_init(struct pci_dev *pdev)
458 u32 tmp, apbase, apbar, aplimit;
459 struct pci_dev *dev1;
461 unsigned size = amd64_fetch_size();
463 dev_info(&pdev->dev, "setting up Nforce3 AGP\n");
465 dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0));
467 dev_info(&pdev->dev, "can't find Nforce3 secondary device\n");
471 for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++)
472 if (nforce3_sizes[i].size == size)
475 if (i == ARRAY_SIZE(nforce3_sizes)) {
476 dev_info(&pdev->dev, "no NForce3 size found for %d\n", size);
481 pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);
483 tmp |= nforce3_sizes[i].size_value;
484 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
486 /* shadow x86-64 registers into NVIDIA registers */
487 pci_read_config_dword (k8_northbridges.nb_misc[0], AMD64_GARTAPERTUREBASE,
490 /* if x86-64 aperture base is beyond 4G, exit here */
491 if ( (apbase & 0x7fff) >> (32 - 25) ) {
492 dev_info(&pdev->dev, "aperture base > 4G\n");
497 apbase = (apbase & 0x7fff) << 25;
499 pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar);
500 apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
502 pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar);
504 aplimit = apbase + (size * 1024 * 1024) - 1;
505 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase);
506 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit);
507 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);
508 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);
517 static int __devinit agp_amd64_probe(struct pci_dev *pdev,
518 const struct pci_device_id *ent)
520 struct agp_bridge_data *bridge;
524 /* The Highlander principle */
525 if (agp_bridges_found)
528 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
532 /* Could check for AGPv3 here */
534 bridge = agp_alloc_bridge();
538 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
539 pdev->device == PCI_DEVICE_ID_AMD_8151_0) {
540 amd8151_init(pdev, bridge);
542 dev_info(&pdev->dev, "AGP bridge [%04x/%04x]\n",
543 pdev->vendor, pdev->device);
546 bridge->driver = &amd_8151_driver;
548 bridge->capndx = cap_ptr;
550 /* Fill in the mode register */
551 pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
553 if (cache_nbs(pdev, cap_ptr) == -1) {
554 agp_put_bridge(bridge);
558 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
559 int ret = nforce3_agp_init(pdev);
561 agp_put_bridge(bridge);
566 if (pdev->vendor == PCI_VENDOR_ID_AL) {
567 int ret = uli_agp_init(pdev);
569 agp_put_bridge(bridge);
574 pci_set_drvdata(pdev, bridge);
575 err = agp_add_bridge(bridge);
583 static void __devexit agp_amd64_remove(struct pci_dev *pdev)
585 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
587 release_mem_region(virt_to_phys(bridge->gatt_table_real),
588 amd64_aperture_sizes[bridge->aperture_size_idx].size);
589 agp_remove_bridge(bridge);
590 agp_put_bridge(bridge);
597 static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state)
599 pci_save_state(pdev);
600 pci_set_power_state(pdev, pci_choose_state(pdev, state));
605 static int agp_amd64_resume(struct pci_dev *pdev)
607 pci_set_power_state(pdev, PCI_D0);
608 pci_restore_state(pdev);
610 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA)
611 nforce3_agp_init(pdev);
613 return amd_8151_configure();
616 #endif /* CONFIG_PM */
618 static struct pci_device_id agp_amd64_pci_table[] = {
620 .class = (PCI_CLASS_BRIDGE_HOST << 8),
622 .vendor = PCI_VENDOR_ID_AMD,
623 .device = PCI_DEVICE_ID_AMD_8151_0,
624 .subvendor = PCI_ANY_ID,
625 .subdevice = PCI_ANY_ID,
629 .class = (PCI_CLASS_BRIDGE_HOST << 8),
631 .vendor = PCI_VENDOR_ID_AL,
632 .device = PCI_DEVICE_ID_AL_M1689,
633 .subvendor = PCI_ANY_ID,
634 .subdevice = PCI_ANY_ID,
638 .class = (PCI_CLASS_BRIDGE_HOST << 8),
640 .vendor = PCI_VENDOR_ID_VIA,
641 .device = PCI_DEVICE_ID_VIA_K8T800PRO_0,
642 .subvendor = PCI_ANY_ID,
643 .subdevice = PCI_ANY_ID,
647 .class = (PCI_CLASS_BRIDGE_HOST << 8),
649 .vendor = PCI_VENDOR_ID_VIA,
650 .device = PCI_DEVICE_ID_VIA_8385_0,
651 .subvendor = PCI_ANY_ID,
652 .subdevice = PCI_ANY_ID,
654 /* VIA K8M800 / K8N800 */
656 .class = (PCI_CLASS_BRIDGE_HOST << 8),
658 .vendor = PCI_VENDOR_ID_VIA,
659 .device = PCI_DEVICE_ID_VIA_8380_0,
660 .subvendor = PCI_ANY_ID,
661 .subdevice = PCI_ANY_ID,
663 /* VIA K8M890 / K8N890 */
665 .class = (PCI_CLASS_BRIDGE_HOST << 8),
667 .vendor = PCI_VENDOR_ID_VIA,
668 .device = PCI_DEVICE_ID_VIA_VT3336,
669 .subvendor = PCI_ANY_ID,
670 .subdevice = PCI_ANY_ID,
674 .class = (PCI_CLASS_BRIDGE_HOST << 8),
676 .vendor = PCI_VENDOR_ID_VIA,
677 .device = PCI_DEVICE_ID_VIA_3238_0,
678 .subvendor = PCI_ANY_ID,
679 .subdevice = PCI_ANY_ID,
681 /* VIA K8T800/K8M800/K8N800 */
683 .class = (PCI_CLASS_BRIDGE_HOST << 8),
685 .vendor = PCI_VENDOR_ID_VIA,
686 .device = PCI_DEVICE_ID_VIA_838X_1,
687 .subvendor = PCI_ANY_ID,
688 .subdevice = PCI_ANY_ID,
692 .class = (PCI_CLASS_BRIDGE_HOST << 8),
694 .vendor = PCI_VENDOR_ID_NVIDIA,
695 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3,
696 .subvendor = PCI_ANY_ID,
697 .subdevice = PCI_ANY_ID,
700 .class = (PCI_CLASS_BRIDGE_HOST << 8),
702 .vendor = PCI_VENDOR_ID_NVIDIA,
703 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S,
704 .subvendor = PCI_ANY_ID,
705 .subdevice = PCI_ANY_ID,
709 .class = (PCI_CLASS_BRIDGE_HOST << 8),
711 .vendor = PCI_VENDOR_ID_SI,
712 .device = PCI_DEVICE_ID_SI_755,
713 .subvendor = PCI_ANY_ID,
714 .subdevice = PCI_ANY_ID,
718 .class = (PCI_CLASS_BRIDGE_HOST << 8),
720 .vendor = PCI_VENDOR_ID_SI,
721 .device = PCI_DEVICE_ID_SI_760,
722 .subvendor = PCI_ANY_ID,
723 .subdevice = PCI_ANY_ID,
727 .class = (PCI_CLASS_BRIDGE_HOST << 8),
729 .vendor = PCI_VENDOR_ID_AL,
731 .subvendor = PCI_ANY_ID,
732 .subdevice = PCI_ANY_ID,
738 MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
740 static DEFINE_PCI_DEVICE_TABLE(agp_amd64_pci_promisc_table) = {
741 { PCI_DEVICE_CLASS(0, 0) },
745 static struct pci_driver agp_amd64_pci_driver = {
746 .name = "agpgart-amd64",
747 .id_table = agp_amd64_pci_table,
748 .probe = agp_amd64_probe,
749 .remove = agp_amd64_remove,
751 .suspend = agp_amd64_suspend,
752 .resume = agp_amd64_resume,
757 /* Not static due to IOMMU code calling it early. */
758 int __init agp_amd64_init(void)
765 err = pci_register_driver(&agp_amd64_pci_driver);
769 if (agp_bridges_found == 0) {
770 if (!agp_try_unsupported && !agp_try_unsupported_boot) {
771 printk(KERN_INFO PFX "No supported AGP bridge found.\n");
773 printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n");
775 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
780 /* First check that we have at least one AMD64 NB */
781 if (!pci_dev_present(k8_nb_ids))
784 /* Look for any AGP bridge */
785 agp_amd64_pci_driver.id_table = agp_amd64_pci_promisc_table;
786 err = driver_attach(&agp_amd64_pci_driver.driver);
787 if (err == 0 && agp_bridges_found == 0)
793 static int __init agp_amd64_mod_init(void)
796 if (gart_iommu_aperture)
797 return agp_bridges_found ? 0 : -ENODEV;
799 return agp_amd64_init();
802 static void __exit agp_amd64_cleanup(void)
805 if (gart_iommu_aperture)
808 if (aperture_resource)
809 release_resource(aperture_resource);
810 pci_unregister_driver(&agp_amd64_pci_driver);
813 module_init(agp_amd64_mod_init);
814 module_exit(agp_amd64_cleanup);
816 MODULE_AUTHOR("Dave Jones <davej@redhat.com>, Andi Kleen");
817 module_param(agp_try_unsupported, bool, 0);
818 MODULE_LICENSE("GPL");