drivers/char/agp/intel-agp.c

   1 /*
   2  * Intel AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pagemap.h>
  10 #include <linux/agp_backend.h>
  11 #include "agp.h"
  12
  13 /*
  14  * If we have Intel graphics, we're not going to have anything other than
  15  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
  16  * on the Intel IOMMU support (CONFIG_DMAR).
  17  * Only newer chipsets need to bother with this, of course.
  18  */
  19 #ifdef CONFIG_DMAR
  20 #define USE_PCI_DMA_API 1
  21 #endif
  22
  23 #define PCI_DEVICE_ID_INTEL_E7221_HB    0x2588
  24 #define PCI_DEVICE_ID_INTEL_E7221_IG    0x258a
  25 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
  26 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
  27 #define PCI_DEVICE_ID_INTEL_82G35_HB     0x2980
  28 #define PCI_DEVICE_ID_INTEL_82G35_IG     0x2982
  29 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
  30 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
  31 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
  32 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
  33 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
  34 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
  35 #define PCI_DEVICE_ID_INTEL_82965GME_HB     0x2A10
  36 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
  37 #define PCI_DEVICE_ID_INTEL_82945GME_HB     0x27AC
  38 #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
  39 #define PCI_DEVICE_ID_INTEL_IGDGM_HB        0xA010
  40 #define PCI_DEVICE_ID_INTEL_IGDGM_IG        0xA011
  41 #define PCI_DEVICE_ID_INTEL_IGDG_HB         0xA000
  42 #define PCI_DEVICE_ID_INTEL_IGDG_IG         0xA001
  43 #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0
  44 #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2
  45 #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0
  46 #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
  47 #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
  48 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
  49 #define PCI_DEVICE_ID_INTEL_B43_HB          0x2E40
  50 #define PCI_DEVICE_ID_INTEL_B43_IG          0x2E42
  51 #define PCI_DEVICE_ID_INTEL_GM45_HB         0x2A40
  52 #define PCI_DEVICE_ID_INTEL_GM45_IG         0x2A42
  53 #define PCI_DEVICE_ID_INTEL_IGD_E_HB        0x2E00
  54 #define PCI_DEVICE_ID_INTEL_IGD_E_IG        0x2E02
  55 #define PCI_DEVICE_ID_INTEL_Q45_HB          0x2E10
  56 #define PCI_DEVICE_ID_INTEL_Q45_IG          0x2E12
  57 #define PCI_DEVICE_ID_INTEL_G45_HB          0x2E20
  58 #define PCI_DEVICE_ID_INTEL_G45_IG          0x2E22
  59 #define PCI_DEVICE_ID_INTEL_G41_HB          0x2E30
  60 #define PCI_DEVICE_ID_INTEL_G41_IG          0x2E32
  61 #define PCI_DEVICE_ID_INTEL_IGDNG_D_HB      0x0040
  62 #define PCI_DEVICE_ID_INTEL_IGDNG_D_IG      0x0042
  63 #define PCI_DEVICE_ID_INTEL_IGDNG_M_HB      0x0044
  64 #define PCI_DEVICE_ID_INTEL_IGDNG_MA_HB     0x0062
  65 #define PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB    0x006a
  66 #define PCI_DEVICE_ID_INTEL_IGDNG_M_IG      0x0046
  67
  68 /* cover 915 and 945 variants */
  69 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
  70                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
  71                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
  72                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
  73                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
  74                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
  75
  76 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
  77                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
  78                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
  79                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
  80                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
  81                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
  82
  83 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
  84                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
  85                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
  86                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
  87                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
  88
  89 #define IS_IGD (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
  90                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
  91
  92 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
  93                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
  94                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
  95                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
  96                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
  97                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \
  98                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \
  99                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB || \
 100                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MA_HB || \
 101                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB)
 102
 103 extern int agp_memory_reserved;
 104
 105
 106 /* Intel 815 register */
 107 #define INTEL_815_APCONT        0x51
 108 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
 109
 110 /* Intel i820 registers */
 111 #define INTEL_I820_RDCR         0x51
 112 #define INTEL_I820_ERRSTS       0xc8
 113
 114 /* Intel i840 registers */
 115 #define INTEL_I840_MCHCFG       0x50
 116 #define INTEL_I840_ERRSTS       0xc8
 117
 118 /* Intel i850 registers */
 119 #define INTEL_I850_MCHCFG       0x50
 120 #define INTEL_I850_ERRSTS       0xc8
 121
 122 /* intel 915G registers */
 123 #define I915_GMADDR     0x18
 124 #define I915_MMADDR     0x10
 125 #define I915_PTEADDR    0x1C
 126 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
 127 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
 128 #define G33_GMCH_GMS_STOLEN_128M        (0x8 << 4)
 129 #define G33_GMCH_GMS_STOLEN_256M        (0x9 << 4)
 130 #define INTEL_GMCH_GMS_STOLEN_96M       (0xa << 4)
 131 #define INTEL_GMCH_GMS_STOLEN_160M      (0xb << 4)
 132 #define INTEL_GMCH_GMS_STOLEN_224M      (0xc << 4)
 133 #define INTEL_GMCH_GMS_STOLEN_352M      (0xd << 4)
 134
 135 #define I915_IFPADDR    0x60
 136
 137 /* Intel 965G registers */
 138 #define I965_MSAC 0x62
 139 #define I965_IFPADDR    0x70
 140
 141 /* Intel 7505 registers */
 142 #define INTEL_I7505_APSIZE      0x74
 143 #define INTEL_I7505_NCAPID      0x60
 144 #define INTEL_I7505_NISTAT      0x6c
 145 #define INTEL_I7505_ATTBASE     0x78
 146 #define INTEL_I7505_ERRSTS      0x42
 147 #define INTEL_I7505_AGPCTRL     0x70
 148 #define INTEL_I7505_MCHCFG      0x50
 149
 150 static const struct aper_size_info_fixed intel_i810_sizes[] =
 151 {
 152         {64, 16384, 4},
 153         /* The 32M mode still requires a 64k gatt */
 154         {32, 8192, 4}
 155 };
 156
 157 #define AGP_DCACHE_MEMORY       1
 158 #define AGP_PHYS_MEMORY         2
 159 #define INTEL_AGP_CACHED_MEMORY 3
 160
 161 static struct gatt_mask intel_i810_masks[] =
 162 {
 163         {.mask = I810_PTE_VALID, .type = 0},
 164         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
 165         {.mask = I810_PTE_VALID, .type = 0},
 166         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
 167          .type = INTEL_AGP_CACHED_MEMORY}
 168 };
 169
 170 static struct _intel_private {
 171         struct pci_dev *pcidev; /* device one */
 172         u8 __iomem *registers;
 173         u32 __iomem *gtt;               /* I915G */
 174         int num_dcache_entries;
 175         /* gtt_entries is the number of gtt entries that are already mapped
 176          * to stolen memory.  Stolen memory is larger than the memory mapped
 177          * through gtt_entries, as it includes some reserved space for the BIOS
 178          * popup and for the GTT.
 179          */
 180         int gtt_entries;                        /* i830+ */
 181         union {
 182                 void __iomem *i9xx_flush_page;
 183                 void *i8xx_flush_page;
 184         };
 185         struct page *i8xx_page;
 186         struct resource ifp_resource;
 187         int resource_valid;
 188 } intel_private;
 189
 190 #ifdef USE_PCI_DMA_API
 191 static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
 192 {
 193         *ret = pci_map_page(intel_private.pcidev, page, 0,
 194                             PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 195         if (pci_dma_mapping_error(intel_private.pcidev, *ret))
 196                 return -EINVAL;
 197         return 0;
 198 }
 199
 200 static void intel_agp_unmap_page(struct page *page, dma_addr_t dma)
 201 {
 202         pci_unmap_page(intel_private.pcidev, dma,
 203                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 204 }
 205
 206 static void intel_agp_free_sglist(struct agp_memory *mem)
 207 {
 208         struct sg_table st;
 209
 210         st.sgl = mem->sg_list;
 211         st.orig_nents = st.nents = mem->page_count;
 212
 213         sg_free_table(&st);
 214
 215         mem->sg_list = NULL;
 216         mem->num_sg = 0;
 217 }
 218
 219 static int intel_agp_map_memory(struct agp_memory *mem)
 220 {
 221         struct sg_table st;
 222         struct scatterlist *sg;
 223         int i;
 224
 225         DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
 226
 227         if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
 228                 return -ENOMEM;
 229
 230         mem->sg_list = sg = st.sgl;
 231
 232         for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
 233                 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
 234
 235         mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
 236                                  mem->page_count, PCI_DMA_BIDIRECTIONAL);
 237         if (unlikely(!mem->num_sg)) {
 238                 intel_agp_free_sglist(mem);
 239                 return -ENOMEM;
 240         }
 241         return 0;
 242 }
 243
 244 static void intel_agp_unmap_memory(struct agp_memory *mem)
 245 {
 246         DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
 247
 248         pci_unmap_sg(intel_private.pcidev, mem->sg_list,
 249                      mem->page_count, PCI_DMA_BIDIRECTIONAL);
 250         intel_agp_free_sglist(mem);
 251 }
 252
 253 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 254                                         off_t pg_start, int mask_type)
 255 {
 256         struct scatterlist *sg;
 257         int i, j;
 258
 259         j = pg_start;
 260
 261         WARN_ON(!mem->num_sg);
 262
 263         if (mem->num_sg == mem->page_count) {
 264                 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
 265                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 266                                         sg_dma_address(sg), mask_type),
 267                                         intel_private.gtt+j);
 268                         j++;
 269                 }
 270         } else {
 271                 /* sg may merge pages, but we have to seperate
 272                  * per-page addr for GTT */
 273                 unsigned int len, m;
 274
 275                 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
 276                         len = sg_dma_len(sg) / PAGE_SIZE;
 277                         for (m = 0; m < len; m++) {
 278                                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 279                                                                        sg_dma_address(sg) + m * PAGE_SIZE,
 280                                                                        mask_type),
 281                                        intel_private.gtt+j);
 282                                 j++;
 283                         }
 284                 }
 285         }
 286         readl(intel_private.gtt+j-1);
 287 }
 288
 289 #else
 290
 291 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 292                                         off_t pg_start, int mask_type)
 293 {
 294         int i, j;
 295
 296         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 297                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 298                                 page_to_phys(mem->pages[i]), mask_type),
 299                        intel_private.gtt+j);
 300         }
 301
 302         readl(intel_private.gtt+j-1);
 303 }
 304
 305 #endif
 306
 307 static int intel_i810_fetch_size(void)
 308 {
 309         u32 smram_miscc;
 310         struct aper_size_info_fixed *values;
 311
 312         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
 313         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 314
 315         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
 316                 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
 317                 return 0;
 318         }
 319         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
 320                 agp_bridge->previous_size =
 321                         agp_bridge->current_size = (void *) (values + 1);
 322                 agp_bridge->aperture_size_idx = 1;
 323                 return values[1].size;
 324         } else {
 325                 agp_bridge->previous_size =
 326                         agp_bridge->current_size = (void *) (values);
 327                 agp_bridge->aperture_size_idx = 0;
 328                 return values[0].size;
 329         }
 330
 331         return 0;
 332 }
 333
 334 static int intel_i810_configure(void)
 335 {
 336         struct aper_size_info_fixed *current_size;
 337         u32 temp;
 338         int i;
 339
 340         current_size = A_SIZE_FIX(agp_bridge->current_size);
 341
 342         if (!intel_private.registers) {
 343                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 344                 temp &= 0xfff80000;
 345
 346                 intel_private.registers = ioremap(temp, 128 * 4096);
 347                 if (!intel_private.registers) {
 348                         dev_err(&intel_private.pcidev->dev,
 349                                 "can't remap memory\n");
 350                         return -ENOMEM;
 351                 }
 352         }
 353
 354         if ((readl(intel_private.registers+I810_DRAM_CTL)
 355                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 356                 /* This will need to be dynamically assigned */
 357                 dev_info(&intel_private.pcidev->dev,
 358                          "detected 4MB dedicated video ram\n");
 359                 intel_private.num_dcache_entries = 1024;
 360         }
 361         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 362         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 363         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 364         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 365
 366         if (agp_bridge->driver->needs_scratch_page) {
 367                 for (i = 0; i < current_size->num_entries; i++) {
 368                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 369                 }
 370                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
 371         }
 372         global_cache_flush();
 373         return 0;
 374 }
 375
 376 static void intel_i810_cleanup(void)
 377 {
 378         writel(0, intel_private.registers+I810_PGETBL_CTL);
 379         readl(intel_private.registers); /* PCI Posting. */
 380         iounmap(intel_private.registers);
 381 }
 382
 383 static void intel_i810_tlbflush(struct agp_memory *mem)
 384 {
 385         return;
 386 }
 387
 388 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 389 {
 390         return;
 391 }
 392
 393 /* Exists to support ARGB cursors */
 394 static struct page *i8xx_alloc_pages(void)
 395 {
 396         struct page *page;
 397
 398         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 399         if (page == NULL)
 400                 return NULL;
 401
 402         if (set_pages_uc(page, 4) < 0) {
 403                 set_pages_wb(page, 4);
 404                 __free_pages(page, 2);
 405                 return NULL;
 406         }
 407         get_page(page);
 408         atomic_inc(&agp_bridge->current_memory_agp);
 409         return page;
 410 }
 411
 412 static void i8xx_destroy_pages(struct page *page)
 413 {
 414         if (page == NULL)
 415                 return;
 416
 417         set_pages_wb(page, 4);
 418         put_page(page);
 419         __free_pages(page, 2);
 420         atomic_dec(&agp_bridge->current_memory_agp);
 421 }
 422
 423 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
 424                                         int type)
 425 {
 426         if (type < AGP_USER_TYPES)
 427                 return type;
 428         else if (type == AGP_USER_CACHED_MEMORY)
 429                 return INTEL_AGP_CACHED_MEMORY;
 430         else
 431                 return 0;
 432 }
 433
 434 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 435                                 int type)
 436 {
 437         int i, j, num_entries;
 438         void *temp;
 439         int ret = -EINVAL;
 440         int mask_type;
 441
 442         if (mem->page_count == 0)
 443                 goto out;
 444
 445         temp = agp_bridge->current_size;
 446         num_entries = A_SIZE_FIX(temp)->num_entries;
 447
 448         if ((pg_start + mem->page_count) > num_entries)
 449                 goto out_err;
 450
 451
 452         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 453                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
 454                         ret = -EBUSY;
 455                         goto out_err;
 456                 }
 457         }
 458
 459         if (type != mem->type)
 460                 goto out_err;
 461
 462         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 463
 464         switch (mask_type) {
 465         case AGP_DCACHE_MEMORY:
 466                 if (!mem->is_flushed)
 467                         global_cache_flush();
 468                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 469                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
 470                                intel_private.registers+I810_PTE_BASE+(i*4));
 471                 }
 472                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 473                 break;
 474         case AGP_PHYS_MEMORY:
 475         case AGP_NORMAL_MEMORY:
 476                 if (!mem->is_flushed)
 477                         global_cache_flush();
 478                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 479                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 480                                         page_to_phys(mem->pages[i]), mask_type),
 481                                intel_private.registers+I810_PTE_BASE+(j*4));
 482                 }
 483                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 484                 break;
 485         default:
 486                 goto out_err;
 487         }
 488
 489         agp_bridge->driver->tlb_flush(mem);
 490 out:
 491         ret = 0;
 492 out_err:
 493         mem->is_flushed = true;
 494         return ret;
 495 }
 496
 497 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 498                                 int type)
 499 {
 500         int i;
 501
 502         if (mem->page_count == 0)
 503                 return 0;
 504
 505         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 506                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 507         }
 508         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 509
 510         agp_bridge->driver->tlb_flush(mem);
 511         return 0;
 512 }
 513
 514 /*
 515  * The i810/i830 requires a physical address to program its mouse
 516  * pointer into hardware.
 517  * However the Xserver still writes to it through the agp aperture.
 518  */
 519 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 520 {
 521         struct agp_memory *new;
 522         struct page *page;
 523
 524         switch (pg_count) {
 525         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 526                 break;
 527         case 4:
 528                 /* kludge to get 4 physical pages for ARGB cursor */
 529                 page = i8xx_alloc_pages();
 530                 break;
 531         default:
 532                 return NULL;
 533         }
 534
 535         if (page == NULL)
 536                 return NULL;
 537
 538         new = agp_create_memory(pg_count);
 539         if (new == NULL)
 540                 return NULL;
 541
 542         new->pages[0] = page;
 543         if (pg_count == 4) {
 544                 /* kludge to get 4 physical pages for ARGB cursor */
 545                 new->pages[1] = new->pages[0] + 1;
 546                 new->pages[2] = new->pages[1] + 1;
 547                 new->pages[3] = new->pages[2] + 1;
 548         }
 549         new->page_count = pg_count;
 550         new->num_scratch_pages = pg_count;
 551         new->type = AGP_PHYS_MEMORY;
 552         new->physical = page_to_phys(new->pages[0]);
 553         return new;
 554 }
 555
 556 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 557 {
 558         struct agp_memory *new;
 559
 560         if (type == AGP_DCACHE_MEMORY) {
 561                 if (pg_count != intel_private.num_dcache_entries)
 562                         return NULL;
 563
 564                 new = agp_create_memory(1);
 565                 if (new == NULL)
 566                         return NULL;
 567
 568                 new->type = AGP_DCACHE_MEMORY;
 569                 new->page_count = pg_count;
 570                 new->num_scratch_pages = 0;
 571                 agp_free_page_array(new);
 572                 return new;
 573         }
 574         if (type == AGP_PHYS_MEMORY)
 575                 return alloc_agpphysmem_i8xx(pg_count, type);
 576         return NULL;
 577 }
 578
 579 static void intel_i810_free_by_type(struct agp_memory *curr)
 580 {
 581         agp_free_key(curr->key);
 582         if (curr->type == AGP_PHYS_MEMORY) {
 583                 if (curr->page_count == 4)
 584                         i8xx_destroy_pages(curr->pages[0]);
 585                 else {
 586                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 587                                                              AGP_PAGE_DESTROY_UNMAP);
 588                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 589                                                              AGP_PAGE_DESTROY_FREE);
 590                 }
 591                 agp_free_page_array(curr);
 592         }
 593         kfree(curr);
 594 }
 595
 596 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 597                                             dma_addr_t addr, int type)
 598 {
 599         /* Type checking must be done elsewhere */
 600         return addr | bridge->driver->masks[type].mask;
 601 }
 602
 603 static struct aper_size_info_fixed intel_i830_sizes[] =
 604 {
 605         {128, 32768, 5},
 606         /* The 64M mode still requires a 128k gatt */
 607         {64, 16384, 5},
 608         {256, 65536, 6},
 609         {512, 131072, 7},
 610 };
 611
 612 static void intel_i830_init_gtt_entries(void)
 613 {
 614         u16 gmch_ctrl;
 615         int gtt_entries;
 616         u8 rdct;
 617         int local = 0;
 618         static const int ddt[4] = { 0, 16, 32, 64 };
 619         int size; /* reserved space (in kb) at the top of stolen memory */
 620
 621         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 622
 623         if (IS_I965) {
 624                 u32 pgetbl_ctl;
 625                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 626
 627                 /* The 965 has a field telling us the size of the GTT,
 628                  * which may be larger than what is necessary to map the
 629                  * aperture.
 630                  */
 631                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 632                 case I965_PGETBL_SIZE_128KB:
 633                         size = 128;
 634                         break;
 635                 case I965_PGETBL_SIZE_256KB:
 636                         size = 256;
 637                         break;
 638                 case I965_PGETBL_SIZE_512KB:
 639                         size = 512;
 640                         break;
 641                 case I965_PGETBL_SIZE_1MB:
 642                         size = 1024;
 643                         break;
 644                 case I965_PGETBL_SIZE_2MB:
 645                         size = 2048;
 646                         break;
 647                 case I965_PGETBL_SIZE_1_5MB:
 648                         size = 1024 + 512;
 649                         break;
 650                 default:
 651                         dev_info(&intel_private.pcidev->dev,
 652                                  "unknown page table size, assuming 512KB\n");
 653                         size = 512;
 654                 }
 655                 size += 4; /* add in BIOS popup space */
 656         } else if (IS_G33 && !IS_IGD) {
 657         /* G33's GTT size defined in gmch_ctrl */
 658                 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
 659                 case G33_PGETBL_SIZE_1M:
 660                         size = 1024;
 661                         break;
 662                 case G33_PGETBL_SIZE_2M:
 663                         size = 2048;
 664                         break;
 665                 default:
 666                         dev_info(&agp_bridge->dev->dev,
 667                                  "unknown page table size 0x%x, assuming 512KB\n",
 668                                 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
 669                         size = 512;
 670                 }
 671                 size += 4;
 672         } else if (IS_G4X || IS_IGD) {
 673                 /* On 4 series hardware, GTT stolen is separate from graphics
 674                  * stolen, ignore it in stolen gtt entries counting.  However,
 675                  * 4KB of the stolen memory doesn't get mapped to the GTT.
 676                  */
 677                 size = 4;
 678         } else {
 679                 /* On previous hardware, the GTT size was just what was
 680                  * required to map the aperture.
 681                  */
 682                 size = agp_bridge->driver->fetch_size() + 4;
 683         }
 684
 685         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 686             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 687                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 688                 case I830_GMCH_GMS_STOLEN_512:
 689                         gtt_entries = KB(512) - KB(size);
 690                         break;
 691                 case I830_GMCH_GMS_STOLEN_1024:
 692                         gtt_entries = MB(1) - KB(size);
 693                         break;
 694                 case I830_GMCH_GMS_STOLEN_8192:
 695                         gtt_entries = MB(8) - KB(size);
 696                         break;
 697                 case I830_GMCH_GMS_LOCAL:
 698                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 699                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
 700                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 701                         local = 1;
 702                         break;
 703                 default:
 704                         gtt_entries = 0;
 705                         break;
 706                 }
 707         } else {
 708                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 709                 case I855_GMCH_GMS_STOLEN_1M:
 710                         gtt_entries = MB(1) - KB(size);
 711                         break;
 712                 case I855_GMCH_GMS_STOLEN_4M:
 713                         gtt_entries = MB(4) - KB(size);
 714                         break;
 715                 case I855_GMCH_GMS_STOLEN_8M:
 716                         gtt_entries = MB(8) - KB(size);
 717                         break;
 718                 case I855_GMCH_GMS_STOLEN_16M:
 719                         gtt_entries = MB(16) - KB(size);
 720                         break;
 721                 case I855_GMCH_GMS_STOLEN_32M:
 722                         gtt_entries = MB(32) - KB(size);
 723                         break;
 724                 case I915_GMCH_GMS_STOLEN_48M:
 725                         /* Check it's really I915G */
 726                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 727                                 gtt_entries = MB(48) - KB(size);
 728                         else
 729                                 gtt_entries = 0;
 730                         break;
 731                 case I915_GMCH_GMS_STOLEN_64M:
 732                         /* Check it's really I915G */
 733                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 734                                 gtt_entries = MB(64) - KB(size);
 735                         else
 736                                 gtt_entries = 0;
 737                         break;
 738                 case G33_GMCH_GMS_STOLEN_128M:
 739                         if (IS_G33 || IS_I965 || IS_G4X)
 740                                 gtt_entries = MB(128) - KB(size);
 741                         else
 742                                 gtt_entries = 0;
 743                         break;
 744                 case G33_GMCH_GMS_STOLEN_256M:
 745                         if (IS_G33 || IS_I965 || IS_G4X)
 746                                 gtt_entries = MB(256) - KB(size);
 747                         else
 748                                 gtt_entries = 0;
 749                         break;
 750                 case INTEL_GMCH_GMS_STOLEN_96M:
 751                         if (IS_I965 || IS_G4X)
 752                                 gtt_entries = MB(96) - KB(size);
 753                         else
 754                                 gtt_entries = 0;
 755                         break;
 756                 case INTEL_GMCH_GMS_STOLEN_160M:
 757                         if (IS_I965 || IS_G4X)
 758                                 gtt_entries = MB(160) - KB(size);
 759                         else
 760                                 gtt_entries = 0;
 761                         break;
 762                 case INTEL_GMCH_GMS_STOLEN_224M:
 763                         if (IS_I965 || IS_G4X)
 764                                 gtt_entries = MB(224) - KB(size);
 765                         else
 766                                 gtt_entries = 0;
 767                         break;
 768                 case INTEL_GMCH_GMS_STOLEN_352M:
 769                         if (IS_I965 || IS_G4X)
 770                                 gtt_entries = MB(352) - KB(size);
 771                         else
 772                                 gtt_entries = 0;
 773                         break;
 774                 default:
 775                         gtt_entries = 0;
 776                         break;
 777                 }
 778         }
 779         if (gtt_entries > 0) {
 780                 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
 781                        gtt_entries / KB(1), local ? "local" : "stolen");
 782                 gtt_entries /= KB(4);
 783         } else {
 784                 dev_info(&agp_bridge->dev->dev,
 785                        "no pre-allocated video memory detected\n");
 786                 gtt_entries = 0;
 787         }
 788
 789         intel_private.gtt_entries = gtt_entries;
 790 }
 791
 792 static void intel_i830_fini_flush(void)
 793 {
 794         kunmap(intel_private.i8xx_page);
 795         intel_private.i8xx_flush_page = NULL;
 796         unmap_page_from_agp(intel_private.i8xx_page);
 797
 798         __free_page(intel_private.i8xx_page);
 799         intel_private.i8xx_page = NULL;
 800 }
 801
 802 static void intel_i830_setup_flush(void)
 803 {
 804         /* return if we've already set the flush mechanism up */
 805         if (intel_private.i8xx_page)
 806                 return;
 807
 808         intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
 809         if (!intel_private.i8xx_page)
 810                 return;
 811
 812         intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
 813         if (!intel_private.i8xx_flush_page)
 814                 intel_i830_fini_flush();
 815 }
 816
 817 static void
 818 do_wbinvd(void *null)
 819 {
 820         wbinvd();
 821 }
 822
 823 /* The chipset_flush interface needs to get data that has already been
 824  * flushed out of the CPU all the way out to main memory, because the GPU
 825  * doesn't snoop those buffers.
 826  *
 827  * The 8xx series doesn't have the same lovely interface for flushing the
 828  * chipset write buffers that the later chips do. According to the 865
 829  * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
 830  * that buffer out, we just fill 1KB and clflush it out, on the assumption
 831  * that it'll push whatever was in there out.  It appears to work.
 832  */
 833 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
 834 {
 835         unsigned int *pg = intel_private.i8xx_flush_page;
 836
 837         memset(pg, 0, 1024);
 838
 839         if (cpu_has_clflush) {
 840                 clflush_cache_range(pg, 1024);
 841         } else {
 842                 if (on_each_cpu(do_wbinvd, NULL, 1) != 0)
 843                         printk(KERN_ERR "Timed out waiting for cache flush.\n");
 844         }
 845 }
 846
 847 /* The intel i830 automatically initializes the agp aperture during POST.
 848  * Use the memory already set aside for in the GTT.
 849  */
 850 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 851 {
 852         int page_order;
 853         struct aper_size_info_fixed *size;
 854         int num_entries;
 855         u32 temp;
 856
 857         size = agp_bridge->current_size;
 858         page_order = size->page_order;
 859         num_entries = size->num_entries;
 860         agp_bridge->gatt_table_real = NULL;
 861
 862         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 863         temp &= 0xfff80000;
 864
 865         intel_private.registers = ioremap(temp, 128 * 4096);
 866         if (!intel_private.registers)
 867                 return -ENOMEM;
 868
 869         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 870         global_cache_flush();   /* FIXME: ?? */
 871
 872         /* we have to call this as early as possible after the MMIO base address is known */
 873         intel_i830_init_gtt_entries();
 874
 875         agp_bridge->gatt_table = NULL;
 876
 877         agp_bridge->gatt_bus_addr = temp;
 878
 879         return 0;
 880 }
 881
 882 /* Return the gatt table to a sane state. Use the top of stolen
 883  * memory for the GTT.
 884  */
 885 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
 886 {
 887         return 0;
 888 }
 889
 890 static int intel_i830_fetch_size(void)
 891 {
 892         u16 gmch_ctrl;
 893         struct aper_size_info_fixed *values;
 894
 895         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 896
 897         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
 898             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
 899                 /* 855GM/852GM/865G has 128MB aperture size */
 900                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 901                 agp_bridge->aperture_size_idx = 0;
 902                 return values[0].size;
 903         }
 904
 905         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 906
 907         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
 908                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 909                 agp_bridge->aperture_size_idx = 0;
 910                 return values[0].size;
 911         } else {
 912                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
 913                 agp_bridge->aperture_size_idx = 1;
 914                 return values[1].size;
 915         }
 916
 917         return 0;
 918 }
 919
 920 static int intel_i830_configure(void)
 921 {
 922         struct aper_size_info_fixed *current_size;
 923         u32 temp;
 924         u16 gmch_ctrl;
 925         int i;
 926
 927         current_size = A_SIZE_FIX(agp_bridge->current_size);
 928
 929         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 930         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 931
 932         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 933         gmch_ctrl |= I830_GMCH_ENABLED;
 934         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
 935
 936         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 937         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 938
 939         if (agp_bridge->driver->needs_scratch_page) {
 940                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 941                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 942                 }
 943                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
 944         }
 945
 946         global_cache_flush();
 947
 948         intel_i830_setup_flush();
 949         return 0;
 950 }
 951
 952 static void intel_i830_cleanup(void)
 953 {
 954         iounmap(intel_private.registers);
 955 }
 956
 957 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
 958                                      int type)
 959 {
 960         int i, j, num_entries;
 961         void *temp;
 962         int ret = -EINVAL;
 963         int mask_type;
 964
 965         if (mem->page_count == 0)
 966                 goto out;
 967
 968         temp = agp_bridge->current_size;
 969         num_entries = A_SIZE_FIX(temp)->num_entries;
 970
 971         if (pg_start < intel_private.gtt_entries) {
 972                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
 973                            "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
 974                            pg_start, intel_private.gtt_entries);
 975
 976                 dev_info(&intel_private.pcidev->dev,
 977                          "trying to insert into local/stolen memory\n");
 978                 goto out_err;
 979         }
 980
 981         if ((pg_start + mem->page_count) > num_entries)
 982                 goto out_err;
 983
 984         /* The i830 can't check the GTT for entries since its read only,
 985          * depend on the caller to make the correct offset decisions.
 986          */
 987
 988         if (type != mem->type)
 989                 goto out_err;
 990
 991         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 992
 993         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 994             mask_type != INTEL_AGP_CACHED_MEMORY)
 995                 goto out_err;
 996
 997         if (!mem->is_flushed)
 998                 global_cache_flush();
 999
1000         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1001                 writel(agp_bridge->driver->mask_memory(agp_bridge,
1002                                 page_to_phys(mem->pages[i]), mask_type),
1003                        intel_private.registers+I810_PTE_BASE+(j*4));
1004         }
1005         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
1006         agp_bridge->driver->tlb_flush(mem);
1007
1008 out:
1009         ret = 0;
1010 out_err:
1011         mem->is_flushed = true;
1012         return ret;
1013 }
1014
1015 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
1016                                      int type)
1017 {
1018         int i;
1019
1020         if (mem->page_count == 0)
1021                 return 0;
1022
1023         if (pg_start < intel_private.gtt_entries) {
1024                 dev_info(&intel_private.pcidev->dev,
1025                          "trying to disable local/stolen memory\n");
1026                 return -EINVAL;
1027         }
1028
1029         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1030                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1031         }
1032         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1033
1034         agp_bridge->driver->tlb_flush(mem);
1035         return 0;
1036 }
1037
1038 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
1039 {
1040         if (type == AGP_PHYS_MEMORY)
1041                 return alloc_agpphysmem_i8xx(pg_count, type);
1042         /* always return NULL for other allocation types for now */
1043         return NULL;
1044 }
1045
1046 static int intel_alloc_chipset_flush_resource(void)
1047 {
1048         int ret;
1049         ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1050                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1051                                      pcibios_align_resource, agp_bridge->dev);
1052
1053         return ret;
1054 }
1055
1056 static void intel_i915_setup_chipset_flush(void)
1057 {
1058         int ret;
1059         u32 temp;
1060
1061         pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
1062         if (!(temp & 0x1)) {
1063                 intel_alloc_chipset_flush_resource();
1064                 intel_private.resource_valid = 1;
1065                 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1066         } else {
1067                 temp &= ~1;
1068
1069                 intel_private.resource_valid = 1;
1070                 intel_private.ifp_resource.start = temp;
1071                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1072                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1073                 /* some BIOSes reserve this area in a pnp some don't */
1074                 if (ret)
1075                         intel_private.resource_valid = 0;
1076         }
1077 }
1078
1079 static void intel_i965_g33_setup_chipset_flush(void)
1080 {
1081         u32 temp_hi, temp_lo;
1082         int ret;
1083
1084         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
1085         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
1086
1087         if (!(temp_lo & 0x1)) {
1088
1089                 intel_alloc_chipset_flush_resource();
1090
1091                 intel_private.resource_valid = 1;
1092                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
1093                         upper_32_bits(intel_private.ifp_resource.start));
1094                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1095         } else {
1096                 u64 l64;
1097
1098                 temp_lo &= ~0x1;
1099                 l64 = ((u64)temp_hi << 32) | temp_lo;
1100
1101                 intel_private.resource_valid = 1;
1102                 intel_private.ifp_resource.start = l64;
1103                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1104                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1105                 /* some BIOSes reserve this area in a pnp some don't */
1106                 if (ret)
1107                         intel_private.resource_valid = 0;
1108         }
1109 }
1110
1111 static void intel_i9xx_setup_flush(void)
1112 {
1113         /* return if already configured */
1114         if (intel_private.ifp_resource.start)
1115                 return;
1116
1117         /* setup a resource for this object */
1118         intel_private.ifp_resource.name = "Intel Flush Page";
1119         intel_private.ifp_resource.flags = IORESOURCE_MEM;
1120
1121         /* Setup chipset flush for 915 */
1122         if (IS_I965 || IS_G33 || IS_G4X) {
1123                 intel_i965_g33_setup_chipset_flush();
1124         } else {
1125                 intel_i915_setup_chipset_flush();
1126         }
1127
1128         if (intel_private.ifp_resource.start) {
1129                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1130                 if (!intel_private.i9xx_flush_page)
1131                         dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
1132         }
1133 }
1134
1135 static int intel_i915_configure(void)
1136 {
1137         struct aper_size_info_fixed *current_size;
1138         u32 temp;
1139         u16 gmch_ctrl;
1140         int i;
1141
1142         current_size = A_SIZE_FIX(agp_bridge->current_size);
1143
1144         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1145
1146         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1147
1148         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1149         gmch_ctrl |= I830_GMCH_ENABLED;
1150         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1151
1152         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1153         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1154
1155         if (agp_bridge->driver->needs_scratch_page) {
1156                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
1157                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
1158                 }
1159                 readl(intel_private.gtt+i-1);   /* PCI Posting. */
1160         }
1161
1162         global_cache_flush();
1163
1164         intel_i9xx_setup_flush();
1165
1166 #ifdef USE_PCI_DMA_API
1167         if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36)))
1168                 dev_err(&intel_private.pcidev->dev,
1169                         "set gfx device dma mask 36bit failed!\n");
1170 #endif
1171
1172         return 0;
1173 }
1174
1175 static void intel_i915_cleanup(void)
1176 {
1177         if (intel_private.i9xx_flush_page)
1178                 iounmap(intel_private.i9xx_flush_page);
1179         if (intel_private.resource_valid)
1180                 release_resource(&intel_private.ifp_resource);
1181         intel_private.ifp_resource.start = 0;
1182         intel_private.resource_valid = 0;
1183         iounmap(intel_private.gtt);
1184         iounmap(intel_private.registers);
1185 }
1186
1187 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1188 {
1189         if (intel_private.i9xx_flush_page)
1190                 writel(1, intel_private.i9xx_flush_page);
1191 }
1192
1193 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1194                                      int type)
1195 {
1196         int num_entries;
1197         void *temp;
1198         int ret = -EINVAL;
1199         int mask_type;
1200
1201         if (mem->page_count == 0)
1202                 goto out;
1203
1204         temp = agp_bridge->current_size;
1205         num_entries = A_SIZE_FIX(temp)->num_entries;
1206
1207         if (pg_start < intel_private.gtt_entries) {
1208                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1209                            "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1210                            pg_start, intel_private.gtt_entries);
1211
1212                 dev_info(&intel_private.pcidev->dev,
1213                          "trying to insert into local/stolen memory\n");
1214                 goto out_err;
1215         }
1216
1217         if ((pg_start + mem->page_count) > num_entries)
1218                 goto out_err;
1219
1220         /* The i915 can't check the GTT for entries since it's read only;
1221          * depend on the caller to make the correct offset decisions.
1222          */
1223
1224         if (type != mem->type)
1225                 goto out_err;
1226
1227         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1228
1229         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1230             mask_type != INTEL_AGP_CACHED_MEMORY)
1231                 goto out_err;
1232
1233         if (!mem->is_flushed)
1234                 global_cache_flush();
1235
1236         intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1237         agp_bridge->driver->tlb_flush(mem);
1238
1239  out:
1240         ret = 0;
1241  out_err:
1242         mem->is_flushed = true;
1243         return ret;
1244 }
1245
1246 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1247                                      int type)
1248 {
1249         int i;
1250
1251         if (mem->page_count == 0)
1252                 return 0;
1253
1254         if (pg_start < intel_private.gtt_entries) {
1255                 dev_info(&intel_private.pcidev->dev,
1256                          "trying to disable local/stolen memory\n");
1257                 return -EINVAL;
1258         }
1259
1260         for (i = pg_start; i < (mem->page_count + pg_start); i++)
1261                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1262
1263         readl(intel_private.gtt+i-1);
1264
1265         agp_bridge->driver->tlb_flush(mem);
1266         return 0;
1267 }
1268
1269 /* Return the aperture size by just checking the resource length.  The effect
1270  * described in the spec of the MSAC registers is just changing of the
1271  * resource size.
1272  */
1273 static int intel_i9xx_fetch_size(void)
1274 {
1275         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1276         int aper_size; /* size in megabytes */
1277         int i;
1278
1279         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1280
1281         for (i = 0; i < num_sizes; i++) {
1282                 if (aper_size == intel_i830_sizes[i].size) {
1283                         agp_bridge->current_size = intel_i830_sizes + i;
1284                         agp_bridge->previous_size = agp_bridge->current_size;
1285                         return aper_size;
1286                 }
1287         }
1288
1289         return 0;
1290 }
1291
1292 /* The intel i915 automatically initializes the agp aperture during POST.
1293  * Use the memory already set aside for in the GTT.
1294  */
1295 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1296 {
1297         int page_order;
1298         struct aper_size_info_fixed *size;
1299         int num_entries;
1300         u32 temp, temp2;
1301         int gtt_map_size = 256 * 1024;
1302
1303         size = agp_bridge->current_size;
1304         page_order = size->page_order;
1305         num_entries = size->num_entries;
1306         agp_bridge->gatt_table_real = NULL;
1307
1308         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1309         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1310
1311         if (IS_G33)
1312             gtt_map_size = 1024 * 1024; /* 1M on G33 */
1313         intel_private.gtt = ioremap(temp2, gtt_map_size);
1314         if (!intel_private.gtt)
1315                 return -ENOMEM;
1316
1317         temp &= 0xfff80000;
1318
1319         intel_private.registers = ioremap(temp, 128 * 4096);
1320         if (!intel_private.registers) {
1321                 iounmap(intel_private.gtt);
1322                 return -ENOMEM;
1323         }
1324
1325         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1326         global_cache_flush();   /* FIXME: ? */
1327
1328         /* we have to call this as early as possible after the MMIO base address is known */
1329         intel_i830_init_gtt_entries();
1330
1331         agp_bridge->gatt_table = NULL;
1332
1333         agp_bridge->gatt_bus_addr = temp;
1334
1335         return 0;
1336 }
1337
1338 /*
1339  * The i965 supports 36-bit physical addresses, but to keep
1340  * the format of the GTT the same, the bits that don't fit
1341  * in a 32-bit word are shifted down to bits 4..7.
1342  *
1343  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1344  * is always zero on 32-bit architectures, so no need to make
1345  * this conditional.
1346  */
1347 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1348                                             dma_addr_t addr, int type)
1349 {
1350         /* Shift high bits down */
1351         addr |= (addr >> 28) & 0xf0;
1352
1353         /* Type checking must be done elsewhere */
1354         return addr | bridge->driver->masks[type].mask;
1355 }
1356
1357 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1358 {
1359         switch (agp_bridge->dev->device) {
1360         case PCI_DEVICE_ID_INTEL_GM45_HB:
1361         case PCI_DEVICE_ID_INTEL_IGD_E_HB:
1362         case PCI_DEVICE_ID_INTEL_Q45_HB:
1363         case PCI_DEVICE_ID_INTEL_G45_HB:
1364         case PCI_DEVICE_ID_INTEL_G41_HB:
1365         case PCI_DEVICE_ID_INTEL_B43_HB:
1366         case PCI_DEVICE_ID_INTEL_IGDNG_D_HB:
1367         case PCI_DEVICE_ID_INTEL_IGDNG_M_HB:
1368         case PCI_DEVICE_ID_INTEL_IGDNG_MA_HB:
1369         case PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB:
1370                 *gtt_offset = *gtt_size = MB(2);
1371                 break;
1372         default:
1373                 *gtt_offset = *gtt_size = KB(512);
1374         }
1375 }
1376
1377 /* The intel i965 automatically initializes the agp aperture during POST.
1378  * Use the memory already set aside for in the GTT.
1379  */
1380 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1381 {
1382         int page_order;
1383         struct aper_size_info_fixed *size;
1384         int num_entries;
1385         u32 temp;
1386         int gtt_offset, gtt_size;
1387
1388         size = agp_bridge->current_size;
1389         page_order = size->page_order;
1390         num_entries = size->num_entries;
1391         agp_bridge->gatt_table_real = NULL;
1392
1393         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1394
1395         temp &= 0xfff00000;
1396
1397         intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1398
1399         intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1400
1401         if (!intel_private.gtt)
1402                 return -ENOMEM;
1403
1404         intel_private.registers = ioremap(temp, 128 * 4096);
1405         if (!intel_private.registers) {
1406                 iounmap(intel_private.gtt);
1407                 return -ENOMEM;
1408         }
1409
1410         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1411         global_cache_flush();   /* FIXME: ? */
1412
1413         /* we have to call this as early as possible after the MMIO base address is known */
1414         intel_i830_init_gtt_entries();
1415
1416         agp_bridge->gatt_table = NULL;
1417
1418         agp_bridge->gatt_bus_addr = temp;
1419
1420         return 0;
1421 }
1422
1423
1424 static int intel_fetch_size(void)
1425 {
1426         int i;
1427         u16 temp;
1428         struct aper_size_info_16 *values;
1429
1430         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1431         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1432
1433         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1434                 if (temp == values[i].size_value) {
1435                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1436                         agp_bridge->aperture_size_idx = i;
1437                         return values[i].size;
1438                 }
1439         }
1440
1441         return 0;
1442 }
1443
1444 static int __intel_8xx_fetch_size(u8 temp)
1445 {
1446         int i;
1447         struct aper_size_info_8 *values;
1448
1449         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1450
1451         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1452                 if (temp == values[i].size_value) {
1453                         agp_bridge->previous_size =
1454                                 agp_bridge->current_size = (void *) (values + i);
1455                         agp_bridge->aperture_size_idx = i;
1456                         return values[i].size;
1457                 }
1458         }
1459         return 0;
1460 }
1461
1462 static int intel_8xx_fetch_size(void)
1463 {
1464         u8 temp;
1465
1466         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1467         return __intel_8xx_fetch_size(temp);
1468 }
1469
1470 static int intel_815_fetch_size(void)
1471 {
1472         u8 temp;
1473
1474         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1475          * one non-reserved bit, so mask the others out ... */
1476         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1477         temp &= (1 << 3);
1478
1479         return __intel_8xx_fetch_size(temp);
1480 }
1481
1482 static void intel_tlbflush(struct agp_memory *mem)
1483 {
1484         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1485         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1486 }
1487
1488
1489 static void intel_8xx_tlbflush(struct agp_memory *mem)
1490 {
1491         u32 temp;
1492         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1493         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1494         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1495         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1496 }
1497
1498
1499 static void intel_cleanup(void)
1500 {
1501         u16 temp;
1502         struct aper_size_info_16 *previous_size;
1503
1504         previous_size = A_SIZE_16(agp_bridge->previous_size);
1505         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1506         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1507         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1508 }
1509
1510
1511 static void intel_8xx_cleanup(void)
1512 {
1513         u16 temp;
1514         struct aper_size_info_8 *previous_size;
1515
1516         previous_size = A_SIZE_8(agp_bridge->previous_size);
1517         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1518         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1519         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1520 }
1521
1522
1523 static int intel_configure(void)
1524 {
1525         u32 temp;
1526         u16 temp2;
1527         struct aper_size_info_16 *current_size;
1528
1529         current_size = A_SIZE_16(agp_bridge->current_size);
1530
1531         /* aperture size */
1532         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1533
1534         /* address to map to */
1535         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1536         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1537
1538         /* attbase - aperture base */
1539         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1540
1541         /* agpctrl */
1542         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1543
1544         /* paccfg/nbxcfg */
1545         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1546         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1547                         (temp2 & ~(1 << 10)) | (1 << 9));
1548         /* clear any possible error conditions */
1549         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1550         return 0;
1551 }
1552
1553 static int intel_815_configure(void)
1554 {
1555         u32 temp, addr;
1556         u8 temp2;
1557         struct aper_size_info_8 *current_size;
1558
1559         /* attbase - aperture base */
1560         /* the Intel 815 chipset spec. says that bits 29-31 in the
1561         * ATTBASE register are reserved -> try not to write them */
1562         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1563                 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
1564                 return -EINVAL;
1565         }
1566
1567         current_size = A_SIZE_8(agp_bridge->current_size);
1568
1569         /* aperture size */
1570         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1571                         current_size->size_value);
1572
1573         /* address to map to */
1574         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1575         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1576
1577         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1578         addr &= INTEL_815_ATTBASE_MASK;
1579         addr |= agp_bridge->gatt_bus_addr;
1580         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1581
1582         /* agpctrl */
1583         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1584
1585         /* apcont */
1586         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1587         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1588
1589         /* clear any possible error conditions */
1590         /* Oddness : this chipset seems to have no ERRSTS register ! */
1591         return 0;
1592 }
1593
1594 static void intel_820_tlbflush(struct agp_memory *mem)
1595 {
1596         return;
1597 }
1598
1599 static void intel_820_cleanup(void)
1600 {
1601         u8 temp;
1602         struct aper_size_info_8 *previous_size;
1603
1604         previous_size = A_SIZE_8(agp_bridge->previous_size);
1605         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1606         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1607                         temp & ~(1 << 1));
1608         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1609                         previous_size->size_value);
1610 }
1611
1612
1613 static int intel_820_configure(void)
1614 {
1615         u32 temp;
1616         u8 temp2;
1617         struct aper_size_info_8 *current_size;
1618
1619         current_size = A_SIZE_8(agp_bridge->current_size);
1620
1621         /* aperture size */
1622         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1623
1624         /* address to map to */
1625         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1626         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1627
1628         /* attbase - aperture base */
1629         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1630
1631         /* agpctrl */
1632         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1633
1634         /* global enable aperture access */
1635         /* This flag is not accessed through MCHCFG register as in */
1636         /* i850 chipset. */
1637         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1638         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1639         /* clear any possible AGP-related error conditions */
1640         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1641         return 0;
1642 }
1643
1644 static int intel_840_configure(void)
1645 {
1646         u32 temp;
1647         u16 temp2;
1648         struct aper_size_info_8 *current_size;
1649
1650         current_size = A_SIZE_8(agp_bridge->current_size);
1651
1652         /* aperture size */
1653         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1654
1655         /* address to map to */
1656         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1657         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1658
1659         /* attbase - aperture base */
1660         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1661
1662         /* agpctrl */
1663         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1664
1665         /* mcgcfg */
1666         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1667         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1668         /* clear any possible error conditions */
1669         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1670         return 0;
1671 }
1672
1673 static int intel_845_configure(void)
1674 {
1675         u32 temp;
1676         u8 temp2;
1677         struct aper_size_info_8 *current_size;
1678
1679         current_size = A_SIZE_8(agp_bridge->current_size);
1680
1681         /* aperture size */
1682         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1683
1684         if (agp_bridge->apbase_config != 0) {
1685                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1686                                        agp_bridge->apbase_config);
1687         } else {
1688                 /* address to map to */
1689                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1690                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1691                 agp_bridge->apbase_config = temp;
1692         }
1693
1694         /* attbase - aperture base */
1695         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1696
1697         /* agpctrl */
1698         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1699
1700         /* agpm */
1701         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1702         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1703         /* clear any possible error conditions */
1704         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1705
1706         intel_i830_setup_flush();
1707         return 0;
1708 }
1709
1710 static int intel_850_configure(void)
1711 {
1712         u32 temp;
1713         u16 temp2;
1714         struct aper_size_info_8 *current_size;
1715
1716         current_size = A_SIZE_8(agp_bridge->current_size);
1717
1718         /* aperture size */
1719         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1720
1721         /* address to map to */
1722         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1723         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1724
1725         /* attbase - aperture base */
1726         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1727
1728         /* agpctrl */
1729         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1730
1731         /* mcgcfg */
1732         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1733         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1734         /* clear any possible AGP-related error conditions */
1735         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1736         return 0;
1737 }
1738
1739 static int intel_860_configure(void)
1740 {
1741         u32 temp;
1742         u16 temp2;
1743         struct aper_size_info_8 *current_size;
1744
1745         current_size = A_SIZE_8(agp_bridge->current_size);
1746
1747         /* aperture size */
1748         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1749
1750         /* address to map to */
1751         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1752         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1753
1754         /* attbase - aperture base */
1755         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1756
1757         /* agpctrl */
1758         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1759
1760         /* mcgcfg */
1761         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1762         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1763         /* clear any possible AGP-related error conditions */
1764         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1765         return 0;
1766 }
1767
1768 static int intel_830mp_configure(void)
1769 {
1770         u32 temp;
1771         u16 temp2;
1772         struct aper_size_info_8 *current_size;
1773
1774         current_size = A_SIZE_8(agp_bridge->current_size);
1775
1776         /* aperture size */
1777         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1778
1779         /* address to map to */
1780         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1781         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1782
1783         /* attbase - aperture base */
1784         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1785
1786         /* agpctrl */
1787         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1788
1789         /* gmch */
1790         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1791         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1792         /* clear any possible AGP-related error conditions */
1793         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1794         return 0;
1795 }
1796
1797 static int intel_7505_configure(void)
1798 {
1799         u32 temp;
1800         u16 temp2;
1801         struct aper_size_info_8 *current_size;
1802
1803         current_size = A_SIZE_8(agp_bridge->current_size);
1804
1805         /* aperture size */
1806         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1807
1808         /* address to map to */
1809         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1810         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1811
1812         /* attbase - aperture base */
1813         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1814
1815         /* agpctrl */
1816         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1817
1818         /* mchcfg */
1819         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1820         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1821
1822         return 0;
1823 }
1824
1825 /* Setup function */
1826 static const struct gatt_mask intel_generic_masks[] =
1827 {
1828         {.mask = 0x00000017, .type = 0}
1829 };
1830
1831 static const struct aper_size_info_8 intel_815_sizes[2] =
1832 {
1833         {64, 16384, 4, 0},
1834         {32, 8192, 3, 8},
1835 };
1836
1837 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1838 {
1839         {256, 65536, 6, 0},
1840         {128, 32768, 5, 32},
1841         {64, 16384, 4, 48},
1842         {32, 8192, 3, 56},
1843         {16, 4096, 2, 60},
1844         {8, 2048, 1, 62},
1845         {4, 1024, 0, 63}
1846 };
1847
1848 static const struct aper_size_info_16 intel_generic_sizes[7] =
1849 {
1850         {256, 65536, 6, 0},
1851         {128, 32768, 5, 32},
1852         {64, 16384, 4, 48},
1853         {32, 8192, 3, 56},
1854         {16, 4096, 2, 60},
1855         {8, 2048, 1, 62},
1856         {4, 1024, 0, 63}
1857 };
1858
1859 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1860 {
1861         {256, 65536, 6, 0},
1862         {128, 32768, 5, 32},
1863         {64, 16384, 4, 48},
1864         {32, 8192, 3, 56}
1865 };
1866
1867 static const struct agp_bridge_driver intel_generic_driver = {
1868         .owner                  = THIS_MODULE,
1869         .aperture_sizes         = intel_generic_sizes,
1870         .size_type              = U16_APER_SIZE,
1871         .num_aperture_sizes     = 7,
1872         .configure              = intel_configure,
1873         .fetch_size             = intel_fetch_size,
1874         .cleanup                = intel_cleanup,
1875         .tlb_flush              = intel_tlbflush,
1876         .mask_memory            = agp_generic_mask_memory,
1877         .masks                  = intel_generic_masks,
1878         .agp_enable             = agp_generic_enable,
1879         .cache_flush            = global_cache_flush,
1880         .create_gatt_table      = agp_generic_create_gatt_table,
1881         .free_gatt_table        = agp_generic_free_gatt_table,
1882         .insert_memory          = agp_generic_insert_memory,
1883         .remove_memory          = agp_generic_remove_memory,
1884         .alloc_by_type          = agp_generic_alloc_by_type,
1885         .free_by_type           = agp_generic_free_by_type,
1886         .agp_alloc_page         = agp_generic_alloc_page,
1887         .agp_alloc_pages        = agp_generic_alloc_pages,
1888         .agp_destroy_page       = agp_generic_destroy_page,
1889         .agp_destroy_pages      = agp_generic_destroy_pages,
1890         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1891 };
1892
1893 static const struct agp_bridge_driver intel_810_driver = {
1894         .owner                  = THIS_MODULE,
1895         .aperture_sizes         = intel_i810_sizes,
1896         .size_type              = FIXED_APER_SIZE,
1897         .num_aperture_sizes     = 2,
1898         .needs_scratch_page     = true,
1899         .configure              = intel_i810_configure,
1900         .fetch_size             = intel_i810_fetch_size,
1901         .cleanup                = intel_i810_cleanup,
1902         .tlb_flush              = intel_i810_tlbflush,
1903         .mask_memory            = intel_i810_mask_memory,
1904         .masks                  = intel_i810_masks,
1905         .agp_enable             = intel_i810_agp_enable,
1906         .cache_flush            = global_cache_flush,
1907         .create_gatt_table      = agp_generic_create_gatt_table,
1908         .free_gatt_table        = agp_generic_free_gatt_table,
1909         .insert_memory          = intel_i810_insert_entries,
1910         .remove_memory          = intel_i810_remove_entries,
1911         .alloc_by_type          = intel_i810_alloc_by_type,
1912         .free_by_type           = intel_i810_free_by_type,
1913         .agp_alloc_page         = agp_generic_alloc_page,
1914         .agp_alloc_pages        = agp_generic_alloc_pages,
1915         .agp_destroy_page       = agp_generic_destroy_page,
1916         .agp_destroy_pages      = agp_generic_destroy_pages,
1917         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1918 };
1919
1920 static const struct agp_bridge_driver intel_815_driver = {
1921         .owner                  = THIS_MODULE,
1922         .aperture_sizes         = intel_815_sizes,
1923         .size_type              = U8_APER_SIZE,
1924         .num_aperture_sizes     = 2,
1925         .configure              = intel_815_configure,
1926         .fetch_size             = intel_815_fetch_size,
1927         .cleanup                = intel_8xx_cleanup,
1928         .tlb_flush              = intel_8xx_tlbflush,
1929         .mask_memory            = agp_generic_mask_memory,
1930         .masks                  = intel_generic_masks,
1931         .agp_enable             = agp_generic_enable,
1932         .cache_flush            = global_cache_flush,
1933         .create_gatt_table      = agp_generic_create_gatt_table,
1934         .free_gatt_table        = agp_generic_free_gatt_table,
1935         .insert_memory          = agp_generic_insert_memory,
1936         .remove_memory          = agp_generic_remove_memory,
1937         .alloc_by_type          = agp_generic_alloc_by_type,
1938         .free_by_type           = agp_generic_free_by_type,
1939         .agp_alloc_page         = agp_generic_alloc_page,
1940         .agp_alloc_pages        = agp_generic_alloc_pages,
1941         .agp_destroy_page       = agp_generic_destroy_page,
1942         .agp_destroy_pages      = agp_generic_destroy_pages,
1943         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1944 };
1945
1946 static const struct agp_bridge_driver intel_830_driver = {
1947         .owner                  = THIS_MODULE,
1948         .aperture_sizes         = intel_i830_sizes,
1949         .size_type              = FIXED_APER_SIZE,
1950         .num_aperture_sizes     = 4,
1951         .needs_scratch_page     = true,
1952         .configure              = intel_i830_configure,
1953         .fetch_size             = intel_i830_fetch_size,
1954         .cleanup                = intel_i830_cleanup,
1955         .tlb_flush              = intel_i810_tlbflush,
1956         .mask_memory            = intel_i810_mask_memory,
1957         .masks                  = intel_i810_masks,
1958         .agp_enable             = intel_i810_agp_enable,
1959         .cache_flush            = global_cache_flush,
1960         .create_gatt_table      = intel_i830_create_gatt_table,
1961         .free_gatt_table        = intel_i830_free_gatt_table,
1962         .insert_memory          = intel_i830_insert_entries,
1963         .remove_memory          = intel_i830_remove_entries,
1964         .alloc_by_type          = intel_i830_alloc_by_type,
1965         .free_by_type           = intel_i810_free_by_type,
1966         .agp_alloc_page         = agp_generic_alloc_page,
1967         .agp_alloc_pages        = agp_generic_alloc_pages,
1968         .agp_destroy_page       = agp_generic_destroy_page,
1969         .agp_destroy_pages      = agp_generic_destroy_pages,
1970         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1971         .chipset_flush          = intel_i830_chipset_flush,
1972 };
1973
1974 static const struct agp_bridge_driver intel_820_driver = {
1975         .owner                  = THIS_MODULE,
1976         .aperture_sizes         = intel_8xx_sizes,
1977         .size_type              = U8_APER_SIZE,
1978         .num_aperture_sizes     = 7,
1979         .configure              = intel_820_configure,
1980         .fetch_size             = intel_8xx_fetch_size,
1981         .cleanup                = intel_820_cleanup,
1982         .tlb_flush              = intel_820_tlbflush,
1983         .mask_memory            = agp_generic_mask_memory,
1984         .masks                  = intel_generic_masks,
1985         .agp_enable             = agp_generic_enable,
1986         .cache_flush            = global_cache_flush,
1987         .create_gatt_table      = agp_generic_create_gatt_table,
1988         .free_gatt_table        = agp_generic_free_gatt_table,
1989         .insert_memory          = agp_generic_insert_memory,
1990         .remove_memory          = agp_generic_remove_memory,
1991         .alloc_by_type          = agp_generic_alloc_by_type,
1992         .free_by_type           = agp_generic_free_by_type,
1993         .agp_alloc_page         = agp_generic_alloc_page,
1994         .agp_alloc_pages        = agp_generic_alloc_pages,
1995         .agp_destroy_page       = agp_generic_destroy_page,
1996         .agp_destroy_pages      = agp_generic_destroy_pages,
1997         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1998 };
1999
2000 static const struct agp_bridge_driver intel_830mp_driver = {
2001         .owner                  = THIS_MODULE,
2002         .aperture_sizes         = intel_830mp_sizes,
2003         .size_type              = U8_APER_SIZE,
2004         .num_aperture_sizes     = 4,
2005         .configure              = intel_830mp_configure,
2006         .fetch_size             = intel_8xx_fetch_size,
2007         .cleanup                = intel_8xx_cleanup,
2008         .tlb_flush              = intel_8xx_tlbflush,
2009         .mask_memory            = agp_generic_mask_memory,
2010         .masks                  = intel_generic_masks,
2011         .agp_enable             = agp_generic_enable,
2012         .cache_flush            = global_cache_flush,
2013         .create_gatt_table      = agp_generic_create_gatt_table,
2014         .free_gatt_table        = agp_generic_free_gatt_table,
2015         .insert_memory          = agp_generic_insert_memory,
2016         .remove_memory          = agp_generic_remove_memory,
2017         .alloc_by_type          = agp_generic_alloc_by_type,
2018         .free_by_type           = agp_generic_free_by_type,
2019         .agp_alloc_page         = agp_generic_alloc_page,
2020         .agp_alloc_pages        = agp_generic_alloc_pages,
2021         .agp_destroy_page       = agp_generic_destroy_page,
2022         .agp_destroy_pages      = agp_generic_destroy_pages,
2023         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2024 };
2025
2026 static const struct agp_bridge_driver intel_840_driver = {
2027         .owner                  = THIS_MODULE,
2028         .aperture_sizes         = intel_8xx_sizes,
2029         .size_type              = U8_APER_SIZE,
2030         .num_aperture_sizes     = 7,
2031         .configure              = intel_840_configure,
2032         .fetch_size             = intel_8xx_fetch_size,
2033         .cleanup                = intel_8xx_cleanup,
2034         .tlb_flush              = intel_8xx_tlbflush,
2035         .mask_memory            = agp_generic_mask_memory,
2036         .masks                  = intel_generic_masks,
2037         .agp_enable             = agp_generic_enable,
2038         .cache_flush            = global_cache_flush,
2039         .create_gatt_table      = agp_generic_create_gatt_table,
2040         .free_gatt_table        = agp_generic_free_gatt_table,
2041         .insert_memory          = agp_generic_insert_memory,
2042         .remove_memory          = agp_generic_remove_memory,
2043         .alloc_by_type          = agp_generic_alloc_by_type,
2044         .free_by_type           = agp_generic_free_by_type,
2045         .agp_alloc_page         = agp_generic_alloc_page,
2046         .agp_alloc_pages        = agp_generic_alloc_pages,
2047         .agp_destroy_page       = agp_generic_destroy_page,
2048         .agp_destroy_pages      = agp_generic_destroy_pages,
2049         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2050 };
2051
2052 static const struct agp_bridge_driver intel_845_driver = {
2053         .owner                  = THIS_MODULE,
2054         .aperture_sizes         = intel_8xx_sizes,
2055         .size_type              = U8_APER_SIZE,
2056         .num_aperture_sizes     = 7,
2057         .configure              = intel_845_configure,
2058         .fetch_size             = intel_8xx_fetch_size,
2059         .cleanup                = intel_8xx_cleanup,
2060         .tlb_flush              = intel_8xx_tlbflush,
2061         .mask_memory            = agp_generic_mask_memory,
2062         .masks                  = intel_generic_masks,
2063         .agp_enable             = agp_generic_enable,
2064         .cache_flush            = global_cache_flush,
2065         .create_gatt_table      = agp_generic_create_gatt_table,
2066         .free_gatt_table        = agp_generic_free_gatt_table,
2067         .insert_memory          = agp_generic_insert_memory,
2068         .remove_memory          = agp_generic_remove_memory,
2069         .alloc_by_type          = agp_generic_alloc_by_type,
2070         .free_by_type           = agp_generic_free_by_type,
2071         .agp_alloc_page         = agp_generic_alloc_page,
2072         .agp_alloc_pages        = agp_generic_alloc_pages,
2073         .agp_destroy_page       = agp_generic_destroy_page,
2074         .agp_destroy_pages      = agp_generic_destroy_pages,
2075         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2076         .chipset_flush          = intel_i830_chipset_flush,
2077 };
2078
2079 static const struct agp_bridge_driver intel_850_driver = {
2080         .owner                  = THIS_MODULE,
2081         .aperture_sizes         = intel_8xx_sizes,
2082         .size_type              = U8_APER_SIZE,
2083         .num_aperture_sizes     = 7,
2084         .configure              = intel_850_configure,
2085         .fetch_size             = intel_8xx_fetch_size,
2086         .cleanup                = intel_8xx_cleanup,
2087         .tlb_flush              = intel_8xx_tlbflush,
2088         .mask_memory            = agp_generic_mask_memory,
2089         .masks                  = intel_generic_masks,
2090         .agp_enable             = agp_generic_enable,
2091         .cache_flush            = global_cache_flush,
2092         .create_gatt_table      = agp_generic_create_gatt_table,
2093         .free_gatt_table        = agp_generic_free_gatt_table,
2094         .insert_memory          = agp_generic_insert_memory,
2095         .remove_memory          = agp_generic_remove_memory,
2096         .alloc_by_type          = agp_generic_alloc_by_type,
2097         .free_by_type           = agp_generic_free_by_type,
2098         .agp_alloc_page         = agp_generic_alloc_page,
2099         .agp_alloc_pages        = agp_generic_alloc_pages,
2100         .agp_destroy_page       = agp_generic_destroy_page,
2101         .agp_destroy_pages      = agp_generic_destroy_pages,
2102         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2103 };
2104
2105 static const struct agp_bridge_driver intel_860_driver = {
2106         .owner                  = THIS_MODULE,
2107         .aperture_sizes         = intel_8xx_sizes,
2108         .size_type              = U8_APER_SIZE,
2109         .num_aperture_sizes     = 7,
2110         .configure              = intel_860_configure,
2111         .fetch_size             = intel_8xx_fetch_size,
2112         .cleanup                = intel_8xx_cleanup,
2113         .tlb_flush              = intel_8xx_tlbflush,
2114         .mask_memory            = agp_generic_mask_memory,
2115         .masks                  = intel_generic_masks,
2116         .agp_enable             = agp_generic_enable,
2117         .cache_flush            = global_cache_flush,
2118         .create_gatt_table      = agp_generic_create_gatt_table,
2119         .free_gatt_table        = agp_generic_free_gatt_table,
2120         .insert_memory          = agp_generic_insert_memory,
2121         .remove_memory          = agp_generic_remove_memory,
2122         .alloc_by_type          = agp_generic_alloc_by_type,
2123         .free_by_type           = agp_generic_free_by_type,
2124         .agp_alloc_page         = agp_generic_alloc_page,
2125         .agp_alloc_pages        = agp_generic_alloc_pages,
2126         .agp_destroy_page       = agp_generic_destroy_page,
2127         .agp_destroy_pages      = agp_generic_destroy_pages,
2128         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2129 };
2130
2131 static const struct agp_bridge_driver intel_915_driver = {
2132         .owner                  = THIS_MODULE,
2133         .aperture_sizes         = intel_i830_sizes,
2134         .size_type              = FIXED_APER_SIZE,
2135         .num_aperture_sizes     = 4,
2136         .needs_scratch_page     = true,
2137         .configure              = intel_i915_configure,
2138         .fetch_size             = intel_i9xx_fetch_size,
2139         .cleanup                = intel_i915_cleanup,
2140         .tlb_flush              = intel_i810_tlbflush,
2141         .mask_memory            = intel_i810_mask_memory,
2142         .masks                  = intel_i810_masks,
2143         .agp_enable             = intel_i810_agp_enable,
2144         .cache_flush            = global_cache_flush,
2145         .create_gatt_table      = intel_i915_create_gatt_table,
2146         .free_gatt_table        = intel_i830_free_gatt_table,
2147         .insert_memory          = intel_i915_insert_entries,
2148         .remove_memory          = intel_i915_remove_entries,
2149         .alloc_by_type          = intel_i830_alloc_by_type,
2150         .free_by_type           = intel_i810_free_by_type,
2151         .agp_alloc_page         = agp_generic_alloc_page,
2152         .agp_alloc_pages        = agp_generic_alloc_pages,
2153         .agp_destroy_page       = agp_generic_destroy_page,
2154         .agp_destroy_pages      = agp_generic_destroy_pages,
2155         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2156         .chipset_flush          = intel_i915_chipset_flush,
2157 #ifdef USE_PCI_DMA_API
2158         .agp_map_page           = intel_agp_map_page,
2159         .agp_unmap_page         = intel_agp_unmap_page,
2160         .agp_map_memory         = intel_agp_map_memory,
2161         .agp_unmap_memory       = intel_agp_unmap_memory,
2162 #endif
2163 };
2164
2165 static const struct agp_bridge_driver intel_i965_driver = {
2166         .owner                  = THIS_MODULE,
2167         .aperture_sizes         = intel_i830_sizes,
2168         .size_type              = FIXED_APER_SIZE,
2169         .num_aperture_sizes     = 4,
2170         .needs_scratch_page     = true,
2171         .configure              = intel_i915_configure,
2172         .fetch_size             = intel_i9xx_fetch_size,
2173         .cleanup                = intel_i915_cleanup,
2174         .tlb_flush              = intel_i810_tlbflush,
2175         .mask_memory            = intel_i965_mask_memory,
2176         .masks                  = intel_i810_masks,
2177         .agp_enable             = intel_i810_agp_enable,
2178         .cache_flush            = global_cache_flush,
2179         .create_gatt_table      = intel_i965_create_gatt_table,
2180         .free_gatt_table        = intel_i830_free_gatt_table,
2181         .insert_memory          = intel_i915_insert_entries,
2182         .remove_memory          = intel_i915_remove_entries,
2183         .alloc_by_type          = intel_i830_alloc_by_type,
2184         .free_by_type           = intel_i810_free_by_type,
2185         .agp_alloc_page         = agp_generic_alloc_page,
2186         .agp_alloc_pages        = agp_generic_alloc_pages,
2187         .agp_destroy_page       = agp_generic_destroy_page,
2188         .agp_destroy_pages      = agp_generic_destroy_pages,
2189         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2190         .chipset_flush          = intel_i915_chipset_flush,
2191 #ifdef USE_PCI_DMA_API
2192         .agp_map_page           = intel_agp_map_page,
2193         .agp_unmap_page         = intel_agp_unmap_page,
2194         .agp_map_memory         = intel_agp_map_memory,
2195         .agp_unmap_memory       = intel_agp_unmap_memory,
2196 #endif
2197 };
2198
2199 static const struct agp_bridge_driver intel_7505_driver = {
2200         .owner                  = THIS_MODULE,
2201         .aperture_sizes         = intel_8xx_sizes,
2202         .size_type              = U8_APER_SIZE,
2203         .num_aperture_sizes     = 7,
2204         .configure              = intel_7505_configure,
2205         .fetch_size             = intel_8xx_fetch_size,
2206         .cleanup                = intel_8xx_cleanup,
2207         .tlb_flush              = intel_8xx_tlbflush,
2208         .mask_memory            = agp_generic_mask_memory,
2209         .masks                  = intel_generic_masks,
2210         .agp_enable             = agp_generic_enable,
2211         .cache_flush            = global_cache_flush,
2212         .create_gatt_table      = agp_generic_create_gatt_table,
2213         .free_gatt_table        = agp_generic_free_gatt_table,
2214         .insert_memory          = agp_generic_insert_memory,
2215         .remove_memory          = agp_generic_remove_memory,
2216         .alloc_by_type          = agp_generic_alloc_by_type,
2217         .free_by_type           = agp_generic_free_by_type,
2218         .agp_alloc_page         = agp_generic_alloc_page,
2219         .agp_alloc_pages        = agp_generic_alloc_pages,
2220         .agp_destroy_page       = agp_generic_destroy_page,
2221         .agp_destroy_pages      = agp_generic_destroy_pages,
2222         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2223 };
2224
2225 static const struct agp_bridge_driver intel_g33_driver = {
2226         .owner                  = THIS_MODULE,
2227         .aperture_sizes         = intel_i830_sizes,
2228         .size_type              = FIXED_APER_SIZE,
2229         .num_aperture_sizes     = 4,
2230         .needs_scratch_page     = true,
2231         .configure              = intel_i915_configure,
2232         .fetch_size             = intel_i9xx_fetch_size,
2233         .cleanup                = intel_i915_cleanup,
2234         .tlb_flush              = intel_i810_tlbflush,
2235         .mask_memory            = intel_i965_mask_memory,
2236         .masks                  = intel_i810_masks,
2237         .agp_enable             = intel_i810_agp_enable,
2238         .cache_flush            = global_cache_flush,
2239         .create_gatt_table      = intel_i915_create_gatt_table,
2240         .free_gatt_table        = intel_i830_free_gatt_table,
2241         .insert_memory          = intel_i915_insert_entries,
2242         .remove_memory          = intel_i915_remove_entries,
2243         .alloc_by_type          = intel_i830_alloc_by_type,
2244         .free_by_type           = intel_i810_free_by_type,
2245         .agp_alloc_page         = agp_generic_alloc_page,
2246         .agp_alloc_pages        = agp_generic_alloc_pages,
2247         .agp_destroy_page       = agp_generic_destroy_page,
2248         .agp_destroy_pages      = agp_generic_destroy_pages,
2249         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2250         .chipset_flush          = intel_i915_chipset_flush,
2251 #ifdef USE_PCI_DMA_API
2252         .agp_map_page           = intel_agp_map_page,
2253         .agp_unmap_page         = intel_agp_unmap_page,
2254         .agp_map_memory         = intel_agp_map_memory,
2255         .agp_unmap_memory       = intel_agp_unmap_memory,
2256 #endif
2257 };
2258
2259 static int find_gmch(u16 device)
2260 {
2261         struct pci_dev *gmch_device;
2262
2263         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2264         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
2265                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
2266                                              device, gmch_device);
2267         }
2268
2269         if (!gmch_device)
2270                 return 0;
2271
2272         intel_private.pcidev = gmch_device;
2273         return 1;
2274 }
2275
2276 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
2277  * driver and gmch_driver must be non-null, and find_gmch will determine
2278  * which one should be used if a gmch_chip_id is present.
2279  */
2280 static const struct intel_driver_description {
2281         unsigned int chip_id;
2282         unsigned int gmch_chip_id;
2283         unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
2284         char *name;
2285         const struct agp_bridge_driver *driver;
2286         const struct agp_bridge_driver *gmch_driver;
2287 } intel_agp_chipsets[] = {
2288         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2289         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2290         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2291         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2292                 NULL, &intel_810_driver },
2293         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2294                 NULL, &intel_810_driver },
2295         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2296                 NULL, &intel_810_driver },
2297         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2298                 &intel_815_driver, &intel_810_driver },
2299         { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2300         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2301         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2302                 &intel_830mp_driver, &intel_830_driver },
2303         { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2304         { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2305         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2306                 &intel_845_driver, &intel_830_driver },
2307         { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2308         { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854",
2309                 &intel_845_driver, &intel_830_driver },
2310         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2311         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2312                 &intel_845_driver, &intel_830_driver },
2313         { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2314         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2315                 &intel_845_driver, &intel_830_driver },
2316         { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2317         { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2318                 NULL, &intel_915_driver },
2319         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2320                 NULL, &intel_915_driver },
2321         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2322                 NULL, &intel_915_driver },
2323         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2324                 NULL, &intel_915_driver },
2325         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2326                 NULL, &intel_915_driver },
2327         { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2328                 NULL, &intel_915_driver },
2329         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2330                 NULL, &intel_i965_driver },
2331         { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
2332                 NULL, &intel_i965_driver },
2333         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2334                 NULL, &intel_i965_driver },
2335         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2336                 NULL, &intel_i965_driver },
2337         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2338                 NULL, &intel_i965_driver },
2339         { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2340                 NULL, &intel_i965_driver },
2341         { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2342         { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2343         { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2344                 NULL, &intel_g33_driver },
2345         { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2346                 NULL, &intel_g33_driver },
2347         { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2348                 NULL, &intel_g33_driver },
2349         { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, 0, "IGD",
2350                 NULL, &intel_g33_driver },
2351         { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, 0, "IGD",
2352                 NULL, &intel_g33_driver },
2353         { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
2354             "Mobile Intel® GM45 Express", NULL, &intel_i965_driver },
2355         { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
2356             "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2357         { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2358             "Q45/Q43", NULL, &intel_i965_driver },
2359         { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2360             "G45/G43", NULL, &intel_i965_driver },
2361         { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0,
2362             "B43", NULL, &intel_i965_driver },
2363         { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2364             "G41", NULL, &intel_i965_driver },
2365         { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0,
2366             "IGDNG/D", NULL, &intel_i965_driver },
2367         { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2368             "IGDNG/M", NULL, &intel_i965_driver },
2369         { PCI_DEVICE_ID_INTEL_IGDNG_MA_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2370             "IGDNG/MA", NULL, &intel_i965_driver },
2371         { PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2372             "IGDNG/MC2", NULL, &intel_i965_driver },
2373         { 0, 0, 0, NULL, NULL, NULL }
2374 };
2375
2376 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2377                                      const struct pci_device_id *ent)
2378 {
2379         struct agp_bridge_data *bridge;
2380         u8 cap_ptr = 0;
2381         struct resource *r;
2382         int i;
2383
2384         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2385
2386         bridge = agp_alloc_bridge();
2387         if (!bridge)
2388                 return -ENOMEM;
2389
2390         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2391                 /* In case that multiple models of gfx chip may
2392                    stand on same host bridge type, this can be
2393                    sure we detect the right IGD. */
2394                 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2395                         if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2396                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2397                                 bridge->driver =
2398                                         intel_agp_chipsets[i].gmch_driver;
2399                                 break;
2400                         } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2401                                 continue;
2402                         } else {
2403                                 bridge->driver = intel_agp_chipsets[i].driver;
2404                                 break;
2405                         }
2406                 }
2407         }
2408
2409         if (intel_agp_chipsets[i].name == NULL) {
2410                 if (cap_ptr)
2411                         dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
2412                                  pdev->vendor, pdev->device);
2413                 agp_put_bridge(bridge);
2414                 return -ENODEV;
2415         }
2416
2417         if (bridge->driver == NULL) {
2418                 /* bridge has no AGP and no IGD detected */
2419                 if (cap_ptr)
2420                         dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
2421                                  intel_agp_chipsets[i].gmch_chip_id);
2422                 agp_put_bridge(bridge);
2423                 return -ENODEV;
2424         }
2425
2426         bridge->dev = pdev;
2427         bridge->capndx = cap_ptr;
2428         bridge->dev_private_data = &intel_private;
2429
2430         dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
2431
2432         /*
2433         * The following fixes the case where the BIOS has "forgotten" to
2434         * provide an address range for the GART.
2435         * 20030610 - hamish@zot.org
2436         */
2437         r = &pdev->resource[0];
2438         if (!r->start && r->end) {
2439                 if (pci_assign_resource(pdev, 0)) {
2440                         dev_err(&pdev->dev, "can't assign resource 0\n");
2441                         agp_put_bridge(bridge);
2442                         return -ENODEV;
2443                 }
2444         }
2445
2446         /*
2447         * If the device has not been properly setup, the following will catch
2448         * the problem and should stop the system from crashing.
2449         * 20030610 - hamish@zot.org
2450         */
2451         if (pci_enable_device(pdev)) {
2452                 dev_err(&pdev->dev, "can't enable PCI device\n");
2453                 agp_put_bridge(bridge);
2454                 return -ENODEV;
2455         }
2456
2457         /* Fill in the mode register */
2458         if (cap_ptr) {
2459                 pci_read_config_dword(pdev,
2460                                 bridge->capndx+PCI_AGP_STATUS,
2461                                 &bridge->mode);
2462         }
2463
2464         pci_set_drvdata(pdev, bridge);
2465         return agp_add_bridge(bridge);
2466 }
2467
2468 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2469 {
2470         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2471
2472         agp_remove_bridge(bridge);
2473
2474         if (intel_private.pcidev)
2475                 pci_dev_put(intel_private.pcidev);
2476
2477         agp_put_bridge(bridge);
2478 }
2479
2480 #ifdef CONFIG_PM
2481 static int agp_intel_resume(struct pci_dev *pdev)
2482 {
2483         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2484         int ret_val;
2485
2486         if (bridge->driver == &intel_generic_driver)
2487                 intel_configure();
2488         else if (bridge->driver == &intel_850_driver)
2489                 intel_850_configure();
2490         else if (bridge->driver == &intel_845_driver)
2491                 intel_845_configure();
2492         else if (bridge->driver == &intel_830mp_driver)
2493                 intel_830mp_configure();
2494         else if (bridge->driver == &intel_915_driver)
2495                 intel_i915_configure();
2496         else if (bridge->driver == &intel_830_driver)
2497                 intel_i830_configure();
2498         else if (bridge->driver == &intel_810_driver)
2499                 intel_i810_configure();
2500         else if (bridge->driver == &intel_i965_driver)
2501                 intel_i915_configure();
2502
2503         ret_val = agp_rebind_memory();
2504         if (ret_val != 0)
2505                 return ret_val;
2506
2507         return 0;
2508 }
2509 #endif
2510
2511 static struct pci_device_id agp_intel_pci_table[] = {
2512 #define ID(x)                                           \
2513         {                                               \
2514         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
2515         .class_mask     = ~0,                           \
2516         .vendor         = PCI_VENDOR_ID_INTEL,          \
2517         .device         = x,                            \
2518         .subvendor      = PCI_ANY_ID,                   \
2519         .subdevice      = PCI_ANY_ID,                   \
2520         }
2521         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2522         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2523         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2524         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2525         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2526         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2527         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2528         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2529         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2530         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2531         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2532         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2533         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2534         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2535         ID(PCI_DEVICE_ID_INTEL_82854_HB),
2536         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2537         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2538         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2539         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2540         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2541         ID(PCI_DEVICE_ID_INTEL_7505_0),
2542         ID(PCI_DEVICE_ID_INTEL_7205_0),
2543         ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2544         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2545         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2546         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2547         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2548         ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2549         ID(PCI_DEVICE_ID_INTEL_IGDGM_HB),
2550         ID(PCI_DEVICE_ID_INTEL_IGDG_HB),
2551         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2552         ID(PCI_DEVICE_ID_INTEL_82G35_HB),
2553         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2554         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2555         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2556         ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2557         ID(PCI_DEVICE_ID_INTEL_G33_HB),
2558         ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2559         ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2560         ID(PCI_DEVICE_ID_INTEL_GM45_HB),
2561         ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
2562         ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2563         ID(PCI_DEVICE_ID_INTEL_G45_HB),
2564         ID(PCI_DEVICE_ID_INTEL_G41_HB),
2565         ID(PCI_DEVICE_ID_INTEL_B43_HB),
2566         ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB),
2567         ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB),
2568         ID(PCI_DEVICE_ID_INTEL_IGDNG_MA_HB),
2569         ID(PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB),
2570         { }
2571 };
2572
2573 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2574
2575 static struct pci_driver agp_intel_pci_driver = {
2576         .name           = "agpgart-intel",
2577         .id_table       = agp_intel_pci_table,
2578         .probe          = agp_intel_probe,
2579         .remove         = __devexit_p(agp_intel_remove),
2580 #ifdef CONFIG_PM
2581         .resume         = agp_intel_resume,
2582 #endif
2583 };
2584
2585 static int __init agp_intel_init(void)
2586 {
2587         if (agp_off)
2588                 return -EINVAL;
2589         return pci_register_driver(&agp_intel_pci_driver);
2590 }
2591
2592 static void __exit agp_intel_cleanup(void)
2593 {
2594         pci_unregister_driver(&agp_intel_pci_driver);
2595 }
2596
2597 module_init(agp_intel_init);
2598 module_exit(agp_intel_cleanup);
2599
2600 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
2601 MODULE_LICENSE("GPL and additional rights");