drivers/char/agp/intel-agp.c

   1 /*
   2  * Intel AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pagemap.h>
  10 #include <linux/agp_backend.h>
  11 #include "agp.h"
  12
  13 #define PCI_DEVICE_ID_INTEL_E7221_HB    0x2588
  14 #define PCI_DEVICE_ID_INTEL_E7221_IG    0x258a
  15 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
  16 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
  17 #define PCI_DEVICE_ID_INTEL_82G35_HB     0x2980
  18 #define PCI_DEVICE_ID_INTEL_82G35_IG     0x2982
  19 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
  20 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
  21 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
  22 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
  23 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
  24 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
  25 #define PCI_DEVICE_ID_INTEL_82965GME_HB     0x2A10
  26 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
  27 #define PCI_DEVICE_ID_INTEL_82945GME_HB     0x27AC
  28 #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
  29 #define PCI_DEVICE_ID_INTEL_IGDGM_HB        0xA010
  30 #define PCI_DEVICE_ID_INTEL_IGDGM_IG        0xA011
  31 #define PCI_DEVICE_ID_INTEL_IGDG_HB         0xA000
  32 #define PCI_DEVICE_ID_INTEL_IGDG_IG         0xA001
  33 #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0
  34 #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2
  35 #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0
  36 #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
  37 #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
  38 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
  39 #define PCI_DEVICE_ID_INTEL_B43_HB          0x2E40
  40 #define PCI_DEVICE_ID_INTEL_B43_IG          0x2E42
  41 #define PCI_DEVICE_ID_INTEL_GM45_HB         0x2A40
  42 #define PCI_DEVICE_ID_INTEL_GM45_IG         0x2A42
  43 #define PCI_DEVICE_ID_INTEL_IGD_E_HB        0x2E00
  44 #define PCI_DEVICE_ID_INTEL_IGD_E_IG        0x2E02
  45 #define PCI_DEVICE_ID_INTEL_Q45_HB          0x2E10
  46 #define PCI_DEVICE_ID_INTEL_Q45_IG          0x2E12
  47 #define PCI_DEVICE_ID_INTEL_G45_HB          0x2E20
  48 #define PCI_DEVICE_ID_INTEL_G45_IG          0x2E22
  49 #define PCI_DEVICE_ID_INTEL_G41_HB          0x2E30
  50 #define PCI_DEVICE_ID_INTEL_G41_IG          0x2E32
  51 #define PCI_DEVICE_ID_INTEL_IGDNG_D_HB      0x0040
  52 #define PCI_DEVICE_ID_INTEL_IGDNG_D_IG      0x0042
  53 #define PCI_DEVICE_ID_INTEL_IGDNG_M_HB      0x0044
  54 #define PCI_DEVICE_ID_INTEL_IGDNG_MA_HB     0x0062
  55 #define PCI_DEVICE_ID_INTEL_IGDNG_M_IG      0x0046
  56
  57 /* cover 915 and 945 variants */
  58 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
  59                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
  60                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
  61                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
  62                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
  63                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
  64
  65 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
  66                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
  67                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
  68                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
  69                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
  70                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
  71
  72 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
  73                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
  74                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
  75                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
  76                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
  77
  78 #define IS_IGD (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
  79                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
  80
  81 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
  82                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
  83                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
  84                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
  85                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
  86                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \
  87                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \
  88                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB || \
  89                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MA_HB)
  90
  91 extern int agp_memory_reserved;
  92
  93
  94 /* Intel 815 register */
  95 #define INTEL_815_APCONT        0x51
  96 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
  97
  98 /* Intel i820 registers */
  99 #define INTEL_I820_RDCR         0x51
 100 #define INTEL_I820_ERRSTS       0xc8
 101
 102 /* Intel i840 registers */
 103 #define INTEL_I840_MCHCFG       0x50
 104 #define INTEL_I840_ERRSTS       0xc8
 105
 106 /* Intel i850 registers */
 107 #define INTEL_I850_MCHCFG       0x50
 108 #define INTEL_I850_ERRSTS       0xc8
 109
 110 /* intel 915G registers */
 111 #define I915_GMADDR     0x18
 112 #define I915_MMADDR     0x10
 113 #define I915_PTEADDR    0x1C
 114 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
 115 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
 116 #define G33_GMCH_GMS_STOLEN_128M        (0x8 << 4)
 117 #define G33_GMCH_GMS_STOLEN_256M        (0x9 << 4)
 118 #define INTEL_GMCH_GMS_STOLEN_96M       (0xa << 4)
 119 #define INTEL_GMCH_GMS_STOLEN_160M      (0xb << 4)
 120 #define INTEL_GMCH_GMS_STOLEN_224M      (0xc << 4)
 121 #define INTEL_GMCH_GMS_STOLEN_352M      (0xd << 4)
 122
 123 #define I915_IFPADDR    0x60
 124
 125 /* Intel 965G registers */
 126 #define I965_MSAC 0x62
 127 #define I965_IFPADDR    0x70
 128
 129 /* Intel 7505 registers */
 130 #define INTEL_I7505_APSIZE      0x74
 131 #define INTEL_I7505_NCAPID      0x60
 132 #define INTEL_I7505_NISTAT      0x6c
 133 #define INTEL_I7505_ATTBASE     0x78
 134 #define INTEL_I7505_ERRSTS      0x42
 135 #define INTEL_I7505_AGPCTRL     0x70
 136 #define INTEL_I7505_MCHCFG      0x50
 137
 138 static const struct aper_size_info_fixed intel_i810_sizes[] =
 139 {
 140         {64, 16384, 4},
 141         /* The 32M mode still requires a 64k gatt */
 142         {32, 8192, 4}
 143 };
 144
 145 #define AGP_DCACHE_MEMORY       1
 146 #define AGP_PHYS_MEMORY         2
 147 #define INTEL_AGP_CACHED_MEMORY 3
 148
 149 static struct gatt_mask intel_i810_masks[] =
 150 {
 151         {.mask = I810_PTE_VALID, .type = 0},
 152         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
 153         {.mask = I810_PTE_VALID, .type = 0},
 154         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
 155          .type = INTEL_AGP_CACHED_MEMORY}
 156 };
 157
 158 static struct _intel_private {
 159         struct pci_dev *pcidev; /* device one */
 160         u8 __iomem *registers;
 161         u32 __iomem *gtt;               /* I915G */
 162         int num_dcache_entries;
 163         /* gtt_entries is the number of gtt entries that are already mapped
 164          * to stolen memory.  Stolen memory is larger than the memory mapped
 165          * through gtt_entries, as it includes some reserved space for the BIOS
 166          * popup and for the GTT.
 167          */
 168         int gtt_entries;                        /* i830+ */
 169         union {
 170                 void __iomem *i9xx_flush_page;
 171                 void *i8xx_flush_page;
 172         };
 173         struct page *i8xx_page;
 174         struct resource ifp_resource;
 175         int resource_valid;
 176 } intel_private;
 177
 178 static int intel_i810_fetch_size(void)
 179 {
 180         u32 smram_miscc;
 181         struct aper_size_info_fixed *values;
 182
 183         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
 184         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 185
 186         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
 187                 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
 188                 return 0;
 189         }
 190         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
 191                 agp_bridge->previous_size =
 192                         agp_bridge->current_size = (void *) (values + 1);
 193                 agp_bridge->aperture_size_idx = 1;
 194                 return values[1].size;
 195         } else {
 196                 agp_bridge->previous_size =
 197                         agp_bridge->current_size = (void *) (values);
 198                 agp_bridge->aperture_size_idx = 0;
 199                 return values[0].size;
 200         }
 201
 202         return 0;
 203 }
 204
 205 static int intel_i810_configure(void)
 206 {
 207         struct aper_size_info_fixed *current_size;
 208         u32 temp;
 209         int i;
 210
 211         current_size = A_SIZE_FIX(agp_bridge->current_size);
 212
 213         if (!intel_private.registers) {
 214                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 215                 temp &= 0xfff80000;
 216
 217                 intel_private.registers = ioremap(temp, 128 * 4096);
 218                 if (!intel_private.registers) {
 219                         dev_err(&intel_private.pcidev->dev,
 220                                 "can't remap memory\n");
 221                         return -ENOMEM;
 222                 }
 223         }
 224
 225         if ((readl(intel_private.registers+I810_DRAM_CTL)
 226                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 227                 /* This will need to be dynamically assigned */
 228                 dev_info(&intel_private.pcidev->dev,
 229                          "detected 4MB dedicated video ram\n");
 230                 intel_private.num_dcache_entries = 1024;
 231         }
 232         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 233         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 234         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 235         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 236
 237         if (agp_bridge->driver->needs_scratch_page) {
 238                 for (i = 0; i < current_size->num_entries; i++) {
 239                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 240                 }
 241                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
 242         }
 243         global_cache_flush();
 244         return 0;
 245 }
 246
 247 static void intel_i810_cleanup(void)
 248 {
 249         writel(0, intel_private.registers+I810_PGETBL_CTL);
 250         readl(intel_private.registers); /* PCI Posting. */
 251         iounmap(intel_private.registers);
 252 }
 253
 254 static void intel_i810_tlbflush(struct agp_memory *mem)
 255 {
 256         return;
 257 }
 258
 259 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 260 {
 261         return;
 262 }
 263
 264 /* Exists to support ARGB cursors */
 265 static struct page *i8xx_alloc_pages(void)
 266 {
 267         struct page *page;
 268
 269         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 270         if (page == NULL)
 271                 return NULL;
 272
 273         if (set_pages_uc(page, 4) < 0) {
 274                 set_pages_wb(page, 4);
 275                 __free_pages(page, 2);
 276                 return NULL;
 277         }
 278         get_page(page);
 279         atomic_inc(&agp_bridge->current_memory_agp);
 280         return page;
 281 }
 282
 283 static void i8xx_destroy_pages(struct page *page)
 284 {
 285         if (page == NULL)
 286                 return;
 287
 288         set_pages_wb(page, 4);
 289         put_page(page);
 290         __free_pages(page, 2);
 291         atomic_dec(&agp_bridge->current_memory_agp);
 292 }
 293
 294 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
 295                                         int type)
 296 {
 297         if (type < AGP_USER_TYPES)
 298                 return type;
 299         else if (type == AGP_USER_CACHED_MEMORY)
 300                 return INTEL_AGP_CACHED_MEMORY;
 301         else
 302                 return 0;
 303 }
 304
 305 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 306                                 int type)
 307 {
 308         int i, j, num_entries;
 309         void *temp;
 310         int ret = -EINVAL;
 311         int mask_type;
 312
 313         if (mem->page_count == 0)
 314                 goto out;
 315
 316         temp = agp_bridge->current_size;
 317         num_entries = A_SIZE_FIX(temp)->num_entries;
 318
 319         if ((pg_start + mem->page_count) > num_entries)
 320                 goto out_err;
 321
 322
 323         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 324                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
 325                         ret = -EBUSY;
 326                         goto out_err;
 327                 }
 328         }
 329
 330         if (type != mem->type)
 331                 goto out_err;
 332
 333         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 334
 335         switch (mask_type) {
 336         case AGP_DCACHE_MEMORY:
 337                 if (!mem->is_flushed)
 338                         global_cache_flush();
 339                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 340                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
 341                                intel_private.registers+I810_PTE_BASE+(i*4));
 342                 }
 343                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 344                 break;
 345         case AGP_PHYS_MEMORY:
 346         case AGP_NORMAL_MEMORY:
 347                 if (!mem->is_flushed)
 348                         global_cache_flush();
 349                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 350                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 351                                                                mem->pages[i],
 352                                                                mask_type),
 353                                intel_private.registers+I810_PTE_BASE+(j*4));
 354                 }
 355                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 356                 break;
 357         default:
 358                 goto out_err;
 359         }
 360
 361         agp_bridge->driver->tlb_flush(mem);
 362 out:
 363         ret = 0;
 364 out_err:
 365         mem->is_flushed = true;
 366         return ret;
 367 }
 368
 369 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 370                                 int type)
 371 {
 372         int i;
 373
 374         if (mem->page_count == 0)
 375                 return 0;
 376
 377         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 378                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 379         }
 380         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 381
 382         agp_bridge->driver->tlb_flush(mem);
 383         return 0;
 384 }
 385
 386 /*
 387  * The i810/i830 requires a physical address to program its mouse
 388  * pointer into hardware.
 389  * However the Xserver still writes to it through the agp aperture.
 390  */
 391 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 392 {
 393         struct agp_memory *new;
 394         struct page *page;
 395
 396         switch (pg_count) {
 397         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 398                 break;
 399         case 4:
 400                 /* kludge to get 4 physical pages for ARGB cursor */
 401                 page = i8xx_alloc_pages();
 402                 break;
 403         default:
 404                 return NULL;
 405         }
 406
 407         if (page == NULL)
 408                 return NULL;
 409
 410         new = agp_create_memory(pg_count);
 411         if (new == NULL)
 412                 return NULL;
 413
 414         new->pages[0] = page;
 415         if (pg_count == 4) {
 416                 /* kludge to get 4 physical pages for ARGB cursor */
 417                 new->pages[1] = new->pages[0] + 1;
 418                 new->pages[2] = new->pages[1] + 1;
 419                 new->pages[3] = new->pages[2] + 1;
 420         }
 421         new->page_count = pg_count;
 422         new->num_scratch_pages = pg_count;
 423         new->type = AGP_PHYS_MEMORY;
 424         new->physical = page_to_phys(new->pages[0]);
 425         return new;
 426 }
 427
 428 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 429 {
 430         struct agp_memory *new;
 431
 432         if (type == AGP_DCACHE_MEMORY) {
 433                 if (pg_count != intel_private.num_dcache_entries)
 434                         return NULL;
 435
 436                 new = agp_create_memory(1);
 437                 if (new == NULL)
 438                         return NULL;
 439
 440                 new->type = AGP_DCACHE_MEMORY;
 441                 new->page_count = pg_count;
 442                 new->num_scratch_pages = 0;
 443                 agp_free_page_array(new);
 444                 return new;
 445         }
 446         if (type == AGP_PHYS_MEMORY)
 447                 return alloc_agpphysmem_i8xx(pg_count, type);
 448         return NULL;
 449 }
 450
 451 static void intel_i810_free_by_type(struct agp_memory *curr)
 452 {
 453         agp_free_key(curr->key);
 454         if (curr->type == AGP_PHYS_MEMORY) {
 455                 if (curr->page_count == 4)
 456                         i8xx_destroy_pages(curr->pages[0]);
 457                 else {
 458                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 459                                                              AGP_PAGE_DESTROY_UNMAP);
 460                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 461                                                              AGP_PAGE_DESTROY_FREE);
 462                 }
 463                 agp_free_page_array(curr);
 464         }
 465         kfree(curr);
 466 }
 467
 468 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 469                                             struct page *page, int type)
 470 {
 471         unsigned long addr = phys_to_gart(page_to_phys(page));
 472         /* Type checking must be done elsewhere */
 473         return addr | bridge->driver->masks[type].mask;
 474 }
 475
 476 static struct aper_size_info_fixed intel_i830_sizes[] =
 477 {
 478         {128, 32768, 5},
 479         /* The 64M mode still requires a 128k gatt */
 480         {64, 16384, 5},
 481         {256, 65536, 6},
 482         {512, 131072, 7},
 483 };
 484
 485 static void intel_i830_init_gtt_entries(void)
 486 {
 487         u16 gmch_ctrl;
 488         int gtt_entries;
 489         u8 rdct;
 490         int local = 0;
 491         static const int ddt[4] = { 0, 16, 32, 64 };
 492         int size; /* reserved space (in kb) at the top of stolen memory */
 493
 494         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 495
 496         if (IS_I965) {
 497                 u32 pgetbl_ctl;
 498                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 499
 500                 /* The 965 has a field telling us the size of the GTT,
 501                  * which may be larger than what is necessary to map the
 502                  * aperture.
 503                  */
 504                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 505                 case I965_PGETBL_SIZE_128KB:
 506                         size = 128;
 507                         break;
 508                 case I965_PGETBL_SIZE_256KB:
 509                         size = 256;
 510                         break;
 511                 case I965_PGETBL_SIZE_512KB:
 512                         size = 512;
 513                         break;
 514                 case I965_PGETBL_SIZE_1MB:
 515                         size = 1024;
 516                         break;
 517                 case I965_PGETBL_SIZE_2MB:
 518                         size = 2048;
 519                         break;
 520                 case I965_PGETBL_SIZE_1_5MB:
 521                         size = 1024 + 512;
 522                         break;
 523                 default:
 524                         dev_info(&intel_private.pcidev->dev,
 525                                  "unknown page table size, assuming 512KB\n");
 526                         size = 512;
 527                 }
 528                 size += 4; /* add in BIOS popup space */
 529         } else if (IS_G33 && !IS_IGD) {
 530         /* G33's GTT size defined in gmch_ctrl */
 531                 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
 532                 case G33_PGETBL_SIZE_1M:
 533                         size = 1024;
 534                         break;
 535                 case G33_PGETBL_SIZE_2M:
 536                         size = 2048;
 537                         break;
 538                 default:
 539                         dev_info(&agp_bridge->dev->dev,
 540                                  "unknown page table size 0x%x, assuming 512KB\n",
 541                                 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
 542                         size = 512;
 543                 }
 544                 size += 4;
 545         } else if (IS_G4X || IS_IGD) {
 546                 /* On 4 series hardware, GTT stolen is separate from graphics
 547                  * stolen, ignore it in stolen gtt entries counting.  However,
 548                  * 4KB of the stolen memory doesn't get mapped to the GTT.
 549                  */
 550                 size = 4;
 551         } else {
 552                 /* On previous hardware, the GTT size was just what was
 553                  * required to map the aperture.
 554                  */
 555                 size = agp_bridge->driver->fetch_size() + 4;
 556         }
 557
 558         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 559             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 560                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 561                 case I830_GMCH_GMS_STOLEN_512:
 562                         gtt_entries = KB(512) - KB(size);
 563                         break;
 564                 case I830_GMCH_GMS_STOLEN_1024:
 565                         gtt_entries = MB(1) - KB(size);
 566                         break;
 567                 case I830_GMCH_GMS_STOLEN_8192:
 568                         gtt_entries = MB(8) - KB(size);
 569                         break;
 570                 case I830_GMCH_GMS_LOCAL:
 571                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 572                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
 573                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 574                         local = 1;
 575                         break;
 576                 default:
 577                         gtt_entries = 0;
 578                         break;
 579                 }
 580         } else {
 581                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 582                 case I855_GMCH_GMS_STOLEN_1M:
 583                         gtt_entries = MB(1) - KB(size);
 584                         break;
 585                 case I855_GMCH_GMS_STOLEN_4M:
 586                         gtt_entries = MB(4) - KB(size);
 587                         break;
 588                 case I855_GMCH_GMS_STOLEN_8M:
 589                         gtt_entries = MB(8) - KB(size);
 590                         break;
 591                 case I855_GMCH_GMS_STOLEN_16M:
 592                         gtt_entries = MB(16) - KB(size);
 593                         break;
 594                 case I855_GMCH_GMS_STOLEN_32M:
 595                         gtt_entries = MB(32) - KB(size);
 596                         break;
 597                 case I915_GMCH_GMS_STOLEN_48M:
 598                         /* Check it's really I915G */
 599                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 600                                 gtt_entries = MB(48) - KB(size);
 601                         else
 602                                 gtt_entries = 0;
 603                         break;
 604                 case I915_GMCH_GMS_STOLEN_64M:
 605                         /* Check it's really I915G */
 606                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 607                                 gtt_entries = MB(64) - KB(size);
 608                         else
 609                                 gtt_entries = 0;
 610                         break;
 611                 case G33_GMCH_GMS_STOLEN_128M:
 612                         if (IS_G33 || IS_I965 || IS_G4X)
 613                                 gtt_entries = MB(128) - KB(size);
 614                         else
 615                                 gtt_entries = 0;
 616                         break;
 617                 case G33_GMCH_GMS_STOLEN_256M:
 618                         if (IS_G33 || IS_I965 || IS_G4X)
 619                                 gtt_entries = MB(256) - KB(size);
 620                         else
 621                                 gtt_entries = 0;
 622                         break;
 623                 case INTEL_GMCH_GMS_STOLEN_96M:
 624                         if (IS_I965 || IS_G4X)
 625                                 gtt_entries = MB(96) - KB(size);
 626                         else
 627                                 gtt_entries = 0;
 628                         break;
 629                 case INTEL_GMCH_GMS_STOLEN_160M:
 630                         if (IS_I965 || IS_G4X)
 631                                 gtt_entries = MB(160) - KB(size);
 632                         else
 633                                 gtt_entries = 0;
 634                         break;
 635                 case INTEL_GMCH_GMS_STOLEN_224M:
 636                         if (IS_I965 || IS_G4X)
 637                                 gtt_entries = MB(224) - KB(size);
 638                         else
 639                                 gtt_entries = 0;
 640                         break;
 641                 case INTEL_GMCH_GMS_STOLEN_352M:
 642                         if (IS_I965 || IS_G4X)
 643                                 gtt_entries = MB(352) - KB(size);
 644                         else
 645                                 gtt_entries = 0;
 646                         break;
 647                 default:
 648                         gtt_entries = 0;
 649                         break;
 650                 }
 651         }
 652         if (gtt_entries > 0) {
 653                 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
 654                        gtt_entries / KB(1), local ? "local" : "stolen");
 655                 gtt_entries /= KB(4);
 656         } else {
 657                 dev_info(&agp_bridge->dev->dev,
 658                        "no pre-allocated video memory detected\n");
 659                 gtt_entries = 0;
 660         }
 661
 662         intel_private.gtt_entries = gtt_entries;
 663 }
 664
 665 static void intel_i830_fini_flush(void)
 666 {
 667         kunmap(intel_private.i8xx_page);
 668         intel_private.i8xx_flush_page = NULL;
 669         unmap_page_from_agp(intel_private.i8xx_page);
 670
 671         __free_page(intel_private.i8xx_page);
 672         intel_private.i8xx_page = NULL;
 673 }
 674
 675 static void intel_i830_setup_flush(void)
 676 {
 677         /* return if we've already set the flush mechanism up */
 678         if (intel_private.i8xx_page)
 679                 return;
 680
 681         intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
 682         if (!intel_private.i8xx_page)
 683                 return;
 684
 685         intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
 686         if (!intel_private.i8xx_flush_page)
 687                 intel_i830_fini_flush();
 688 }
 689
 690 static void
 691 do_wbinvd(void *null)
 692 {
 693         wbinvd();
 694 }
 695
 696 /* The chipset_flush interface needs to get data that has already been
 697  * flushed out of the CPU all the way out to main memory, because the GPU
 698  * doesn't snoop those buffers.
 699  *
 700  * The 8xx series doesn't have the same lovely interface for flushing the
 701  * chipset write buffers that the later chips do. According to the 865
 702  * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
 703  * that buffer out, we just fill 1KB and clflush it out, on the assumption
 704  * that it'll push whatever was in there out.  It appears to work.
 705  */
 706 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
 707 {
 708         unsigned int *pg = intel_private.i8xx_flush_page;
 709
 710         memset(pg, 0, 1024);
 711
 712         if (cpu_has_clflush) {
 713                 clflush_cache_range(pg, 1024);
 714         } else {
 715                 if (on_each_cpu(do_wbinvd, NULL, 1) != 0)
 716                         printk(KERN_ERR "Timed out waiting for cache flush.\n");
 717         }
 718 }
 719
 720 /* The intel i830 automatically initializes the agp aperture during POST.
 721  * Use the memory already set aside for in the GTT.
 722  */
 723 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 724 {
 725         int page_order;
 726         struct aper_size_info_fixed *size;
 727         int num_entries;
 728         u32 temp;
 729
 730         size = agp_bridge->current_size;
 731         page_order = size->page_order;
 732         num_entries = size->num_entries;
 733         agp_bridge->gatt_table_real = NULL;
 734
 735         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 736         temp &= 0xfff80000;
 737
 738         intel_private.registers = ioremap(temp, 128 * 4096);
 739         if (!intel_private.registers)
 740                 return -ENOMEM;
 741
 742         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 743         global_cache_flush();   /* FIXME: ?? */
 744
 745         /* we have to call this as early as possible after the MMIO base address is known */
 746         intel_i830_init_gtt_entries();
 747
 748         agp_bridge->gatt_table = NULL;
 749
 750         agp_bridge->gatt_bus_addr = temp;
 751
 752         return 0;
 753 }
 754
 755 /* Return the gatt table to a sane state. Use the top of stolen
 756  * memory for the GTT.
 757  */
 758 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
 759 {
 760         return 0;
 761 }
 762
 763 static int intel_i830_fetch_size(void)
 764 {
 765         u16 gmch_ctrl;
 766         struct aper_size_info_fixed *values;
 767
 768         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 769
 770         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
 771             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
 772                 /* 855GM/852GM/865G has 128MB aperture size */
 773                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 774                 agp_bridge->aperture_size_idx = 0;
 775                 return values[0].size;
 776         }
 777
 778         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 779
 780         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
 781                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 782                 agp_bridge->aperture_size_idx = 0;
 783                 return values[0].size;
 784         } else {
 785                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
 786                 agp_bridge->aperture_size_idx = 1;
 787                 return values[1].size;
 788         }
 789
 790         return 0;
 791 }
 792
 793 static int intel_i830_configure(void)
 794 {
 795         struct aper_size_info_fixed *current_size;
 796         u32 temp;
 797         u16 gmch_ctrl;
 798         int i;
 799
 800         current_size = A_SIZE_FIX(agp_bridge->current_size);
 801
 802         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 803         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 804
 805         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 806         gmch_ctrl |= I830_GMCH_ENABLED;
 807         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
 808
 809         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 810         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 811
 812         if (agp_bridge->driver->needs_scratch_page) {
 813                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 814                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 815                 }
 816                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
 817         }
 818
 819         global_cache_flush();
 820
 821         intel_i830_setup_flush();
 822         return 0;
 823 }
 824
 825 static void intel_i830_cleanup(void)
 826 {
 827         iounmap(intel_private.registers);
 828 }
 829
 830 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
 831                                      int type)
 832 {
 833         int i, j, num_entries;
 834         void *temp;
 835         int ret = -EINVAL;
 836         int mask_type;
 837
 838         if (mem->page_count == 0)
 839                 goto out;
 840
 841         temp = agp_bridge->current_size;
 842         num_entries = A_SIZE_FIX(temp)->num_entries;
 843
 844         if (pg_start < intel_private.gtt_entries) {
 845                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
 846                            "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
 847                            pg_start, intel_private.gtt_entries);
 848
 849                 dev_info(&intel_private.pcidev->dev,
 850                          "trying to insert into local/stolen memory\n");
 851                 goto out_err;
 852         }
 853
 854         if ((pg_start + mem->page_count) > num_entries)
 855                 goto out_err;
 856
 857         /* The i830 can't check the GTT for entries since its read only,
 858          * depend on the caller to make the correct offset decisions.
 859          */
 860
 861         if (type != mem->type)
 862                 goto out_err;
 863
 864         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 865
 866         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 867             mask_type != INTEL_AGP_CACHED_MEMORY)
 868                 goto out_err;
 869
 870         if (!mem->is_flushed)
 871                 global_cache_flush();
 872
 873         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 874                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 875                                                        mem->pages[i], mask_type),
 876                        intel_private.registers+I810_PTE_BASE+(j*4));
 877         }
 878         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 879         agp_bridge->driver->tlb_flush(mem);
 880
 881 out:
 882         ret = 0;
 883 out_err:
 884         mem->is_flushed = true;
 885         return ret;
 886 }
 887
 888 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
 889                                      int type)
 890 {
 891         int i;
 892
 893         if (mem->page_count == 0)
 894                 return 0;
 895
 896         if (pg_start < intel_private.gtt_entries) {
 897                 dev_info(&intel_private.pcidev->dev,
 898                          "trying to disable local/stolen memory\n");
 899                 return -EINVAL;
 900         }
 901
 902         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 903                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 904         }
 905         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 906
 907         agp_bridge->driver->tlb_flush(mem);
 908         return 0;
 909 }
 910
 911 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
 912 {
 913         if (type == AGP_PHYS_MEMORY)
 914                 return alloc_agpphysmem_i8xx(pg_count, type);
 915         /* always return NULL for other allocation types for now */
 916         return NULL;
 917 }
 918
 919 static int intel_alloc_chipset_flush_resource(void)
 920 {
 921         int ret;
 922         ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
 923                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
 924                                      pcibios_align_resource, agp_bridge->dev);
 925
 926         return ret;
 927 }
 928
 929 static void intel_i915_setup_chipset_flush(void)
 930 {
 931         int ret;
 932         u32 temp;
 933
 934         pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
 935         if (!(temp & 0x1)) {
 936                 intel_alloc_chipset_flush_resource();
 937                 intel_private.resource_valid = 1;
 938                 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
 939         } else {
 940                 temp &= ~1;
 941
 942                 intel_private.resource_valid = 1;
 943                 intel_private.ifp_resource.start = temp;
 944                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
 945                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
 946                 /* some BIOSes reserve this area in a pnp some don't */
 947                 if (ret)
 948                         intel_private.resource_valid = 0;
 949         }
 950 }
 951
 952 static void intel_i965_g33_setup_chipset_flush(void)
 953 {
 954         u32 temp_hi, temp_lo;
 955         int ret;
 956
 957         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
 958         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
 959
 960         if (!(temp_lo & 0x1)) {
 961
 962                 intel_alloc_chipset_flush_resource();
 963
 964                 intel_private.resource_valid = 1;
 965                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
 966                         upper_32_bits(intel_private.ifp_resource.start));
 967                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
 968         } else {
 969                 u64 l64;
 970
 971                 temp_lo &= ~0x1;
 972                 l64 = ((u64)temp_hi << 32) | temp_lo;
 973
 974                 intel_private.resource_valid = 1;
 975                 intel_private.ifp_resource.start = l64;
 976                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
 977                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
 978                 /* some BIOSes reserve this area in a pnp some don't */
 979                 if (ret)
 980                         intel_private.resource_valid = 0;
 981         }
 982 }
 983
 984 static void intel_i9xx_setup_flush(void)
 985 {
 986         /* return if already configured */
 987         if (intel_private.ifp_resource.start)
 988                 return;
 989
 990         /* setup a resource for this object */
 991         intel_private.ifp_resource.name = "Intel Flush Page";
 992         intel_private.ifp_resource.flags = IORESOURCE_MEM;
 993
 994         /* Setup chipset flush for 915 */
 995         if (IS_I965 || IS_G33 || IS_G4X) {
 996                 intel_i965_g33_setup_chipset_flush();
 997         } else {
 998                 intel_i915_setup_chipset_flush();
 999         }
1000
1001         if (intel_private.ifp_resource.start) {
1002                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1003                 if (!intel_private.i9xx_flush_page)
1004                         dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
1005         }
1006 }
1007
1008 static int intel_i915_configure(void)
1009 {
1010         struct aper_size_info_fixed *current_size;
1011         u32 temp;
1012         u16 gmch_ctrl;
1013         int i;
1014
1015         current_size = A_SIZE_FIX(agp_bridge->current_size);
1016
1017         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1018
1019         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1020
1021         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1022         gmch_ctrl |= I830_GMCH_ENABLED;
1023         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1024
1025         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1026         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1027
1028         if (agp_bridge->driver->needs_scratch_page) {
1029                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
1030                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
1031                 }
1032                 readl(intel_private.gtt+i-1);   /* PCI Posting. */
1033         }
1034
1035         global_cache_flush();
1036
1037         intel_i9xx_setup_flush();
1038
1039         return 0;
1040 }
1041
1042 static void intel_i915_cleanup(void)
1043 {
1044         if (intel_private.i9xx_flush_page)
1045                 iounmap(intel_private.i9xx_flush_page);
1046         if (intel_private.resource_valid)
1047                 release_resource(&intel_private.ifp_resource);
1048         intel_private.ifp_resource.start = 0;
1049         intel_private.resource_valid = 0;
1050         iounmap(intel_private.gtt);
1051         iounmap(intel_private.registers);
1052 }
1053
1054 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1055 {
1056         if (intel_private.i9xx_flush_page)
1057                 writel(1, intel_private.i9xx_flush_page);
1058 }
1059
1060 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1061                                      int type)
1062 {
1063         int i, j, num_entries;
1064         void *temp;
1065         int ret = -EINVAL;
1066         int mask_type;
1067
1068         if (mem->page_count == 0)
1069                 goto out;
1070
1071         temp = agp_bridge->current_size;
1072         num_entries = A_SIZE_FIX(temp)->num_entries;
1073
1074         if (pg_start < intel_private.gtt_entries) {
1075                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1076                            "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1077                            pg_start, intel_private.gtt_entries);
1078
1079                 dev_info(&intel_private.pcidev->dev,
1080                          "trying to insert into local/stolen memory\n");
1081                 goto out_err;
1082         }
1083
1084         if ((pg_start + mem->page_count) > num_entries)
1085                 goto out_err;
1086
1087         /* The i915 can't check the GTT for entries since its read only,
1088          * depend on the caller to make the correct offset decisions.
1089          */
1090
1091         if (type != mem->type)
1092                 goto out_err;
1093
1094         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1095
1096         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1097             mask_type != INTEL_AGP_CACHED_MEMORY)
1098                 goto out_err;
1099
1100         if (!mem->is_flushed)
1101                 global_cache_flush();
1102
1103         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1104                 writel(agp_bridge->driver->mask_memory(agp_bridge,
1105                                                        mem->pages[i], mask_type), intel_private.gtt+j);
1106         }
1107
1108         readl(intel_private.gtt+j-1);
1109         agp_bridge->driver->tlb_flush(mem);
1110
1111  out:
1112         ret = 0;
1113  out_err:
1114         mem->is_flushed = true;
1115         return ret;
1116 }
1117
1118 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1119                                      int type)
1120 {
1121         int i;
1122
1123         if (mem->page_count == 0)
1124                 return 0;
1125
1126         if (pg_start < intel_private.gtt_entries) {
1127                 dev_info(&intel_private.pcidev->dev,
1128                          "trying to disable local/stolen memory\n");
1129                 return -EINVAL;
1130         }
1131
1132         for (i = pg_start; i < (mem->page_count + pg_start); i++)
1133                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1134
1135         readl(intel_private.gtt+i-1);
1136
1137         agp_bridge->driver->tlb_flush(mem);
1138         return 0;
1139 }
1140
1141 /* Return the aperture size by just checking the resource length.  The effect
1142  * described in the spec of the MSAC registers is just changing of the
1143  * resource size.
1144  */
1145 static int intel_i9xx_fetch_size(void)
1146 {
1147         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1148         int aper_size; /* size in megabytes */
1149         int i;
1150
1151         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1152
1153         for (i = 0; i < num_sizes; i++) {
1154                 if (aper_size == intel_i830_sizes[i].size) {
1155                         agp_bridge->current_size = intel_i830_sizes + i;
1156                         agp_bridge->previous_size = agp_bridge->current_size;
1157                         return aper_size;
1158                 }
1159         }
1160
1161         return 0;
1162 }
1163
1164 /* The intel i915 automatically initializes the agp aperture during POST.
1165  * Use the memory already set aside for in the GTT.
1166  */
1167 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1168 {
1169         int page_order;
1170         struct aper_size_info_fixed *size;
1171         int num_entries;
1172         u32 temp, temp2;
1173         int gtt_map_size = 256 * 1024;
1174
1175         size = agp_bridge->current_size;
1176         page_order = size->page_order;
1177         num_entries = size->num_entries;
1178         agp_bridge->gatt_table_real = NULL;
1179
1180         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1181         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1182
1183         if (IS_G33)
1184             gtt_map_size = 1024 * 1024; /* 1M on G33 */
1185         intel_private.gtt = ioremap(temp2, gtt_map_size);
1186         if (!intel_private.gtt)
1187                 return -ENOMEM;
1188
1189         temp &= 0xfff80000;
1190
1191         intel_private.registers = ioremap(temp, 128 * 4096);
1192         if (!intel_private.registers) {
1193                 iounmap(intel_private.gtt);
1194                 return -ENOMEM;
1195         }
1196
1197         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1198         global_cache_flush();   /* FIXME: ? */
1199
1200         /* we have to call this as early as possible after the MMIO base address is known */
1201         intel_i830_init_gtt_entries();
1202
1203         agp_bridge->gatt_table = NULL;
1204
1205         agp_bridge->gatt_bus_addr = temp;
1206
1207         return 0;
1208 }
1209
1210 /*
1211  * The i965 supports 36-bit physical addresses, but to keep
1212  * the format of the GTT the same, the bits that don't fit
1213  * in a 32-bit word are shifted down to bits 4..7.
1214  *
1215  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1216  * is always zero on 32-bit architectures, so no need to make
1217  * this conditional.
1218  */
1219 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1220                                             struct page *page, int type)
1221 {
1222         dma_addr_t addr = phys_to_gart(page_to_phys(page));
1223         /* Shift high bits down */
1224         addr |= (addr >> 28) & 0xf0;
1225
1226         /* Type checking must be done elsewhere */
1227         return addr | bridge->driver->masks[type].mask;
1228 }
1229
1230 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1231 {
1232         switch (agp_bridge->dev->device) {
1233         case PCI_DEVICE_ID_INTEL_GM45_HB:
1234         case PCI_DEVICE_ID_INTEL_IGD_E_HB:
1235         case PCI_DEVICE_ID_INTEL_Q45_HB:
1236         case PCI_DEVICE_ID_INTEL_G45_HB:
1237         case PCI_DEVICE_ID_INTEL_G41_HB:
1238         case PCI_DEVICE_ID_INTEL_B43_HB:
1239         case PCI_DEVICE_ID_INTEL_IGDNG_D_HB:
1240         case PCI_DEVICE_ID_INTEL_IGDNG_M_HB:
1241         case PCI_DEVICE_ID_INTEL_IGDNG_MA_HB:
1242                 *gtt_offset = *gtt_size = MB(2);
1243                 break;
1244         default:
1245                 *gtt_offset = *gtt_size = KB(512);
1246         }
1247 }
1248
1249 /* The intel i965 automatically initializes the agp aperture during POST.
1250  * Use the memory already set aside for in the GTT.
1251  */
1252 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1253 {
1254         int page_order;
1255         struct aper_size_info_fixed *size;
1256         int num_entries;
1257         u32 temp;
1258         int gtt_offset, gtt_size;
1259
1260         size = agp_bridge->current_size;
1261         page_order = size->page_order;
1262         num_entries = size->num_entries;
1263         agp_bridge->gatt_table_real = NULL;
1264
1265         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1266
1267         temp &= 0xfff00000;
1268
1269         intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1270
1271         intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1272
1273         if (!intel_private.gtt)
1274                 return -ENOMEM;
1275
1276         intel_private.registers = ioremap(temp, 128 * 4096);
1277         if (!intel_private.registers) {
1278                 iounmap(intel_private.gtt);
1279                 return -ENOMEM;
1280         }
1281
1282         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1283         global_cache_flush();   /* FIXME: ? */
1284
1285         /* we have to call this as early as possible after the MMIO base address is known */
1286         intel_i830_init_gtt_entries();
1287
1288         agp_bridge->gatt_table = NULL;
1289
1290         agp_bridge->gatt_bus_addr = temp;
1291
1292         return 0;
1293 }
1294
1295
1296 static int intel_fetch_size(void)
1297 {
1298         int i;
1299         u16 temp;
1300         struct aper_size_info_16 *values;
1301
1302         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1303         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1304
1305         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1306                 if (temp == values[i].size_value) {
1307                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1308                         agp_bridge->aperture_size_idx = i;
1309                         return values[i].size;
1310                 }
1311         }
1312
1313         return 0;
1314 }
1315
1316 static int __intel_8xx_fetch_size(u8 temp)
1317 {
1318         int i;
1319         struct aper_size_info_8 *values;
1320
1321         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1322
1323         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1324                 if (temp == values[i].size_value) {
1325                         agp_bridge->previous_size =
1326                                 agp_bridge->current_size = (void *) (values + i);
1327                         agp_bridge->aperture_size_idx = i;
1328                         return values[i].size;
1329                 }
1330         }
1331         return 0;
1332 }
1333
1334 static int intel_8xx_fetch_size(void)
1335 {
1336         u8 temp;
1337
1338         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1339         return __intel_8xx_fetch_size(temp);
1340 }
1341
1342 static int intel_815_fetch_size(void)
1343 {
1344         u8 temp;
1345
1346         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1347          * one non-reserved bit, so mask the others out ... */
1348         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1349         temp &= (1 << 3);
1350
1351         return __intel_8xx_fetch_size(temp);
1352 }
1353
1354 static void intel_tlbflush(struct agp_memory *mem)
1355 {
1356         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1357         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1358 }
1359
1360
1361 static void intel_8xx_tlbflush(struct agp_memory *mem)
1362 {
1363         u32 temp;
1364         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1365         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1366         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1367         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1368 }
1369
1370
1371 static void intel_cleanup(void)
1372 {
1373         u16 temp;
1374         struct aper_size_info_16 *previous_size;
1375
1376         previous_size = A_SIZE_16(agp_bridge->previous_size);
1377         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1378         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1379         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1380 }
1381
1382
1383 static void intel_8xx_cleanup(void)
1384 {
1385         u16 temp;
1386         struct aper_size_info_8 *previous_size;
1387
1388         previous_size = A_SIZE_8(agp_bridge->previous_size);
1389         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1390         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1391         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1392 }
1393
1394
1395 static int intel_configure(void)
1396 {
1397         u32 temp;
1398         u16 temp2;
1399         struct aper_size_info_16 *current_size;
1400
1401         current_size = A_SIZE_16(agp_bridge->current_size);
1402
1403         /* aperture size */
1404         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1405
1406         /* address to map to */
1407         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1408         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1409
1410         /* attbase - aperture base */
1411         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1412
1413         /* agpctrl */
1414         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1415
1416         /* paccfg/nbxcfg */
1417         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1418         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1419                         (temp2 & ~(1 << 10)) | (1 << 9));
1420         /* clear any possible error conditions */
1421         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1422         return 0;
1423 }
1424
1425 static int intel_815_configure(void)
1426 {
1427         u32 temp, addr;
1428         u8 temp2;
1429         struct aper_size_info_8 *current_size;
1430
1431         /* attbase - aperture base */
1432         /* the Intel 815 chipset spec. says that bits 29-31 in the
1433         * ATTBASE register are reserved -> try not to write them */
1434         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1435                 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
1436                 return -EINVAL;
1437         }
1438
1439         current_size = A_SIZE_8(agp_bridge->current_size);
1440
1441         /* aperture size */
1442         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1443                         current_size->size_value);
1444
1445         /* address to map to */
1446         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1447         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1448
1449         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1450         addr &= INTEL_815_ATTBASE_MASK;
1451         addr |= agp_bridge->gatt_bus_addr;
1452         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1453
1454         /* agpctrl */
1455         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1456
1457         /* apcont */
1458         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1459         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1460
1461         /* clear any possible error conditions */
1462         /* Oddness : this chipset seems to have no ERRSTS register ! */
1463         return 0;
1464 }
1465
1466 static void intel_820_tlbflush(struct agp_memory *mem)
1467 {
1468         return;
1469 }
1470
1471 static void intel_820_cleanup(void)
1472 {
1473         u8 temp;
1474         struct aper_size_info_8 *previous_size;
1475
1476         previous_size = A_SIZE_8(agp_bridge->previous_size);
1477         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1478         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1479                         temp & ~(1 << 1));
1480         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1481                         previous_size->size_value);
1482 }
1483
1484
1485 static int intel_820_configure(void)
1486 {
1487         u32 temp;
1488         u8 temp2;
1489         struct aper_size_info_8 *current_size;
1490
1491         current_size = A_SIZE_8(agp_bridge->current_size);
1492
1493         /* aperture size */
1494         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1495
1496         /* address to map to */
1497         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1498         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1499
1500         /* attbase - aperture base */
1501         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1502
1503         /* agpctrl */
1504         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1505
1506         /* global enable aperture access */
1507         /* This flag is not accessed through MCHCFG register as in */
1508         /* i850 chipset. */
1509         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1510         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1511         /* clear any possible AGP-related error conditions */
1512         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1513         return 0;
1514 }
1515
1516 static int intel_840_configure(void)
1517 {
1518         u32 temp;
1519         u16 temp2;
1520         struct aper_size_info_8 *current_size;
1521
1522         current_size = A_SIZE_8(agp_bridge->current_size);
1523
1524         /* aperture size */
1525         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1526
1527         /* address to map to */
1528         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1529         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1530
1531         /* attbase - aperture base */
1532         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1533
1534         /* agpctrl */
1535         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1536
1537         /* mcgcfg */
1538         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1539         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1540         /* clear any possible error conditions */
1541         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1542         return 0;
1543 }
1544
1545 static int intel_845_configure(void)
1546 {
1547         u32 temp;
1548         u8 temp2;
1549         struct aper_size_info_8 *current_size;
1550
1551         current_size = A_SIZE_8(agp_bridge->current_size);
1552
1553         /* aperture size */
1554         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1555
1556         if (agp_bridge->apbase_config != 0) {
1557                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1558                                        agp_bridge->apbase_config);
1559         } else {
1560                 /* address to map to */
1561                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1562                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1563                 agp_bridge->apbase_config = temp;
1564         }
1565
1566         /* attbase - aperture base */
1567         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1568
1569         /* agpctrl */
1570         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1571
1572         /* agpm */
1573         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1574         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1575         /* clear any possible error conditions */
1576         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1577
1578         intel_i830_setup_flush();
1579         return 0;
1580 }
1581
1582 static int intel_850_configure(void)
1583 {
1584         u32 temp;
1585         u16 temp2;
1586         struct aper_size_info_8 *current_size;
1587
1588         current_size = A_SIZE_8(agp_bridge->current_size);
1589
1590         /* aperture size */
1591         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1592
1593         /* address to map to */
1594         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1595         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1596
1597         /* attbase - aperture base */
1598         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1599
1600         /* agpctrl */
1601         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1602
1603         /* mcgcfg */
1604         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1605         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1606         /* clear any possible AGP-related error conditions */
1607         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1608         return 0;
1609 }
1610
1611 static int intel_860_configure(void)
1612 {
1613         u32 temp;
1614         u16 temp2;
1615         struct aper_size_info_8 *current_size;
1616
1617         current_size = A_SIZE_8(agp_bridge->current_size);
1618
1619         /* aperture size */
1620         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1621
1622         /* address to map to */
1623         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1624         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1625
1626         /* attbase - aperture base */
1627         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1628
1629         /* agpctrl */
1630         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1631
1632         /* mcgcfg */
1633         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1634         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1635         /* clear any possible AGP-related error conditions */
1636         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1637         return 0;
1638 }
1639
1640 static int intel_830mp_configure(void)
1641 {
1642         u32 temp;
1643         u16 temp2;
1644         struct aper_size_info_8 *current_size;
1645
1646         current_size = A_SIZE_8(agp_bridge->current_size);
1647
1648         /* aperture size */
1649         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1650
1651         /* address to map to */
1652         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1653         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1654
1655         /* attbase - aperture base */
1656         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1657
1658         /* agpctrl */
1659         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1660
1661         /* gmch */
1662         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1663         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1664         /* clear any possible AGP-related error conditions */
1665         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1666         return 0;
1667 }
1668
1669 static int intel_7505_configure(void)
1670 {
1671         u32 temp;
1672         u16 temp2;
1673         struct aper_size_info_8 *current_size;
1674
1675         current_size = A_SIZE_8(agp_bridge->current_size);
1676
1677         /* aperture size */
1678         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1679
1680         /* address to map to */
1681         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1682         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1683
1684         /* attbase - aperture base */
1685         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1686
1687         /* agpctrl */
1688         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1689
1690         /* mchcfg */
1691         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1692         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1693
1694         return 0;
1695 }
1696
1697 /* Setup function */
1698 static const struct gatt_mask intel_generic_masks[] =
1699 {
1700         {.mask = 0x00000017, .type = 0}
1701 };
1702
1703 static const struct aper_size_info_8 intel_815_sizes[2] =
1704 {
1705         {64, 16384, 4, 0},
1706         {32, 8192, 3, 8},
1707 };
1708
1709 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1710 {
1711         {256, 65536, 6, 0},
1712         {128, 32768, 5, 32},
1713         {64, 16384, 4, 48},
1714         {32, 8192, 3, 56},
1715         {16, 4096, 2, 60},
1716         {8, 2048, 1, 62},
1717         {4, 1024, 0, 63}
1718 };
1719
1720 static const struct aper_size_info_16 intel_generic_sizes[7] =
1721 {
1722         {256, 65536, 6, 0},
1723         {128, 32768, 5, 32},
1724         {64, 16384, 4, 48},
1725         {32, 8192, 3, 56},
1726         {16, 4096, 2, 60},
1727         {8, 2048, 1, 62},
1728         {4, 1024, 0, 63}
1729 };
1730
1731 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1732 {
1733         {256, 65536, 6, 0},
1734         {128, 32768, 5, 32},
1735         {64, 16384, 4, 48},
1736         {32, 8192, 3, 56}
1737 };
1738
1739 static const struct agp_bridge_driver intel_generic_driver = {
1740         .owner                  = THIS_MODULE,
1741         .aperture_sizes         = intel_generic_sizes,
1742         .size_type              = U16_APER_SIZE,
1743         .num_aperture_sizes     = 7,
1744         .configure              = intel_configure,
1745         .fetch_size             = intel_fetch_size,
1746         .cleanup                = intel_cleanup,
1747         .tlb_flush              = intel_tlbflush,
1748         .mask_memory            = agp_generic_mask_memory,
1749         .masks                  = intel_generic_masks,
1750         .agp_enable             = agp_generic_enable,
1751         .cache_flush            = global_cache_flush,
1752         .create_gatt_table      = agp_generic_create_gatt_table,
1753         .free_gatt_table        = agp_generic_free_gatt_table,
1754         .insert_memory          = agp_generic_insert_memory,
1755         .remove_memory          = agp_generic_remove_memory,
1756         .alloc_by_type          = agp_generic_alloc_by_type,
1757         .free_by_type           = agp_generic_free_by_type,
1758         .agp_alloc_page         = agp_generic_alloc_page,
1759         .agp_alloc_pages        = agp_generic_alloc_pages,
1760         .agp_destroy_page       = agp_generic_destroy_page,
1761         .agp_destroy_pages      = agp_generic_destroy_pages,
1762         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1763 };
1764
1765 static const struct agp_bridge_driver intel_810_driver = {
1766         .owner                  = THIS_MODULE,
1767         .aperture_sizes         = intel_i810_sizes,
1768         .size_type              = FIXED_APER_SIZE,
1769         .num_aperture_sizes     = 2,
1770         .needs_scratch_page     = true,
1771         .configure              = intel_i810_configure,
1772         .fetch_size             = intel_i810_fetch_size,
1773         .cleanup                = intel_i810_cleanup,
1774         .tlb_flush              = intel_i810_tlbflush,
1775         .mask_memory            = intel_i810_mask_memory,
1776         .masks                  = intel_i810_masks,
1777         .agp_enable             = intel_i810_agp_enable,
1778         .cache_flush            = global_cache_flush,
1779         .create_gatt_table      = agp_generic_create_gatt_table,
1780         .free_gatt_table        = agp_generic_free_gatt_table,
1781         .insert_memory          = intel_i810_insert_entries,
1782         .remove_memory          = intel_i810_remove_entries,
1783         .alloc_by_type          = intel_i810_alloc_by_type,
1784         .free_by_type           = intel_i810_free_by_type,
1785         .agp_alloc_page         = agp_generic_alloc_page,
1786         .agp_alloc_pages        = agp_generic_alloc_pages,
1787         .agp_destroy_page       = agp_generic_destroy_page,
1788         .agp_destroy_pages      = agp_generic_destroy_pages,
1789         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1790 };
1791
1792 static const struct agp_bridge_driver intel_815_driver = {
1793         .owner                  = THIS_MODULE,
1794         .aperture_sizes         = intel_815_sizes,
1795         .size_type              = U8_APER_SIZE,
1796         .num_aperture_sizes     = 2,
1797         .configure              = intel_815_configure,
1798         .fetch_size             = intel_815_fetch_size,
1799         .cleanup                = intel_8xx_cleanup,
1800         .tlb_flush              = intel_8xx_tlbflush,
1801         .mask_memory            = agp_generic_mask_memory,
1802         .masks                  = intel_generic_masks,
1803         .agp_enable             = agp_generic_enable,
1804         .cache_flush            = global_cache_flush,
1805         .create_gatt_table      = agp_generic_create_gatt_table,
1806         .free_gatt_table        = agp_generic_free_gatt_table,
1807         .insert_memory          = agp_generic_insert_memory,
1808         .remove_memory          = agp_generic_remove_memory,
1809         .alloc_by_type          = agp_generic_alloc_by_type,
1810         .free_by_type           = agp_generic_free_by_type,
1811         .agp_alloc_page         = agp_generic_alloc_page,
1812         .agp_alloc_pages        = agp_generic_alloc_pages,
1813         .agp_destroy_page       = agp_generic_destroy_page,
1814         .agp_destroy_pages      = agp_generic_destroy_pages,
1815         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1816 };
1817
1818 static const struct agp_bridge_driver intel_830_driver = {
1819         .owner                  = THIS_MODULE,
1820         .aperture_sizes         = intel_i830_sizes,
1821         .size_type              = FIXED_APER_SIZE,
1822         .num_aperture_sizes     = 4,
1823         .needs_scratch_page     = true,
1824         .configure              = intel_i830_configure,
1825         .fetch_size             = intel_i830_fetch_size,
1826         .cleanup                = intel_i830_cleanup,
1827         .tlb_flush              = intel_i810_tlbflush,
1828         .mask_memory            = intel_i810_mask_memory,
1829         .masks                  = intel_i810_masks,
1830         .agp_enable             = intel_i810_agp_enable,
1831         .cache_flush            = global_cache_flush,
1832         .create_gatt_table      = intel_i830_create_gatt_table,
1833         .free_gatt_table        = intel_i830_free_gatt_table,
1834         .insert_memory          = intel_i830_insert_entries,
1835         .remove_memory          = intel_i830_remove_entries,
1836         .alloc_by_type          = intel_i830_alloc_by_type,
1837         .free_by_type           = intel_i810_free_by_type,
1838         .agp_alloc_page         = agp_generic_alloc_page,
1839         .agp_alloc_pages        = agp_generic_alloc_pages,
1840         .agp_destroy_page       = agp_generic_destroy_page,
1841         .agp_destroy_pages      = agp_generic_destroy_pages,
1842         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1843         .chipset_flush          = intel_i830_chipset_flush,
1844 };
1845
1846 static const struct agp_bridge_driver intel_820_driver = {
1847         .owner                  = THIS_MODULE,
1848         .aperture_sizes         = intel_8xx_sizes,
1849         .size_type              = U8_APER_SIZE,
1850         .num_aperture_sizes     = 7,
1851         .configure              = intel_820_configure,
1852         .fetch_size             = intel_8xx_fetch_size,
1853         .cleanup                = intel_820_cleanup,
1854         .tlb_flush              = intel_820_tlbflush,
1855         .mask_memory            = agp_generic_mask_memory,
1856         .masks                  = intel_generic_masks,
1857         .agp_enable             = agp_generic_enable,
1858         .cache_flush            = global_cache_flush,
1859         .create_gatt_table      = agp_generic_create_gatt_table,
1860         .free_gatt_table        = agp_generic_free_gatt_table,
1861         .insert_memory          = agp_generic_insert_memory,
1862         .remove_memory          = agp_generic_remove_memory,
1863         .alloc_by_type          = agp_generic_alloc_by_type,
1864         .free_by_type           = agp_generic_free_by_type,
1865         .agp_alloc_page         = agp_generic_alloc_page,
1866         .agp_alloc_pages        = agp_generic_alloc_pages,
1867         .agp_destroy_page       = agp_generic_destroy_page,
1868         .agp_destroy_pages      = agp_generic_destroy_pages,
1869         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1870 };
1871
1872 static const struct agp_bridge_driver intel_830mp_driver = {
1873         .owner                  = THIS_MODULE,
1874         .aperture_sizes         = intel_830mp_sizes,
1875         .size_type              = U8_APER_SIZE,
1876         .num_aperture_sizes     = 4,
1877         .configure              = intel_830mp_configure,
1878         .fetch_size             = intel_8xx_fetch_size,
1879         .cleanup                = intel_8xx_cleanup,
1880         .tlb_flush              = intel_8xx_tlbflush,
1881         .mask_memory            = agp_generic_mask_memory,
1882         .masks                  = intel_generic_masks,
1883         .agp_enable             = agp_generic_enable,
1884         .cache_flush            = global_cache_flush,
1885         .create_gatt_table      = agp_generic_create_gatt_table,
1886         .free_gatt_table        = agp_generic_free_gatt_table,
1887         .insert_memory          = agp_generic_insert_memory,
1888         .remove_memory          = agp_generic_remove_memory,
1889         .alloc_by_type          = agp_generic_alloc_by_type,
1890         .free_by_type           = agp_generic_free_by_type,
1891         .agp_alloc_page         = agp_generic_alloc_page,
1892         .agp_alloc_pages        = agp_generic_alloc_pages,
1893         .agp_destroy_page       = agp_generic_destroy_page,
1894         .agp_destroy_pages      = agp_generic_destroy_pages,
1895         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1896 };
1897
1898 static const struct agp_bridge_driver intel_840_driver = {
1899         .owner                  = THIS_MODULE,
1900         .aperture_sizes         = intel_8xx_sizes,
1901         .size_type              = U8_APER_SIZE,
1902         .num_aperture_sizes     = 7,
1903         .configure              = intel_840_configure,
1904         .fetch_size             = intel_8xx_fetch_size,
1905         .cleanup                = intel_8xx_cleanup,
1906         .tlb_flush              = intel_8xx_tlbflush,
1907         .mask_memory            = agp_generic_mask_memory,
1908         .masks                  = intel_generic_masks,
1909         .agp_enable             = agp_generic_enable,
1910         .cache_flush            = global_cache_flush,
1911         .create_gatt_table      = agp_generic_create_gatt_table,
1912         .free_gatt_table        = agp_generic_free_gatt_table,
1913         .insert_memory          = agp_generic_insert_memory,
1914         .remove_memory          = agp_generic_remove_memory,
1915         .alloc_by_type          = agp_generic_alloc_by_type,
1916         .free_by_type           = agp_generic_free_by_type,
1917         .agp_alloc_page         = agp_generic_alloc_page,
1918         .agp_alloc_pages        = agp_generic_alloc_pages,
1919         .agp_destroy_page       = agp_generic_destroy_page,
1920         .agp_destroy_pages      = agp_generic_destroy_pages,
1921         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1922 };
1923
1924 static const struct agp_bridge_driver intel_845_driver = {
1925         .owner                  = THIS_MODULE,
1926         .aperture_sizes         = intel_8xx_sizes,
1927         .size_type              = U8_APER_SIZE,
1928         .num_aperture_sizes     = 7,
1929         .configure              = intel_845_configure,
1930         .fetch_size             = intel_8xx_fetch_size,
1931         .cleanup                = intel_8xx_cleanup,
1932         .tlb_flush              = intel_8xx_tlbflush,
1933         .mask_memory            = agp_generic_mask_memory,
1934         .masks                  = intel_generic_masks,
1935         .agp_enable             = agp_generic_enable,
1936         .cache_flush            = global_cache_flush,
1937         .create_gatt_table      = agp_generic_create_gatt_table,
1938         .free_gatt_table        = agp_generic_free_gatt_table,
1939         .insert_memory          = agp_generic_insert_memory,
1940         .remove_memory          = agp_generic_remove_memory,
1941         .alloc_by_type          = agp_generic_alloc_by_type,
1942         .free_by_type           = agp_generic_free_by_type,
1943         .agp_alloc_page         = agp_generic_alloc_page,
1944         .agp_alloc_pages        = agp_generic_alloc_pages,
1945         .agp_destroy_page       = agp_generic_destroy_page,
1946         .agp_destroy_pages      = agp_generic_destroy_pages,
1947         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1948         .chipset_flush          = intel_i830_chipset_flush,
1949 };
1950
1951 static const struct agp_bridge_driver intel_850_driver = {
1952         .owner                  = THIS_MODULE,
1953         .aperture_sizes         = intel_8xx_sizes,
1954         .size_type              = U8_APER_SIZE,
1955         .num_aperture_sizes     = 7,
1956         .configure              = intel_850_configure,
1957         .fetch_size             = intel_8xx_fetch_size,
1958         .cleanup                = intel_8xx_cleanup,
1959         .tlb_flush              = intel_8xx_tlbflush,
1960         .mask_memory            = agp_generic_mask_memory,
1961         .masks                  = intel_generic_masks,
1962         .agp_enable             = agp_generic_enable,
1963         .cache_flush            = global_cache_flush,
1964         .create_gatt_table      = agp_generic_create_gatt_table,
1965         .free_gatt_table        = agp_generic_free_gatt_table,
1966         .insert_memory          = agp_generic_insert_memory,
1967         .remove_memory          = agp_generic_remove_memory,
1968         .alloc_by_type          = agp_generic_alloc_by_type,
1969         .free_by_type           = agp_generic_free_by_type,
1970         .agp_alloc_page         = agp_generic_alloc_page,
1971         .agp_alloc_pages        = agp_generic_alloc_pages,
1972         .agp_destroy_page       = agp_generic_destroy_page,
1973         .agp_destroy_pages      = agp_generic_destroy_pages,
1974         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1975 };
1976
1977 static const struct agp_bridge_driver intel_860_driver = {
1978         .owner                  = THIS_MODULE,
1979         .aperture_sizes         = intel_8xx_sizes,
1980         .size_type              = U8_APER_SIZE,
1981         .num_aperture_sizes     = 7,
1982         .configure              = intel_860_configure,
1983         .fetch_size             = intel_8xx_fetch_size,
1984         .cleanup                = intel_8xx_cleanup,
1985         .tlb_flush              = intel_8xx_tlbflush,
1986         .mask_memory            = agp_generic_mask_memory,
1987         .masks                  = intel_generic_masks,
1988         .agp_enable             = agp_generic_enable,
1989         .cache_flush            = global_cache_flush,
1990         .create_gatt_table      = agp_generic_create_gatt_table,
1991         .free_gatt_table        = agp_generic_free_gatt_table,
1992         .insert_memory          = agp_generic_insert_memory,
1993         .remove_memory          = agp_generic_remove_memory,
1994         .alloc_by_type          = agp_generic_alloc_by_type,
1995         .free_by_type           = agp_generic_free_by_type,
1996         .agp_alloc_page         = agp_generic_alloc_page,
1997         .agp_alloc_pages        = agp_generic_alloc_pages,
1998         .agp_destroy_page       = agp_generic_destroy_page,
1999         .agp_destroy_pages      = agp_generic_destroy_pages,
2000         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2001 };
2002
2003 static const struct agp_bridge_driver intel_915_driver = {
2004         .owner                  = THIS_MODULE,
2005         .aperture_sizes         = intel_i830_sizes,
2006         .size_type              = FIXED_APER_SIZE,
2007         .num_aperture_sizes     = 4,
2008         .needs_scratch_page     = true,
2009         .configure              = intel_i915_configure,
2010         .fetch_size             = intel_i9xx_fetch_size,
2011         .cleanup                = intel_i915_cleanup,
2012         .tlb_flush              = intel_i810_tlbflush,
2013         .mask_memory            = intel_i810_mask_memory,
2014         .masks                  = intel_i810_masks,
2015         .agp_enable             = intel_i810_agp_enable,
2016         .cache_flush            = global_cache_flush,
2017         .create_gatt_table      = intel_i915_create_gatt_table,
2018         .free_gatt_table        = intel_i830_free_gatt_table,
2019         .insert_memory          = intel_i915_insert_entries,
2020         .remove_memory          = intel_i915_remove_entries,
2021         .alloc_by_type          = intel_i830_alloc_by_type,
2022         .free_by_type           = intel_i810_free_by_type,
2023         .agp_alloc_page         = agp_generic_alloc_page,
2024         .agp_alloc_pages        = agp_generic_alloc_pages,
2025         .agp_destroy_page       = agp_generic_destroy_page,
2026         .agp_destroy_pages      = agp_generic_destroy_pages,
2027         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2028         .chipset_flush          = intel_i915_chipset_flush,
2029 };
2030
2031 static const struct agp_bridge_driver intel_i965_driver = {
2032         .owner                  = THIS_MODULE,
2033         .aperture_sizes         = intel_i830_sizes,
2034         .size_type              = FIXED_APER_SIZE,
2035         .num_aperture_sizes     = 4,
2036         .needs_scratch_page     = true,
2037         .configure              = intel_i915_configure,
2038         .fetch_size             = intel_i9xx_fetch_size,
2039         .cleanup                = intel_i915_cleanup,
2040         .tlb_flush              = intel_i810_tlbflush,
2041         .mask_memory            = intel_i965_mask_memory,
2042         .masks                  = intel_i810_masks,
2043         .agp_enable             = intel_i810_agp_enable,
2044         .cache_flush            = global_cache_flush,
2045         .create_gatt_table      = intel_i965_create_gatt_table,
2046         .free_gatt_table        = intel_i830_free_gatt_table,
2047         .insert_memory          = intel_i915_insert_entries,
2048         .remove_memory          = intel_i915_remove_entries,
2049         .alloc_by_type          = intel_i830_alloc_by_type,
2050         .free_by_type           = intel_i810_free_by_type,
2051         .agp_alloc_page         = agp_generic_alloc_page,
2052         .agp_alloc_pages        = agp_generic_alloc_pages,
2053         .agp_destroy_page       = agp_generic_destroy_page,
2054         .agp_destroy_pages      = agp_generic_destroy_pages,
2055         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2056         .chipset_flush          = intel_i915_chipset_flush,
2057 };
2058
2059 static const struct agp_bridge_driver intel_7505_driver = {
2060         .owner                  = THIS_MODULE,
2061         .aperture_sizes         = intel_8xx_sizes,
2062         .size_type              = U8_APER_SIZE,
2063         .num_aperture_sizes     = 7,
2064         .configure              = intel_7505_configure,
2065         .fetch_size             = intel_8xx_fetch_size,
2066         .cleanup                = intel_8xx_cleanup,
2067         .tlb_flush              = intel_8xx_tlbflush,
2068         .mask_memory            = agp_generic_mask_memory,
2069         .masks                  = intel_generic_masks,
2070         .agp_enable             = agp_generic_enable,
2071         .cache_flush            = global_cache_flush,
2072         .create_gatt_table      = agp_generic_create_gatt_table,
2073         .free_gatt_table        = agp_generic_free_gatt_table,
2074         .insert_memory          = agp_generic_insert_memory,
2075         .remove_memory          = agp_generic_remove_memory,
2076         .alloc_by_type          = agp_generic_alloc_by_type,
2077         .free_by_type           = agp_generic_free_by_type,
2078         .agp_alloc_page         = agp_generic_alloc_page,
2079         .agp_alloc_pages        = agp_generic_alloc_pages,
2080         .agp_destroy_page       = agp_generic_destroy_page,
2081         .agp_destroy_pages      = agp_generic_destroy_pages,
2082         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2083 };
2084
2085 static const struct agp_bridge_driver intel_g33_driver = {
2086         .owner                  = THIS_MODULE,
2087         .aperture_sizes         = intel_i830_sizes,
2088         .size_type              = FIXED_APER_SIZE,
2089         .num_aperture_sizes     = 4,
2090         .needs_scratch_page     = true,
2091         .configure              = intel_i915_configure,
2092         .fetch_size             = intel_i9xx_fetch_size,
2093         .cleanup                = intel_i915_cleanup,
2094         .tlb_flush              = intel_i810_tlbflush,
2095         .mask_memory            = intel_i965_mask_memory,
2096         .masks                  = intel_i810_masks,
2097         .agp_enable             = intel_i810_agp_enable,
2098         .cache_flush            = global_cache_flush,
2099         .create_gatt_table      = intel_i915_create_gatt_table,
2100         .free_gatt_table        = intel_i830_free_gatt_table,
2101         .insert_memory          = intel_i915_insert_entries,
2102         .remove_memory          = intel_i915_remove_entries,
2103         .alloc_by_type          = intel_i830_alloc_by_type,
2104         .free_by_type           = intel_i810_free_by_type,
2105         .agp_alloc_page         = agp_generic_alloc_page,
2106         .agp_alloc_pages        = agp_generic_alloc_pages,
2107         .agp_destroy_page       = agp_generic_destroy_page,
2108         .agp_destroy_pages      = agp_generic_destroy_pages,
2109         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2110         .chipset_flush          = intel_i915_chipset_flush,
2111 };
2112
2113 static int find_gmch(u16 device)
2114 {
2115         struct pci_dev *gmch_device;
2116
2117         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2118         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
2119                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
2120                                              device, gmch_device);
2121         }
2122
2123         if (!gmch_device)
2124                 return 0;
2125
2126         intel_private.pcidev = gmch_device;
2127         return 1;
2128 }
2129
2130 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
2131  * driver and gmch_driver must be non-null, and find_gmch will determine
2132  * which one should be used if a gmch_chip_id is present.
2133  */
2134 static const struct intel_driver_description {
2135         unsigned int chip_id;
2136         unsigned int gmch_chip_id;
2137         unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
2138         char *name;
2139         const struct agp_bridge_driver *driver;
2140         const struct agp_bridge_driver *gmch_driver;
2141 } intel_agp_chipsets[] = {
2142         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2143         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2144         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2145         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2146                 NULL, &intel_810_driver },
2147         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2148                 NULL, &intel_810_driver },
2149         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2150                 NULL, &intel_810_driver },
2151         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2152                 &intel_815_driver, &intel_810_driver },
2153         { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2154         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2155         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2156                 &intel_830mp_driver, &intel_830_driver },
2157         { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2158         { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2159         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2160                 &intel_845_driver, &intel_830_driver },
2161         { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2162         { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854",
2163                 &intel_845_driver, &intel_830_driver },
2164         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2165         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2166                 &intel_845_driver, &intel_830_driver },
2167         { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2168         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2169                 &intel_845_driver, &intel_830_driver },
2170         { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2171         { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2172                 NULL, &intel_915_driver },
2173         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2174                 NULL, &intel_915_driver },
2175         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2176                 NULL, &intel_915_driver },
2177         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2178                 NULL, &intel_915_driver },
2179         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2180                 NULL, &intel_915_driver },
2181         { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2182                 NULL, &intel_915_driver },
2183         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2184                 NULL, &intel_i965_driver },
2185         { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
2186                 NULL, &intel_i965_driver },
2187         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2188                 NULL, &intel_i965_driver },
2189         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2190                 NULL, &intel_i965_driver },
2191         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2192                 NULL, &intel_i965_driver },
2193         { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2194                 NULL, &intel_i965_driver },
2195         { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2196         { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2197         { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2198                 NULL, &intel_g33_driver },
2199         { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2200                 NULL, &intel_g33_driver },
2201         { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2202                 NULL, &intel_g33_driver },
2203         { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, 0, "IGD",
2204                 NULL, &intel_g33_driver },
2205         { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, 0, "IGD",
2206                 NULL, &intel_g33_driver },
2207         { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
2208             "Mobile Intel® GM45 Express", NULL, &intel_i965_driver },
2209         { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
2210             "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2211         { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2212             "Q45/Q43", NULL, &intel_i965_driver },
2213         { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2214             "G45/G43", NULL, &intel_i965_driver },
2215         { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0,
2216             "B43", NULL, &intel_i965_driver },
2217         { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2218             "G41", NULL, &intel_i965_driver },
2219         { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0,
2220             "IGDNG/D", NULL, &intel_i965_driver },
2221         { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2222             "IGDNG/M", NULL, &intel_i965_driver },
2223         { PCI_DEVICE_ID_INTEL_IGDNG_MA_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2224             "IGDNG/MA", NULL, &intel_i965_driver },
2225         { 0, 0, 0, NULL, NULL, NULL }
2226 };
2227
2228 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2229                                      const struct pci_device_id *ent)
2230 {
2231         struct agp_bridge_data *bridge;
2232         u8 cap_ptr = 0;
2233         struct resource *r;
2234         int i;
2235
2236         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2237
2238         bridge = agp_alloc_bridge();
2239         if (!bridge)
2240                 return -ENOMEM;
2241
2242         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2243                 /* In case that multiple models of gfx chip may
2244                    stand on same host bridge type, this can be
2245                    sure we detect the right IGD. */
2246                 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2247                         if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2248                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2249                                 bridge->driver =
2250                                         intel_agp_chipsets[i].gmch_driver;
2251                                 break;
2252                         } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2253                                 continue;
2254                         } else {
2255                                 bridge->driver = intel_agp_chipsets[i].driver;
2256                                 break;
2257                         }
2258                 }
2259         }
2260
2261         if (intel_agp_chipsets[i].name == NULL) {
2262                 if (cap_ptr)
2263                         dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
2264                                  pdev->vendor, pdev->device);
2265                 agp_put_bridge(bridge);
2266                 return -ENODEV;
2267         }
2268
2269         if (bridge->driver == NULL) {
2270                 /* bridge has no AGP and no IGD detected */
2271                 if (cap_ptr)
2272                         dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
2273                                  intel_agp_chipsets[i].gmch_chip_id);
2274                 agp_put_bridge(bridge);
2275                 return -ENODEV;
2276         }
2277
2278         bridge->dev = pdev;
2279         bridge->capndx = cap_ptr;
2280         bridge->dev_private_data = &intel_private;
2281
2282         dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
2283
2284         /*
2285         * The following fixes the case where the BIOS has "forgotten" to
2286         * provide an address range for the GART.
2287         * 20030610 - hamish@zot.org
2288         */
2289         r = &pdev->resource[0];
2290         if (!r->start && r->end) {
2291                 if (pci_assign_resource(pdev, 0)) {
2292                         dev_err(&pdev->dev, "can't assign resource 0\n");
2293                         agp_put_bridge(bridge);
2294                         return -ENODEV;
2295                 }
2296         }
2297
2298         /*
2299         * If the device has not been properly setup, the following will catch
2300         * the problem and should stop the system from crashing.
2301         * 20030610 - hamish@zot.org
2302         */
2303         if (pci_enable_device(pdev)) {
2304                 dev_err(&pdev->dev, "can't enable PCI device\n");
2305                 agp_put_bridge(bridge);
2306                 return -ENODEV;
2307         }
2308
2309         /* Fill in the mode register */
2310         if (cap_ptr) {
2311                 pci_read_config_dword(pdev,
2312                                 bridge->capndx+PCI_AGP_STATUS,
2313                                 &bridge->mode);
2314         }
2315
2316         pci_set_drvdata(pdev, bridge);
2317         return agp_add_bridge(bridge);
2318 }
2319
2320 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2321 {
2322         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2323
2324         agp_remove_bridge(bridge);
2325
2326         if (intel_private.pcidev)
2327                 pci_dev_put(intel_private.pcidev);
2328
2329         agp_put_bridge(bridge);
2330 }
2331
2332 #ifdef CONFIG_PM
2333 static int agp_intel_resume(struct pci_dev *pdev)
2334 {
2335         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2336         int ret_val;
2337
2338         pci_restore_state(pdev);
2339
2340         /* We should restore our graphics device's config space,
2341          * as host bridge (00:00) resumes before graphics device (02:00),
2342          * then our access to its pci space can work right.
2343          */
2344         if (intel_private.pcidev)
2345                 pci_restore_state(intel_private.pcidev);
2346
2347         if (bridge->driver == &intel_generic_driver)
2348                 intel_configure();
2349         else if (bridge->driver == &intel_850_driver)
2350                 intel_850_configure();
2351         else if (bridge->driver == &intel_845_driver)
2352                 intel_845_configure();
2353         else if (bridge->driver == &intel_830mp_driver)
2354                 intel_830mp_configure();
2355         else if (bridge->driver == &intel_915_driver)
2356                 intel_i915_configure();
2357         else if (bridge->driver == &intel_830_driver)
2358                 intel_i830_configure();
2359         else if (bridge->driver == &intel_810_driver)
2360                 intel_i810_configure();
2361         else if (bridge->driver == &intel_i965_driver)
2362                 intel_i915_configure();
2363
2364         ret_val = agp_rebind_memory();
2365         if (ret_val != 0)
2366                 return ret_val;
2367
2368         return 0;
2369 }
2370 #endif
2371
2372 static struct pci_device_id agp_intel_pci_table[] = {
2373 #define ID(x)                                           \
2374         {                                               \
2375         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
2376         .class_mask     = ~0,                           \
2377         .vendor         = PCI_VENDOR_ID_INTEL,          \
2378         .device         = x,                            \
2379         .subvendor      = PCI_ANY_ID,                   \
2380         .subdevice      = PCI_ANY_ID,                   \
2381         }
2382         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2383         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2384         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2385         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2386         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2387         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2388         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2389         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2390         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2391         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2392         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2393         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2394         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2395         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2396         ID(PCI_DEVICE_ID_INTEL_82854_HB),
2397         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2398         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2399         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2400         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2401         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2402         ID(PCI_DEVICE_ID_INTEL_7505_0),
2403         ID(PCI_DEVICE_ID_INTEL_7205_0),
2404         ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2405         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2406         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2407         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2408         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2409         ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2410         ID(PCI_DEVICE_ID_INTEL_IGDGM_HB),
2411         ID(PCI_DEVICE_ID_INTEL_IGDG_HB),
2412         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2413         ID(PCI_DEVICE_ID_INTEL_82G35_HB),
2414         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2415         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2416         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2417         ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2418         ID(PCI_DEVICE_ID_INTEL_G33_HB),
2419         ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2420         ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2421         ID(PCI_DEVICE_ID_INTEL_GM45_HB),
2422         ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
2423         ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2424         ID(PCI_DEVICE_ID_INTEL_G45_HB),
2425         ID(PCI_DEVICE_ID_INTEL_G41_HB),
2426         ID(PCI_DEVICE_ID_INTEL_B43_HB),
2427         ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB),
2428         ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB),
2429         ID(PCI_DEVICE_ID_INTEL_IGDNG_MA_HB),
2430         { }
2431 };
2432
2433 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2434
2435 static struct pci_driver agp_intel_pci_driver = {
2436         .name           = "agpgart-intel",
2437         .id_table       = agp_intel_pci_table,
2438         .probe          = agp_intel_probe,
2439         .remove         = __devexit_p(agp_intel_remove),
2440 #ifdef CONFIG_PM
2441         .resume         = agp_intel_resume,
2442 #endif
2443 };
2444
2445 static int __init agp_intel_init(void)
2446 {
2447         if (agp_off)
2448                 return -EINVAL;
2449         return pci_register_driver(&agp_intel_pci_driver);
2450 }
2451
2452 static void __exit agp_intel_cleanup(void)
2453 {
2454         pci_unregister_driver(&agp_intel_pci_driver);
2455 }
2456
2457 module_init(agp_intel_init);
2458 module_exit(agp_intel_cleanup);
2459
2460 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
2461 MODULE_LICENSE("GPL and additional rights");