2 * Intel GTT (Graphics Translation Table) routines
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
15 * /fairy-tale-mode off
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
26 #include "intel-agp.h"
27 #include <drm/intel-gtt.h>
30 * If we have Intel graphics, we're not going to have anything other than
31 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
32 * on the Intel IOMMU support (CONFIG_DMAR).
33 * Only newer chipsets need to bother with this, of course.
36 #define USE_PCI_DMA_API 1
38 #define USE_PCI_DMA_API 0
41 struct intel_gtt_driver {
43 unsigned int is_g33 : 1;
44 unsigned int is_pineview : 1;
45 unsigned int is_ironlake : 1;
46 unsigned int has_pgtbl_enable : 1;
47 unsigned int dma_mask_size : 8;
48 /* Chipset specific GTT setup */
50 /* This should undo anything done in ->setup() save the unmapping
51 * of the mmio register file, that's done in the generic code. */
52 void (*cleanup)(void);
53 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
54 /* Flags is a more or less chipset specific opaque value.
55 * For chipsets that need to support old ums (non-gem) code, this
56 * needs to be identical to the various supported agp memory types! */
57 bool (*check_flags)(unsigned int flags);
58 void (*chipset_flush)(void);
61 static struct _intel_private {
62 struct intel_gtt base;
63 const struct intel_gtt_driver *driver;
64 struct pci_dev *pcidev; /* device one */
65 struct pci_dev *bridge_dev;
66 u8 __iomem *registers;
67 phys_addr_t gtt_bus_addr;
68 phys_addr_t gma_bus_addr;
70 u32 __iomem *gtt; /* I915G */
71 bool clear_fake_agp; /* on first access via agp, fill with scratch */
72 int num_dcache_entries;
74 void __iomem *i9xx_flush_page;
75 void *i8xx_flush_page;
78 struct page *i8xx_page;
79 struct resource ifp_resource;
81 struct page *scratch_page;
82 dma_addr_t scratch_page_dma;
85 #define INTEL_GTT_GEN intel_private.driver->gen
86 #define IS_G33 intel_private.driver->is_g33
87 #define IS_PINEVIEW intel_private.driver->is_pineview
88 #define IS_IRONLAKE intel_private.driver->is_ironlake
89 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
91 int intel_gtt_map_memory(struct page **pages, unsigned int num_entries,
92 struct scatterlist **sg_list, int *num_sg)
95 struct scatterlist *sg;
99 return 0; /* already mapped (for e.g. resume */
101 DBG("try mapping %lu pages\n", (unsigned long)num_entries);
103 if (sg_alloc_table(&st, num_entries, GFP_KERNEL))
106 *sg_list = sg = st.sgl;
108 for (i = 0 ; i < num_entries; i++, sg = sg_next(sg))
109 sg_set_page(sg, pages[i], PAGE_SIZE, 0);
111 *num_sg = pci_map_sg(intel_private.pcidev, *sg_list,
112 num_entries, PCI_DMA_BIDIRECTIONAL);
113 if (unlikely(!*num_sg))
122 EXPORT_SYMBOL(intel_gtt_map_memory);
124 void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
127 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
129 pci_unmap_sg(intel_private.pcidev, sg_list,
130 num_sg, PCI_DMA_BIDIRECTIONAL);
133 st.orig_nents = st.nents = num_sg;
137 EXPORT_SYMBOL(intel_gtt_unmap_memory);
139 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
144 /* Exists to support ARGB cursors */
145 static struct page *i8xx_alloc_pages(void)
149 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
153 if (set_pages_uc(page, 4) < 0) {
154 set_pages_wb(page, 4);
155 __free_pages(page, 2);
159 atomic_inc(&agp_bridge->current_memory_agp);
163 static void i8xx_destroy_pages(struct page *page)
168 set_pages_wb(page, 4);
170 __free_pages(page, 2);
171 atomic_dec(&agp_bridge->current_memory_agp);
174 #define I810_GTT_ORDER 4
175 static int i810_setup(void)
180 /* i81x does not preallocate the gtt. It's always 64kb in size. */
181 gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
182 if (gtt_table == NULL)
184 intel_private.i81x_gtt_table = gtt_table;
186 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr);
187 reg_addr &= 0xfff80000;
189 intel_private.registers = ioremap(reg_addr, KB(64));
190 if (!intel_private.registers)
193 writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
194 intel_private.registers+I810_PGETBL_CTL);
196 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
198 if ((readl(intel_private.registers+I810_DRAM_CTL)
199 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
200 dev_info(&intel_private.pcidev->dev,
201 "detected 4MB dedicated video ram\n");
202 intel_private.num_dcache_entries = 1024;
208 static void i810_cleanup(void)
210 writel(0, intel_private.registers+I810_PGETBL_CTL);
211 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
214 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
219 if ((pg_start + mem->page_count)
220 > intel_private.num_dcache_entries)
223 if (!mem->is_flushed)
224 global_cache_flush();
226 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
227 dma_addr_t addr = i << PAGE_SHIFT;
228 intel_private.driver->write_entry(addr,
231 readl(intel_private.gtt+i-1);
237 * The i810/i830 requires a physical address to program its mouse
238 * pointer into hardware.
239 * However the Xserver still writes to it through the agp aperture.
241 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
243 struct agp_memory *new;
247 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
250 /* kludge to get 4 physical pages for ARGB cursor */
251 page = i8xx_alloc_pages();
260 new = agp_create_memory(pg_count);
264 new->pages[0] = page;
266 /* kludge to get 4 physical pages for ARGB cursor */
267 new->pages[1] = new->pages[0] + 1;
268 new->pages[2] = new->pages[1] + 1;
269 new->pages[3] = new->pages[2] + 1;
271 new->page_count = pg_count;
272 new->num_scratch_pages = pg_count;
273 new->type = AGP_PHYS_MEMORY;
274 new->physical = page_to_phys(new->pages[0]);
278 static void intel_i810_free_by_type(struct agp_memory *curr)
280 agp_free_key(curr->key);
281 if (curr->type == AGP_PHYS_MEMORY) {
282 if (curr->page_count == 4)
283 i8xx_destroy_pages(curr->pages[0]);
285 agp_bridge->driver->agp_destroy_page(curr->pages[0],
286 AGP_PAGE_DESTROY_UNMAP);
287 agp_bridge->driver->agp_destroy_page(curr->pages[0],
288 AGP_PAGE_DESTROY_FREE);
290 agp_free_page_array(curr);
295 static int intel_gtt_setup_scratch_page(void)
300 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
304 set_pages_uc(page, 1);
306 if (intel_private.base.needs_dmar) {
307 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
308 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
309 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
312 intel_private.scratch_page_dma = dma_addr;
314 intel_private.scratch_page_dma = page_to_phys(page);
316 intel_private.scratch_page = page;
321 static void i810_write_entry(dma_addr_t addr, unsigned int entry,
324 u32 pte_flags = I810_PTE_VALID;
327 case AGP_DCACHE_MEMORY:
328 pte_flags |= I810_PTE_LOCAL;
330 case AGP_USER_CACHED_MEMORY:
331 pte_flags |= I830_PTE_SYSTEM_CACHED;
335 writel(addr | pte_flags, intel_private.gtt + entry);
338 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
346 static unsigned int intel_gtt_stolen_size(void)
351 static const int ddt[4] = { 0, 16, 32, 64 };
352 unsigned int stolen_size = 0;
354 if (INTEL_GTT_GEN == 1)
355 return 0; /* no stolen mem on i81x */
357 pci_read_config_word(intel_private.bridge_dev,
358 I830_GMCH_CTRL, &gmch_ctrl);
360 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
361 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
362 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
363 case I830_GMCH_GMS_STOLEN_512:
364 stolen_size = KB(512);
366 case I830_GMCH_GMS_STOLEN_1024:
369 case I830_GMCH_GMS_STOLEN_8192:
372 case I830_GMCH_GMS_LOCAL:
373 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
374 stolen_size = (I830_RDRAM_ND(rdct) + 1) *
375 MB(ddt[I830_RDRAM_DDT(rdct)]);
382 } else if (INTEL_GTT_GEN == 6) {
384 * SandyBridge has new memory control reg at 0x50.w
387 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
388 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
389 case SNB_GMCH_GMS_STOLEN_32M:
390 stolen_size = MB(32);
392 case SNB_GMCH_GMS_STOLEN_64M:
393 stolen_size = MB(64);
395 case SNB_GMCH_GMS_STOLEN_96M:
396 stolen_size = MB(96);
398 case SNB_GMCH_GMS_STOLEN_128M:
399 stolen_size = MB(128);
401 case SNB_GMCH_GMS_STOLEN_160M:
402 stolen_size = MB(160);
404 case SNB_GMCH_GMS_STOLEN_192M:
405 stolen_size = MB(192);
407 case SNB_GMCH_GMS_STOLEN_224M:
408 stolen_size = MB(224);
410 case SNB_GMCH_GMS_STOLEN_256M:
411 stolen_size = MB(256);
413 case SNB_GMCH_GMS_STOLEN_288M:
414 stolen_size = MB(288);
416 case SNB_GMCH_GMS_STOLEN_320M:
417 stolen_size = MB(320);
419 case SNB_GMCH_GMS_STOLEN_352M:
420 stolen_size = MB(352);
422 case SNB_GMCH_GMS_STOLEN_384M:
423 stolen_size = MB(384);
425 case SNB_GMCH_GMS_STOLEN_416M:
426 stolen_size = MB(416);
428 case SNB_GMCH_GMS_STOLEN_448M:
429 stolen_size = MB(448);
431 case SNB_GMCH_GMS_STOLEN_480M:
432 stolen_size = MB(480);
434 case SNB_GMCH_GMS_STOLEN_512M:
435 stolen_size = MB(512);
439 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
440 case I855_GMCH_GMS_STOLEN_1M:
443 case I855_GMCH_GMS_STOLEN_4M:
446 case I855_GMCH_GMS_STOLEN_8M:
449 case I855_GMCH_GMS_STOLEN_16M:
450 stolen_size = MB(16);
452 case I855_GMCH_GMS_STOLEN_32M:
453 stolen_size = MB(32);
455 case I915_GMCH_GMS_STOLEN_48M:
456 stolen_size = MB(48);
458 case I915_GMCH_GMS_STOLEN_64M:
459 stolen_size = MB(64);
461 case G33_GMCH_GMS_STOLEN_128M:
462 stolen_size = MB(128);
464 case G33_GMCH_GMS_STOLEN_256M:
465 stolen_size = MB(256);
467 case INTEL_GMCH_GMS_STOLEN_96M:
468 stolen_size = MB(96);
470 case INTEL_GMCH_GMS_STOLEN_160M:
471 stolen_size = MB(160);
473 case INTEL_GMCH_GMS_STOLEN_224M:
474 stolen_size = MB(224);
476 case INTEL_GMCH_GMS_STOLEN_352M:
477 stolen_size = MB(352);
485 if (stolen_size > 0) {
486 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
487 stolen_size / KB(1), local ? "local" : "stolen");
489 dev_info(&intel_private.bridge_dev->dev,
490 "no pre-allocated video memory detected\n");
497 static void i965_adjust_pgetbl_size(unsigned int size_flag)
499 u32 pgetbl_ctl, pgetbl_ctl2;
501 /* ensure that ppgtt is disabled */
502 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
503 pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
504 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
506 /* write the new ggtt size */
507 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
508 pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
509 pgetbl_ctl |= size_flag;
510 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
513 static unsigned int i965_gtt_total_entries(void)
519 pci_read_config_word(intel_private.bridge_dev,
520 I830_GMCH_CTRL, &gmch_ctl);
522 if (INTEL_GTT_GEN == 5) {
523 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
524 case G4x_GMCH_SIZE_1M:
525 case G4x_GMCH_SIZE_VT_1M:
526 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
528 case G4x_GMCH_SIZE_VT_1_5M:
529 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
531 case G4x_GMCH_SIZE_2M:
532 case G4x_GMCH_SIZE_VT_2M:
533 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
538 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
540 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
541 case I965_PGETBL_SIZE_128KB:
544 case I965_PGETBL_SIZE_256KB:
547 case I965_PGETBL_SIZE_512KB:
550 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
551 case I965_PGETBL_SIZE_1MB:
554 case I965_PGETBL_SIZE_2MB:
557 case I965_PGETBL_SIZE_1_5MB:
558 size = KB(1024 + 512);
561 dev_info(&intel_private.pcidev->dev,
562 "unknown page table size, assuming 512KB\n");
569 static unsigned int intel_gtt_total_entries(void)
573 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
574 return i965_gtt_total_entries();
575 else if (INTEL_GTT_GEN == 6) {
578 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
579 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
581 case SNB_GTT_SIZE_0M:
582 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
585 case SNB_GTT_SIZE_1M:
588 case SNB_GTT_SIZE_2M:
594 /* On previous hardware, the GTT size was just what was
595 * required to map the aperture.
597 return intel_private.base.gtt_mappable_entries;
601 static unsigned int intel_gtt_mappable_entries(void)
603 unsigned int aperture_size;
605 if (INTEL_GTT_GEN == 1) {
608 pci_read_config_dword(intel_private.bridge_dev,
609 I810_SMRAM_MISCC, &smram_miscc);
611 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
612 == I810_GFX_MEM_WIN_32M)
613 aperture_size = MB(32);
615 aperture_size = MB(64);
616 } else if (INTEL_GTT_GEN == 2) {
619 pci_read_config_word(intel_private.bridge_dev,
620 I830_GMCH_CTRL, &gmch_ctrl);
622 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
623 aperture_size = MB(64);
625 aperture_size = MB(128);
627 /* 9xx supports large sizes, just look at the length */
628 aperture_size = pci_resource_len(intel_private.pcidev, 2);
631 return aperture_size >> PAGE_SHIFT;
634 static void intel_gtt_teardown_scratch_page(void)
636 set_pages_wb(intel_private.scratch_page, 1);
637 pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma,
638 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
639 put_page(intel_private.scratch_page);
640 __free_page(intel_private.scratch_page);
643 static void intel_gtt_cleanup(void)
645 intel_private.driver->cleanup();
647 iounmap(intel_private.gtt);
648 iounmap(intel_private.registers);
650 intel_gtt_teardown_scratch_page();
653 static int intel_gtt_init(void)
658 ret = intel_private.driver->setup();
662 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
663 intel_private.base.gtt_total_entries = intel_gtt_total_entries();
665 /* save the PGETBL reg for resume */
666 intel_private.PGETBL_save =
667 readl(intel_private.registers+I810_PGETBL_CTL)
668 & ~I810_PGETBL_ENABLED;
669 /* we only ever restore the register when enabling the PGTBL... */
671 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
673 dev_info(&intel_private.bridge_dev->dev,
674 "detected gtt size: %dK total, %dK mappable\n",
675 intel_private.base.gtt_total_entries * 4,
676 intel_private.base.gtt_mappable_entries * 4);
678 gtt_map_size = intel_private.base.gtt_total_entries * 4;
680 intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
682 if (!intel_private.gtt) {
683 intel_private.driver->cleanup();
684 iounmap(intel_private.registers);
688 global_cache_flush(); /* FIXME: ? */
690 intel_private.base.stolen_size = intel_gtt_stolen_size();
692 intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
694 ret = intel_gtt_setup_scratch_page();
703 static int intel_fake_agp_fetch_size(void)
705 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
706 unsigned int aper_size;
709 aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
712 for (i = 0; i < num_sizes; i++) {
713 if (aper_size == intel_fake_agp_sizes[i].size) {
714 agp_bridge->current_size =
715 (void *) (intel_fake_agp_sizes + i);
723 static void i830_cleanup(void)
725 if (intel_private.i8xx_flush_page) {
726 kunmap(intel_private.i8xx_flush_page);
727 intel_private.i8xx_flush_page = NULL;
730 __free_page(intel_private.i8xx_page);
731 intel_private.i8xx_page = NULL;
734 static void intel_i830_setup_flush(void)
736 /* return if we've already set the flush mechanism up */
737 if (intel_private.i8xx_page)
740 intel_private.i8xx_page = alloc_page(GFP_KERNEL);
741 if (!intel_private.i8xx_page)
744 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
745 if (!intel_private.i8xx_flush_page)
749 /* The chipset_flush interface needs to get data that has already been
750 * flushed out of the CPU all the way out to main memory, because the GPU
751 * doesn't snoop those buffers.
753 * The 8xx series doesn't have the same lovely interface for flushing the
754 * chipset write buffers that the later chips do. According to the 865
755 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
756 * that buffer out, we just fill 1KB and clflush it out, on the assumption
757 * that it'll push whatever was in there out. It appears to work.
759 static void i830_chipset_flush(void)
761 unsigned int *pg = intel_private.i8xx_flush_page;
766 clflush_cache_range(pg, 1024);
767 else if (wbinvd_on_all_cpus() != 0)
768 printk(KERN_ERR "Timed out waiting for cache flush.\n");
771 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
774 u32 pte_flags = I810_PTE_VALID;
776 if (flags == AGP_USER_CACHED_MEMORY)
777 pte_flags |= I830_PTE_SYSTEM_CACHED;
779 writel(addr | pte_flags, intel_private.gtt + entry);
782 static bool intel_enable_gtt(void)
787 if (INTEL_GTT_GEN <= 2)
788 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
791 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
794 intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
796 if (INTEL_GTT_GEN >= 6)
799 if (INTEL_GTT_GEN == 2) {
802 pci_read_config_word(intel_private.bridge_dev,
803 I830_GMCH_CTRL, &gmch_ctrl);
804 gmch_ctrl |= I830_GMCH_ENABLED;
805 pci_write_config_word(intel_private.bridge_dev,
806 I830_GMCH_CTRL, gmch_ctrl);
808 pci_read_config_word(intel_private.bridge_dev,
809 I830_GMCH_CTRL, &gmch_ctrl);
810 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
811 dev_err(&intel_private.pcidev->dev,
812 "failed to enable the GTT: GMCH_CTRL=%x\n",
818 /* On the resume path we may be adjusting the PGTBL value, so
819 * be paranoid and flush all chipset write buffers...
821 if (INTEL_GTT_GEN >= 3)
822 writel(0, intel_private.registers+GFX_FLSH_CNTL);
824 reg = intel_private.registers+I810_PGETBL_CTL;
825 writel(intel_private.PGETBL_save, reg);
826 if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
827 dev_err(&intel_private.pcidev->dev,
828 "failed to enable the GTT: PGETBL=%x [expected %x]\n",
829 readl(reg), intel_private.PGETBL_save);
833 if (INTEL_GTT_GEN >= 3)
834 writel(0, intel_private.registers+GFX_FLSH_CNTL);
839 static int i830_setup(void)
843 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr);
844 reg_addr &= 0xfff80000;
846 intel_private.registers = ioremap(reg_addr, KB(64));
847 if (!intel_private.registers)
850 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
852 intel_i830_setup_flush();
857 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
859 agp_bridge->gatt_table_real = NULL;
860 agp_bridge->gatt_table = NULL;
861 agp_bridge->gatt_bus_addr = 0;
866 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
871 static int intel_fake_agp_configure(void)
873 if (!intel_enable_gtt())
876 intel_private.clear_fake_agp = true;
877 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
882 static bool i830_check_flags(unsigned int flags)
886 case AGP_PHYS_MEMORY:
887 case AGP_USER_CACHED_MEMORY:
888 case AGP_USER_MEMORY:
895 void intel_gtt_insert_sg_entries(struct scatterlist *sg_list,
897 unsigned int pg_start,
900 struct scatterlist *sg;
906 /* sg may merge pages, but we have to separate
907 * per-page addr for GTT */
908 for_each_sg(sg_list, sg, sg_len, i) {
909 len = sg_dma_len(sg) >> PAGE_SHIFT;
910 for (m = 0; m < len; m++) {
911 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
912 intel_private.driver->write_entry(addr,
917 readl(intel_private.gtt+j-1);
919 EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
921 void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries,
922 struct page **pages, unsigned int flags)
926 for (i = 0, j = first_entry; i < num_entries; i++, j++) {
927 dma_addr_t addr = page_to_phys(pages[i]);
928 intel_private.driver->write_entry(addr,
931 readl(intel_private.gtt+j-1);
933 EXPORT_SYMBOL(intel_gtt_insert_pages);
935 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
936 off_t pg_start, int type)
940 if (intel_private.clear_fake_agp) {
941 int start = intel_private.base.stolen_size / PAGE_SIZE;
942 int end = intel_private.base.gtt_mappable_entries;
943 intel_gtt_clear_range(start, end - start);
944 intel_private.clear_fake_agp = false;
947 if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
948 return i810_insert_dcache_entries(mem, pg_start, type);
950 if (mem->page_count == 0)
953 if (pg_start + mem->page_count > intel_private.base.gtt_total_entries)
956 if (type != mem->type)
959 if (!intel_private.driver->check_flags(type))
962 if (!mem->is_flushed)
963 global_cache_flush();
965 if (intel_private.base.needs_dmar) {
966 ret = intel_gtt_map_memory(mem->pages, mem->page_count,
967 &mem->sg_list, &mem->num_sg);
971 intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg,
974 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
980 mem->is_flushed = true;
984 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
988 for (i = first_entry; i < (first_entry + num_entries); i++) {
989 intel_private.driver->write_entry(intel_private.scratch_page_dma,
992 readl(intel_private.gtt+i-1);
994 EXPORT_SYMBOL(intel_gtt_clear_range);
996 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
997 off_t pg_start, int type)
999 if (mem->page_count == 0)
1002 intel_gtt_clear_range(pg_start, mem->page_count);
1004 if (intel_private.base.needs_dmar) {
1005 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
1006 mem->sg_list = NULL;
1013 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1016 struct agp_memory *new;
1018 if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
1019 if (pg_count != intel_private.num_dcache_entries)
1022 new = agp_create_memory(1);
1026 new->type = AGP_DCACHE_MEMORY;
1027 new->page_count = pg_count;
1028 new->num_scratch_pages = 0;
1029 agp_free_page_array(new);
1032 if (type == AGP_PHYS_MEMORY)
1033 return alloc_agpphysmem_i8xx(pg_count, type);
1034 /* always return NULL for other allocation types for now */
1038 static int intel_alloc_chipset_flush_resource(void)
1041 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1042 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1043 pcibios_align_resource, intel_private.bridge_dev);
1048 static void intel_i915_setup_chipset_flush(void)
1053 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1054 if (!(temp & 0x1)) {
1055 intel_alloc_chipset_flush_resource();
1056 intel_private.resource_valid = 1;
1057 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1061 intel_private.resource_valid = 1;
1062 intel_private.ifp_resource.start = temp;
1063 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1064 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1065 /* some BIOSes reserve this area in a pnp some don't */
1067 intel_private.resource_valid = 0;
1071 static void intel_i965_g33_setup_chipset_flush(void)
1073 u32 temp_hi, temp_lo;
1076 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1077 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1079 if (!(temp_lo & 0x1)) {
1081 intel_alloc_chipset_flush_resource();
1083 intel_private.resource_valid = 1;
1084 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1085 upper_32_bits(intel_private.ifp_resource.start));
1086 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1091 l64 = ((u64)temp_hi << 32) | temp_lo;
1093 intel_private.resource_valid = 1;
1094 intel_private.ifp_resource.start = l64;
1095 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1096 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1097 /* some BIOSes reserve this area in a pnp some don't */
1099 intel_private.resource_valid = 0;
1103 static void intel_i9xx_setup_flush(void)
1105 /* return if already configured */
1106 if (intel_private.ifp_resource.start)
1109 if (INTEL_GTT_GEN == 6)
1112 /* setup a resource for this object */
1113 intel_private.ifp_resource.name = "Intel Flush Page";
1114 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1116 /* Setup chipset flush for 915 */
1117 if (IS_G33 || INTEL_GTT_GEN >= 4) {
1118 intel_i965_g33_setup_chipset_flush();
1120 intel_i915_setup_chipset_flush();
1123 if (intel_private.ifp_resource.start)
1124 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1125 if (!intel_private.i9xx_flush_page)
1126 dev_err(&intel_private.pcidev->dev,
1127 "can't ioremap flush page - no chipset flushing\n");
1130 static void i9xx_cleanup(void)
1132 if (intel_private.i9xx_flush_page)
1133 iounmap(intel_private.i9xx_flush_page);
1134 if (intel_private.resource_valid)
1135 release_resource(&intel_private.ifp_resource);
1136 intel_private.ifp_resource.start = 0;
1137 intel_private.resource_valid = 0;
1140 static void i9xx_chipset_flush(void)
1142 if (intel_private.i9xx_flush_page)
1143 writel(1, intel_private.i9xx_flush_page);
1146 static void i965_write_entry(dma_addr_t addr,
1152 pte_flags = I810_PTE_VALID;
1153 if (flags == AGP_USER_CACHED_MEMORY)
1154 pte_flags |= I830_PTE_SYSTEM_CACHED;
1156 /* Shift high bits down */
1157 addr |= (addr >> 28) & 0xf0;
1158 writel(addr | pte_flags, intel_private.gtt + entry);
1161 static bool gen6_check_flags(unsigned int flags)
1166 static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
1169 unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1170 unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
1173 if (type_mask == AGP_USER_MEMORY)
1174 pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
1175 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
1176 pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
1178 pte_flags |= GEN6_PTE_GFDT;
1179 } else { /* set 'normal'/'cached' to LLC by default */
1180 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
1182 pte_flags |= GEN6_PTE_GFDT;
1185 /* gen6 has bit11-4 for physical addr bit39-32 */
1186 addr |= (addr >> 28) & 0xff0;
1187 writel(addr | pte_flags, intel_private.gtt + entry);
1190 static void gen6_cleanup(void)
1194 static int i9xx_setup(void)
1198 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr);
1200 reg_addr &= 0xfff80000;
1202 intel_private.registers = ioremap(reg_addr, 128 * 4096);
1203 if (!intel_private.registers)
1206 if (INTEL_GTT_GEN == 3) {
1209 pci_read_config_dword(intel_private.pcidev,
1210 I915_PTEADDR, >t_addr);
1211 intel_private.gtt_bus_addr = gtt_addr;
1215 switch (INTEL_GTT_GEN) {
1222 gtt_offset = KB(512);
1225 intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1228 intel_i9xx_setup_flush();
1233 static const struct agp_bridge_driver intel_fake_agp_driver = {
1234 .owner = THIS_MODULE,
1235 .size_type = FIXED_APER_SIZE,
1236 .aperture_sizes = intel_fake_agp_sizes,
1237 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1238 .configure = intel_fake_agp_configure,
1239 .fetch_size = intel_fake_agp_fetch_size,
1240 .cleanup = intel_gtt_cleanup,
1241 .agp_enable = intel_fake_agp_enable,
1242 .cache_flush = global_cache_flush,
1243 .create_gatt_table = intel_fake_agp_create_gatt_table,
1244 .free_gatt_table = intel_fake_agp_free_gatt_table,
1245 .insert_memory = intel_fake_agp_insert_entries,
1246 .remove_memory = intel_fake_agp_remove_entries,
1247 .alloc_by_type = intel_fake_agp_alloc_by_type,
1248 .free_by_type = intel_i810_free_by_type,
1249 .agp_alloc_page = agp_generic_alloc_page,
1250 .agp_alloc_pages = agp_generic_alloc_pages,
1251 .agp_destroy_page = agp_generic_destroy_page,
1252 .agp_destroy_pages = agp_generic_destroy_pages,
1255 static const struct intel_gtt_driver i81x_gtt_driver = {
1257 .has_pgtbl_enable = 1,
1258 .dma_mask_size = 32,
1259 .setup = i810_setup,
1260 .cleanup = i810_cleanup,
1261 .check_flags = i830_check_flags,
1262 .write_entry = i810_write_entry,
1264 static const struct intel_gtt_driver i8xx_gtt_driver = {
1266 .has_pgtbl_enable = 1,
1267 .setup = i830_setup,
1268 .cleanup = i830_cleanup,
1269 .write_entry = i830_write_entry,
1270 .dma_mask_size = 32,
1271 .check_flags = i830_check_flags,
1272 .chipset_flush = i830_chipset_flush,
1274 static const struct intel_gtt_driver i915_gtt_driver = {
1276 .has_pgtbl_enable = 1,
1277 .setup = i9xx_setup,
1278 .cleanup = i9xx_cleanup,
1279 /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1280 .write_entry = i830_write_entry,
1281 .dma_mask_size = 32,
1282 .check_flags = i830_check_flags,
1283 .chipset_flush = i9xx_chipset_flush,
1285 static const struct intel_gtt_driver g33_gtt_driver = {
1288 .setup = i9xx_setup,
1289 .cleanup = i9xx_cleanup,
1290 .write_entry = i965_write_entry,
1291 .dma_mask_size = 36,
1292 .check_flags = i830_check_flags,
1293 .chipset_flush = i9xx_chipset_flush,
1295 static const struct intel_gtt_driver pineview_gtt_driver = {
1297 .is_pineview = 1, .is_g33 = 1,
1298 .setup = i9xx_setup,
1299 .cleanup = i9xx_cleanup,
1300 .write_entry = i965_write_entry,
1301 .dma_mask_size = 36,
1302 .check_flags = i830_check_flags,
1303 .chipset_flush = i9xx_chipset_flush,
1305 static const struct intel_gtt_driver i965_gtt_driver = {
1307 .has_pgtbl_enable = 1,
1308 .setup = i9xx_setup,
1309 .cleanup = i9xx_cleanup,
1310 .write_entry = i965_write_entry,
1311 .dma_mask_size = 36,
1312 .check_flags = i830_check_flags,
1313 .chipset_flush = i9xx_chipset_flush,
1315 static const struct intel_gtt_driver g4x_gtt_driver = {
1317 .setup = i9xx_setup,
1318 .cleanup = i9xx_cleanup,
1319 .write_entry = i965_write_entry,
1320 .dma_mask_size = 36,
1321 .check_flags = i830_check_flags,
1322 .chipset_flush = i9xx_chipset_flush,
1324 static const struct intel_gtt_driver ironlake_gtt_driver = {
1327 .setup = i9xx_setup,
1328 .cleanup = i9xx_cleanup,
1329 .write_entry = i965_write_entry,
1330 .dma_mask_size = 36,
1331 .check_flags = i830_check_flags,
1332 .chipset_flush = i9xx_chipset_flush,
1334 static const struct intel_gtt_driver sandybridge_gtt_driver = {
1336 .setup = i9xx_setup,
1337 .cleanup = gen6_cleanup,
1338 .write_entry = gen6_write_entry,
1339 .dma_mask_size = 40,
1340 .check_flags = gen6_check_flags,
1341 .chipset_flush = i9xx_chipset_flush,
1344 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1345 * driver and gmch_driver must be non-null, and find_gmch will determine
1346 * which one should be used if a gmch_chip_id is present.
1348 static const struct intel_gtt_driver_description {
1349 unsigned int gmch_chip_id;
1351 const struct intel_gtt_driver *gtt_driver;
1352 } intel_gtt_chipsets[] = {
1353 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1355 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1357 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1359 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1361 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1363 { PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
1365 { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1367 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1369 { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1371 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1373 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1375 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1377 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1379 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1381 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1383 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1385 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1387 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1389 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1391 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1393 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1395 { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1397 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1399 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1401 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1402 &pineview_gtt_driver },
1403 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1404 &pineview_gtt_driver },
1405 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1407 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1409 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1411 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1413 { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1415 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1417 { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1419 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1420 "HD Graphics", &ironlake_gtt_driver },
1421 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1422 "HD Graphics", &ironlake_gtt_driver },
1423 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1424 "Sandybridge", &sandybridge_gtt_driver },
1425 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1426 "Sandybridge", &sandybridge_gtt_driver },
1427 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1428 "Sandybridge", &sandybridge_gtt_driver },
1429 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1430 "Sandybridge", &sandybridge_gtt_driver },
1431 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1432 "Sandybridge", &sandybridge_gtt_driver },
1433 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1434 "Sandybridge", &sandybridge_gtt_driver },
1435 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1436 "Sandybridge", &sandybridge_gtt_driver },
1440 static int find_gmch(u16 device)
1442 struct pci_dev *gmch_device;
1444 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1445 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1446 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1447 device, gmch_device);
1453 intel_private.pcidev = gmch_device;
1457 int intel_gmch_probe(struct pci_dev *pdev,
1458 struct agp_bridge_data *bridge)
1461 intel_private.driver = NULL;
1463 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1464 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1465 intel_private.driver =
1466 intel_gtt_chipsets[i].gtt_driver;
1471 if (!intel_private.driver)
1474 bridge->driver = &intel_fake_agp_driver;
1475 bridge->dev_private_data = &intel_private;
1478 intel_private.bridge_dev = pci_dev_get(pdev);
1480 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1482 mask = intel_private.driver->dma_mask_size;
1483 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1484 dev_err(&intel_private.pcidev->dev,
1485 "set gfx device dma mask %d-bit failed!\n", mask);
1487 pci_set_consistent_dma_mask(intel_private.pcidev,
1488 DMA_BIT_MASK(mask));
1490 /*if (bridge->driver == &intel_810_driver)
1493 if (intel_gtt_init() != 0)
1498 EXPORT_SYMBOL(intel_gmch_probe);
1500 const struct intel_gtt *intel_gtt_get(void)
1502 return &intel_private.base;
1504 EXPORT_SYMBOL(intel_gtt_get);
1506 void intel_gtt_chipset_flush(void)
1508 if (intel_private.driver->chipset_flush)
1509 intel_private.driver->chipset_flush();
1511 EXPORT_SYMBOL(intel_gtt_chipset_flush);
1513 void intel_gmch_remove(struct pci_dev *pdev)
1515 if (intel_private.pcidev)
1516 pci_dev_put(intel_private.pcidev);
1517 if (intel_private.bridge_dev)
1518 pci_dev_put(intel_private.bridge_dev);
1520 EXPORT_SYMBOL(intel_gmch_remove);
1522 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1523 MODULE_LICENSE("GPL and additional rights");