drivers/char/agp/intel-gtt.c

   1 /*
   2  * Intel GTT (Graphics Translation Table) routines
   3  *
   4  * Caveat: This driver implements the linux agp interface, but this is far from
   5  * a agp driver! GTT support ended up here for purely historical reasons: The
   6  * old userspace intel graphics drivers needed an interface to map memory into
   7  * the GTT. And the drm provides a default interface for graphic devices sitting
   8  * on an agp port. So it made sense to fake the GTT support as an agp port to
   9  * avoid having to create a new api.
  10  *
  11  * With gem this does not make much sense anymore, just needlessly complicates
  12  * the code. But as long as the old graphics stack is still support, it's stuck
  13  * here.
  14  *
  15  * /fairy-tale-mode off
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/pci.h>
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/pagemap.h>
  23 #include <linux/agp_backend.h>
  24 #include <linux/delay.h>
  25 #include <asm/smp.h>
  26 #include "agp.h"
  27 #include "intel-agp.h"
  28 #include <drm/intel-gtt.h>
  29
  30 /*
  31  * If we have Intel graphics, we're not going to have anything other than
  32  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
  33  * on the Intel IOMMU support (CONFIG_INTEL_IOMMU).
  34  * Only newer chipsets need to bother with this, of course.
  35  */
  36 #ifdef CONFIG_INTEL_IOMMU
  37 #define USE_PCI_DMA_API 1
  38 #else
  39 #define USE_PCI_DMA_API 0
  40 #endif
  41
  42 struct intel_gtt_driver {
  43         unsigned int gen : 8;
  44         unsigned int is_g33 : 1;
  45         unsigned int is_pineview : 1;
  46         unsigned int is_ironlake : 1;
  47         unsigned int has_pgtbl_enable : 1;
  48         unsigned int dma_mask_size : 8;
  49         /* Chipset specific GTT setup */
  50         int (*setup)(void);
  51         /* This should undo anything done in ->setup() save the unmapping
  52          * of the mmio register file, that's done in the generic code. */
  53         void (*cleanup)(void);
  54         void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
  55         /* Flags is a more or less chipset specific opaque value.
  56          * For chipsets that need to support old ums (non-gem) code, this
  57          * needs to be identical to the various supported agp memory types! */
  58         bool (*check_flags)(unsigned int flags);
  59         void (*chipset_flush)(void);
  60 };
  61
  62 static struct _intel_private {
  63         struct intel_gtt base;
  64         const struct intel_gtt_driver *driver;
  65         struct pci_dev *pcidev; /* device one */
  66         struct pci_dev *bridge_dev;
  67         u8 __iomem *registers;
  68         phys_addr_t gtt_bus_addr;
  69         u32 PGETBL_save;
  70         u32 __iomem *gtt;               /* I915G */
  71         bool clear_fake_agp; /* on first access via agp, fill with scratch */
  72         int num_dcache_entries;
  73         void __iomem *i9xx_flush_page;
  74         char *i81x_gtt_table;
  75         struct resource ifp_resource;
  76         int resource_valid;
  77         struct page *scratch_page;
  78         int refcount;
  79 } intel_private;
  80
  81 #define INTEL_GTT_GEN   intel_private.driver->gen
  82 #define IS_G33          intel_private.driver->is_g33
  83 #define IS_PINEVIEW     intel_private.driver->is_pineview
  84 #define IS_IRONLAKE     intel_private.driver->is_ironlake
  85 #define HAS_PGTBL_EN    intel_private.driver->has_pgtbl_enable
  86
  87 static int intel_gtt_map_memory(struct page **pages,
  88                                 unsigned int num_entries,
  89                                 struct sg_table *st)
  90 {
  91         struct scatterlist *sg;
  92         int i;
  93
  94         DBG("try mapping %lu pages\n", (unsigned long)num_entries);
  95
  96         if (sg_alloc_table(st, num_entries, GFP_KERNEL))
  97                 goto err;
  98
  99         for_each_sg(st->sgl, sg, num_entries, i)
 100                 sg_set_page(sg, pages[i], PAGE_SIZE, 0);
 101
 102         if (!pci_map_sg(intel_private.pcidev,
 103                         st->sgl, st->nents, PCI_DMA_BIDIRECTIONAL))
 104                 goto err;
 105
 106         return 0;
 107
 108 err:
 109         sg_free_table(st);
 110         return -ENOMEM;
 111 }
 112
 113 static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
 114 {
 115         struct sg_table st;
 116         DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
 117
 118         pci_unmap_sg(intel_private.pcidev, sg_list,
 119                      num_sg, PCI_DMA_BIDIRECTIONAL);
 120
 121         st.sgl = sg_list;
 122         st.orig_nents = st.nents = num_sg;
 123
 124         sg_free_table(&st);
 125 }
 126
 127 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 128 {
 129         return;
 130 }
 131
 132 /* Exists to support ARGB cursors */
 133 static struct page *i8xx_alloc_pages(void)
 134 {
 135         struct page *page;
 136
 137         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 138         if (page == NULL)
 139                 return NULL;
 140
 141         if (set_pages_uc(page, 4) < 0) {
 142                 set_pages_wb(page, 4);
 143                 __free_pages(page, 2);
 144                 return NULL;
 145         }
 146         get_page(page);
 147         atomic_inc(&agp_bridge->current_memory_agp);
 148         return page;
 149 }
 150
 151 static void i8xx_destroy_pages(struct page *page)
 152 {
 153         if (page == NULL)
 154                 return;
 155
 156         set_pages_wb(page, 4);
 157         put_page(page);
 158         __free_pages(page, 2);
 159         atomic_dec(&agp_bridge->current_memory_agp);
 160 }
 161
 162 #define I810_GTT_ORDER 4
 163 static int i810_setup(void)
 164 {
 165         u32 reg_addr;
 166         char *gtt_table;
 167
 168         /* i81x does not preallocate the gtt. It's always 64kb in size. */
 169         gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
 170         if (gtt_table == NULL)
 171                 return -ENOMEM;
 172         intel_private.i81x_gtt_table = gtt_table;
 173
 174         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
 175         reg_addr &= 0xfff80000;
 176
 177         intel_private.registers = ioremap(reg_addr, KB(64));
 178         if (!intel_private.registers)
 179                 return -ENOMEM;
 180
 181         writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
 182                intel_private.registers+I810_PGETBL_CTL);
 183
 184         intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
 185
 186         if ((readl(intel_private.registers+I810_DRAM_CTL)
 187                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 188                 dev_info(&intel_private.pcidev->dev,
 189                          "detected 4MB dedicated video ram\n");
 190                 intel_private.num_dcache_entries = 1024;
 191         }
 192
 193         return 0;
 194 }
 195
 196 static void i810_cleanup(void)
 197 {
 198         writel(0, intel_private.registers+I810_PGETBL_CTL);
 199         free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
 200 }
 201
 202 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
 203                                       int type)
 204 {
 205         int i;
 206
 207         if ((pg_start + mem->page_count)
 208                         > intel_private.num_dcache_entries)
 209                 return -EINVAL;
 210
 211         if (!mem->is_flushed)
 212                 global_cache_flush();
 213
 214         for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 215                 dma_addr_t addr = i << PAGE_SHIFT;
 216                 intel_private.driver->write_entry(addr,
 217                                                   i, type);
 218         }
 219         readl(intel_private.gtt+i-1);
 220
 221         return 0;
 222 }
 223
 224 /*
 225  * The i810/i830 requires a physical address to program its mouse
 226  * pointer into hardware.
 227  * However the Xserver still writes to it through the agp aperture.
 228  */
 229 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 230 {
 231         struct agp_memory *new;
 232         struct page *page;
 233
 234         switch (pg_count) {
 235         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 236                 break;
 237         case 4:
 238                 /* kludge to get 4 physical pages for ARGB cursor */
 239                 page = i8xx_alloc_pages();
 240                 break;
 241         default:
 242                 return NULL;
 243         }
 244
 245         if (page == NULL)
 246                 return NULL;
 247
 248         new = agp_create_memory(pg_count);
 249         if (new == NULL)
 250                 return NULL;
 251
 252         new->pages[0] = page;
 253         if (pg_count == 4) {
 254                 /* kludge to get 4 physical pages for ARGB cursor */
 255                 new->pages[1] = new->pages[0] + 1;
 256                 new->pages[2] = new->pages[1] + 1;
 257                 new->pages[3] = new->pages[2] + 1;
 258         }
 259         new->page_count = pg_count;
 260         new->num_scratch_pages = pg_count;
 261         new->type = AGP_PHYS_MEMORY;
 262         new->physical = page_to_phys(new->pages[0]);
 263         return new;
 264 }
 265
 266 static void intel_i810_free_by_type(struct agp_memory *curr)
 267 {
 268         agp_free_key(curr->key);
 269         if (curr->type == AGP_PHYS_MEMORY) {
 270                 if (curr->page_count == 4)
 271                         i8xx_destroy_pages(curr->pages[0]);
 272                 else {
 273                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 274                                                              AGP_PAGE_DESTROY_UNMAP);
 275                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 276                                                              AGP_PAGE_DESTROY_FREE);
 277                 }
 278                 agp_free_page_array(curr);
 279         }
 280         kfree(curr);
 281 }
 282
 283 static int intel_gtt_setup_scratch_page(void)
 284 {
 285         struct page *page;
 286         dma_addr_t dma_addr;
 287
 288         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 289         if (page == NULL)
 290                 return -ENOMEM;
 291         get_page(page);
 292         set_pages_uc(page, 1);
 293
 294         if (intel_private.base.needs_dmar) {
 295                 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
 296                                     PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 297                 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
 298                         return -EINVAL;
 299
 300                 intel_private.base.scratch_page_dma = dma_addr;
 301         } else
 302                 intel_private.base.scratch_page_dma = page_to_phys(page);
 303
 304         intel_private.scratch_page = page;
 305
 306         return 0;
 307 }
 308
 309 static void i810_write_entry(dma_addr_t addr, unsigned int entry,
 310                              unsigned int flags)
 311 {
 312         u32 pte_flags = I810_PTE_VALID;
 313
 314         switch (flags) {
 315         case AGP_DCACHE_MEMORY:
 316                 pte_flags |= I810_PTE_LOCAL;
 317                 break;
 318         case AGP_USER_CACHED_MEMORY:
 319                 pte_flags |= I830_PTE_SYSTEM_CACHED;
 320                 break;
 321         }
 322
 323         writel(addr | pte_flags, intel_private.gtt + entry);
 324 }
 325
 326 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
 327         {32, 8192, 3},
 328         {64, 16384, 4},
 329         {128, 32768, 5},
 330         {256, 65536, 6},
 331         {512, 131072, 7},
 332 };
 333
 334 static unsigned int intel_gtt_stolen_size(void)
 335 {
 336         u16 gmch_ctrl;
 337         u8 rdct;
 338         int local = 0;
 339         static const int ddt[4] = { 0, 16, 32, 64 };
 340         unsigned int stolen_size = 0;
 341
 342         if (INTEL_GTT_GEN == 1)
 343                 return 0; /* no stolen mem on i81x */
 344
 345         pci_read_config_word(intel_private.bridge_dev,
 346                              I830_GMCH_CTRL, &gmch_ctrl);
 347
 348         if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 349             intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 350                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 351                 case I830_GMCH_GMS_STOLEN_512:
 352                         stolen_size = KB(512);
 353                         break;
 354                 case I830_GMCH_GMS_STOLEN_1024:
 355                         stolen_size = MB(1);
 356                         break;
 357                 case I830_GMCH_GMS_STOLEN_8192:
 358                         stolen_size = MB(8);
 359                         break;
 360                 case I830_GMCH_GMS_LOCAL:
 361                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 362                         stolen_size = (I830_RDRAM_ND(rdct) + 1) *
 363                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 364                         local = 1;
 365                         break;
 366                 default:
 367                         stolen_size = 0;
 368                         break;
 369                 }
 370         } else {
 371                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 372                 case I855_GMCH_GMS_STOLEN_1M:
 373                         stolen_size = MB(1);
 374                         break;
 375                 case I855_GMCH_GMS_STOLEN_4M:
 376                         stolen_size = MB(4);
 377                         break;
 378                 case I855_GMCH_GMS_STOLEN_8M:
 379                         stolen_size = MB(8);
 380                         break;
 381                 case I855_GMCH_GMS_STOLEN_16M:
 382                         stolen_size = MB(16);
 383                         break;
 384                 case I855_GMCH_GMS_STOLEN_32M:
 385                         stolen_size = MB(32);
 386                         break;
 387                 case I915_GMCH_GMS_STOLEN_48M:
 388                         stolen_size = MB(48);
 389                         break;
 390                 case I915_GMCH_GMS_STOLEN_64M:
 391                         stolen_size = MB(64);
 392                         break;
 393                 case G33_GMCH_GMS_STOLEN_128M:
 394                         stolen_size = MB(128);
 395                         break;
 396                 case G33_GMCH_GMS_STOLEN_256M:
 397                         stolen_size = MB(256);
 398                         break;
 399                 case INTEL_GMCH_GMS_STOLEN_96M:
 400                         stolen_size = MB(96);
 401                         break;
 402                 case INTEL_GMCH_GMS_STOLEN_160M:
 403                         stolen_size = MB(160);
 404                         break;
 405                 case INTEL_GMCH_GMS_STOLEN_224M:
 406                         stolen_size = MB(224);
 407                         break;
 408                 case INTEL_GMCH_GMS_STOLEN_352M:
 409                         stolen_size = MB(352);
 410                         break;
 411                 default:
 412                         stolen_size = 0;
 413                         break;
 414                 }
 415         }
 416
 417         if (stolen_size > 0) {
 418                 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
 419                        stolen_size / KB(1), local ? "local" : "stolen");
 420         } else {
 421                 dev_info(&intel_private.bridge_dev->dev,
 422                        "no pre-allocated video memory detected\n");
 423                 stolen_size = 0;
 424         }
 425
 426         return stolen_size;
 427 }
 428
 429 static void i965_adjust_pgetbl_size(unsigned int size_flag)
 430 {
 431         u32 pgetbl_ctl, pgetbl_ctl2;
 432
 433         /* ensure that ppgtt is disabled */
 434         pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
 435         pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
 436         writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
 437
 438         /* write the new ggtt size */
 439         pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 440         pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
 441         pgetbl_ctl |= size_flag;
 442         writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
 443 }
 444
 445 static unsigned int i965_gtt_total_entries(void)
 446 {
 447         int size;
 448         u32 pgetbl_ctl;
 449         u16 gmch_ctl;
 450
 451         pci_read_config_word(intel_private.bridge_dev,
 452                              I830_GMCH_CTRL, &gmch_ctl);
 453
 454         if (INTEL_GTT_GEN == 5) {
 455                 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
 456                 case G4x_GMCH_SIZE_1M:
 457                 case G4x_GMCH_SIZE_VT_1M:
 458                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
 459                         break;
 460                 case G4x_GMCH_SIZE_VT_1_5M:
 461                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
 462                         break;
 463                 case G4x_GMCH_SIZE_2M:
 464                 case G4x_GMCH_SIZE_VT_2M:
 465                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
 466                         break;
 467                 }
 468         }
 469
 470         pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 471
 472         switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 473         case I965_PGETBL_SIZE_128KB:
 474                 size = KB(128);
 475                 break;
 476         case I965_PGETBL_SIZE_256KB:
 477                 size = KB(256);
 478                 break;
 479         case I965_PGETBL_SIZE_512KB:
 480                 size = KB(512);
 481                 break;
 482         /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
 483         case I965_PGETBL_SIZE_1MB:
 484                 size = KB(1024);
 485                 break;
 486         case I965_PGETBL_SIZE_2MB:
 487                 size = KB(2048);
 488                 break;
 489         case I965_PGETBL_SIZE_1_5MB:
 490                 size = KB(1024 + 512);
 491                 break;
 492         default:
 493                 dev_info(&intel_private.pcidev->dev,
 494                          "unknown page table size, assuming 512KB\n");
 495                 size = KB(512);
 496         }
 497
 498         return size/4;
 499 }
 500
 501 static unsigned int intel_gtt_total_entries(void)
 502 {
 503         if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
 504                 return i965_gtt_total_entries();
 505         else {
 506                 /* On previous hardware, the GTT size was just what was
 507                  * required to map the aperture.
 508                  */
 509                 return intel_private.base.gtt_mappable_entries;
 510         }
 511 }
 512
 513 static unsigned int intel_gtt_mappable_entries(void)
 514 {
 515         unsigned int aperture_size;
 516
 517         if (INTEL_GTT_GEN == 1) {
 518                 u32 smram_miscc;
 519
 520                 pci_read_config_dword(intel_private.bridge_dev,
 521                                       I810_SMRAM_MISCC, &smram_miscc);
 522
 523                 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
 524                                 == I810_GFX_MEM_WIN_32M)
 525                         aperture_size = MB(32);
 526                 else
 527                         aperture_size = MB(64);
 528         } else if (INTEL_GTT_GEN == 2) {
 529                 u16 gmch_ctrl;
 530
 531                 pci_read_config_word(intel_private.bridge_dev,
 532                                      I830_GMCH_CTRL, &gmch_ctrl);
 533
 534                 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
 535                         aperture_size = MB(64);
 536                 else
 537                         aperture_size = MB(128);
 538         } else {
 539                 /* 9xx supports large sizes, just look at the length */
 540                 aperture_size = pci_resource_len(intel_private.pcidev, 2);
 541         }
 542
 543         return aperture_size >> PAGE_SHIFT;
 544 }
 545
 546 static void intel_gtt_teardown_scratch_page(void)
 547 {
 548         set_pages_wb(intel_private.scratch_page, 1);
 549         pci_unmap_page(intel_private.pcidev, intel_private.base.scratch_page_dma,
 550                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 551         put_page(intel_private.scratch_page);
 552         __free_page(intel_private.scratch_page);
 553 }
 554
 555 static void intel_gtt_cleanup(void)
 556 {
 557         intel_private.driver->cleanup();
 558
 559         iounmap(intel_private.gtt);
 560         iounmap(intel_private.registers);
 561
 562         intel_gtt_teardown_scratch_page();
 563 }
 564
 565 static int intel_gtt_init(void)
 566 {
 567         u32 gma_addr;
 568         u32 gtt_map_size;
 569         int ret;
 570
 571         ret = intel_private.driver->setup();
 572         if (ret != 0)
 573                 return ret;
 574
 575         intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
 576         intel_private.base.gtt_total_entries = intel_gtt_total_entries();
 577
 578         /* save the PGETBL reg for resume */
 579         intel_private.PGETBL_save =
 580                 readl(intel_private.registers+I810_PGETBL_CTL)
 581                         & ~I810_PGETBL_ENABLED;
 582         /* we only ever restore the register when enabling the PGTBL... */
 583         if (HAS_PGTBL_EN)
 584                 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
 585
 586         dev_info(&intel_private.bridge_dev->dev,
 587                         "detected gtt size: %dK total, %dK mappable\n",
 588                         intel_private.base.gtt_total_entries * 4,
 589                         intel_private.base.gtt_mappable_entries * 4);
 590
 591         gtt_map_size = intel_private.base.gtt_total_entries * 4;
 592
 593         intel_private.gtt = NULL;
 594         if (INTEL_GTT_GEN < 6 && INTEL_GTT_GEN > 2)
 595                 intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr,
 596                                                gtt_map_size);
 597         if (intel_private.gtt == NULL)
 598                 intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
 599                                             gtt_map_size);
 600         if (intel_private.gtt == NULL) {
 601                 intel_private.driver->cleanup();
 602                 iounmap(intel_private.registers);
 603                 return -ENOMEM;
 604         }
 605
 606         global_cache_flush();   /* FIXME: ? */
 607
 608         intel_private.base.stolen_size = intel_gtt_stolen_size();
 609
 610         intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
 611
 612         ret = intel_gtt_setup_scratch_page();
 613         if (ret != 0) {
 614                 intel_gtt_cleanup();
 615                 return ret;
 616         }
 617
 618         if (INTEL_GTT_GEN <= 2)
 619                 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
 620                                       &gma_addr);
 621         else
 622                 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
 623                                       &gma_addr);
 624
 625         intel_private.base.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
 626
 627         return 0;
 628 }
 629
 630 static int intel_fake_agp_fetch_size(void)
 631 {
 632         int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
 633         unsigned int aper_size;
 634         int i;
 635
 636         aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
 637                     / MB(1);
 638
 639         for (i = 0; i < num_sizes; i++) {
 640                 if (aper_size == intel_fake_agp_sizes[i].size) {
 641                         agp_bridge->current_size =
 642                                 (void *) (intel_fake_agp_sizes + i);
 643                         return aper_size;
 644                 }
 645         }
 646
 647         return 0;
 648 }
 649
 650 static void i830_cleanup(void)
 651 {
 652 }
 653
 654 /* The chipset_flush interface needs to get data that has already been
 655  * flushed out of the CPU all the way out to main memory, because the GPU
 656  * doesn't snoop those buffers.
 657  *
 658  * The 8xx series doesn't have the same lovely interface for flushing the
 659  * chipset write buffers that the later chips do. According to the 865
 660  * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
 661  * that buffer out, we just fill 1KB and clflush it out, on the assumption
 662  * that it'll push whatever was in there out.  It appears to work.
 663  */
 664 static void i830_chipset_flush(void)
 665 {
 666         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 667
 668         /* Forcibly evict everything from the CPU write buffers.
 669          * clflush appears to be insufficient.
 670          */
 671         wbinvd_on_all_cpus();
 672
 673         /* Now we've only seen documents for this magic bit on 855GM,
 674          * we hope it exists for the other gen2 chipsets...
 675          *
 676          * Also works as advertised on my 845G.
 677          */
 678         writel(readl(intel_private.registers+I830_HIC) | (1<<31),
 679                intel_private.registers+I830_HIC);
 680
 681         while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
 682                 if (time_after(jiffies, timeout))
 683                         break;
 684
 685                 udelay(50);
 686         }
 687 }
 688
 689 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
 690                              unsigned int flags)
 691 {
 692         u32 pte_flags = I810_PTE_VALID;
 693
 694         if (flags ==  AGP_USER_CACHED_MEMORY)
 695                 pte_flags |= I830_PTE_SYSTEM_CACHED;
 696
 697         writel(addr | pte_flags, intel_private.gtt + entry);
 698 }
 699
 700 bool intel_enable_gtt(void)
 701 {
 702         u8 __iomem *reg;
 703
 704         if (INTEL_GTT_GEN == 2) {
 705                 u16 gmch_ctrl;
 706
 707                 pci_read_config_word(intel_private.bridge_dev,
 708                                      I830_GMCH_CTRL, &gmch_ctrl);
 709                 gmch_ctrl |= I830_GMCH_ENABLED;
 710                 pci_write_config_word(intel_private.bridge_dev,
 711                                       I830_GMCH_CTRL, gmch_ctrl);
 712
 713                 pci_read_config_word(intel_private.bridge_dev,
 714                                      I830_GMCH_CTRL, &gmch_ctrl);
 715                 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
 716                         dev_err(&intel_private.pcidev->dev,
 717                                 "failed to enable the GTT: GMCH_CTRL=%x\n",
 718                                 gmch_ctrl);
 719                         return false;
 720                 }
 721         }
 722
 723         /* On the resume path we may be adjusting the PGTBL value, so
 724          * be paranoid and flush all chipset write buffers...
 725          */
 726         if (INTEL_GTT_GEN >= 3)
 727                 writel(0, intel_private.registers+GFX_FLSH_CNTL);
 728
 729         reg = intel_private.registers+I810_PGETBL_CTL;
 730         writel(intel_private.PGETBL_save, reg);
 731         if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
 732                 dev_err(&intel_private.pcidev->dev,
 733                         "failed to enable the GTT: PGETBL=%x [expected %x]\n",
 734                         readl(reg), intel_private.PGETBL_save);
 735                 return false;
 736         }
 737
 738         if (INTEL_GTT_GEN >= 3)
 739                 writel(0, intel_private.registers+GFX_FLSH_CNTL);
 740
 741         return true;
 742 }
 743 EXPORT_SYMBOL(intel_enable_gtt);
 744
 745 static int i830_setup(void)
 746 {
 747         u32 reg_addr;
 748
 749         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
 750         reg_addr &= 0xfff80000;
 751
 752         intel_private.registers = ioremap(reg_addr, KB(64));
 753         if (!intel_private.registers)
 754                 return -ENOMEM;
 755
 756         intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
 757
 758         return 0;
 759 }
 760
 761 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
 762 {
 763         agp_bridge->gatt_table_real = NULL;
 764         agp_bridge->gatt_table = NULL;
 765         agp_bridge->gatt_bus_addr = 0;
 766
 767         return 0;
 768 }
 769
 770 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
 771 {
 772         return 0;
 773 }
 774
 775 static int intel_fake_agp_configure(void)
 776 {
 777         if (!intel_enable_gtt())
 778             return -EIO;
 779
 780         intel_private.clear_fake_agp = true;
 781         agp_bridge->gart_bus_addr = intel_private.base.gma_bus_addr;
 782
 783         return 0;
 784 }
 785
 786 static bool i830_check_flags(unsigned int flags)
 787 {
 788         switch (flags) {
 789         case 0:
 790         case AGP_PHYS_MEMORY:
 791         case AGP_USER_CACHED_MEMORY:
 792         case AGP_USER_MEMORY:
 793                 return true;
 794         }
 795
 796         return false;
 797 }
 798
 799 void intel_gtt_insert_sg_entries(struct sg_table *st,
 800                                  unsigned int pg_start,
 801                                  unsigned int flags)
 802 {
 803         struct scatterlist *sg;
 804         unsigned int len, m;
 805         int i, j;
 806
 807         j = pg_start;
 808
 809         /* sg may merge pages, but we have to separate
 810          * per-page addr for GTT */
 811         for_each_sg(st->sgl, sg, st->nents, i) {
 812                 len = sg_dma_len(sg) >> PAGE_SHIFT;
 813                 for (m = 0; m < len; m++) {
 814                         dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
 815                         intel_private.driver->write_entry(addr, j, flags);
 816                         j++;
 817                 }
 818         }
 819         readl(intel_private.gtt+j-1);
 820 }
 821 EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
 822
 823 static void intel_gtt_insert_pages(unsigned int first_entry,
 824                                    unsigned int num_entries,
 825                                    struct page **pages,
 826                                    unsigned int flags)
 827 {
 828         int i, j;
 829
 830         for (i = 0, j = first_entry; i < num_entries; i++, j++) {
 831                 dma_addr_t addr = page_to_phys(pages[i]);
 832                 intel_private.driver->write_entry(addr,
 833                                                   j, flags);
 834         }
 835         readl(intel_private.gtt+j-1);
 836 }
 837
 838 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
 839                                          off_t pg_start, int type)
 840 {
 841         int ret = -EINVAL;
 842
 843         if (intel_private.base.do_idle_maps)
 844                 return -ENODEV;
 845
 846         if (intel_private.clear_fake_agp) {
 847                 int start = intel_private.base.stolen_size / PAGE_SIZE;
 848                 int end = intel_private.base.gtt_mappable_entries;
 849                 intel_gtt_clear_range(start, end - start);
 850                 intel_private.clear_fake_agp = false;
 851         }
 852
 853         if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
 854                 return i810_insert_dcache_entries(mem, pg_start, type);
 855
 856         if (mem->page_count == 0)
 857                 goto out;
 858
 859         if (pg_start + mem->page_count > intel_private.base.gtt_total_entries)
 860                 goto out_err;
 861
 862         if (type != mem->type)
 863                 goto out_err;
 864
 865         if (!intel_private.driver->check_flags(type))
 866                 goto out_err;
 867
 868         if (!mem->is_flushed)
 869                 global_cache_flush();
 870
 871         if (intel_private.base.needs_dmar) {
 872                 struct sg_table st;
 873
 874                 ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st);
 875                 if (ret != 0)
 876                         return ret;
 877
 878                 intel_gtt_insert_sg_entries(&st, pg_start, type);
 879                 mem->sg_list = st.sgl;
 880                 mem->num_sg = st.nents;
 881         } else
 882                 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
 883                                        type);
 884
 885 out:
 886         ret = 0;
 887 out_err:
 888         mem->is_flushed = true;
 889         return ret;
 890 }
 891
 892 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
 893 {
 894         unsigned int i;
 895
 896         for (i = first_entry; i < (first_entry + num_entries); i++) {
 897                 intel_private.driver->write_entry(intel_private.base.scratch_page_dma,
 898                                                   i, 0);
 899         }
 900         readl(intel_private.gtt+i-1);
 901 }
 902 EXPORT_SYMBOL(intel_gtt_clear_range);
 903
 904 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
 905                                          off_t pg_start, int type)
 906 {
 907         if (mem->page_count == 0)
 908                 return 0;
 909
 910         if (intel_private.base.do_idle_maps)
 911                 return -ENODEV;
 912
 913         intel_gtt_clear_range(pg_start, mem->page_count);
 914
 915         if (intel_private.base.needs_dmar) {
 916                 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
 917                 mem->sg_list = NULL;
 918                 mem->num_sg = 0;
 919         }
 920
 921         return 0;
 922 }
 923
 924 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
 925                                                        int type)
 926 {
 927         struct agp_memory *new;
 928
 929         if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
 930                 if (pg_count != intel_private.num_dcache_entries)
 931                         return NULL;
 932
 933                 new = agp_create_memory(1);
 934                 if (new == NULL)
 935                         return NULL;
 936
 937                 new->type = AGP_DCACHE_MEMORY;
 938                 new->page_count = pg_count;
 939                 new->num_scratch_pages = 0;
 940                 agp_free_page_array(new);
 941                 return new;
 942         }
 943         if (type == AGP_PHYS_MEMORY)
 944                 return alloc_agpphysmem_i8xx(pg_count, type);
 945         /* always return NULL for other allocation types for now */
 946         return NULL;
 947 }
 948
 949 static int intel_alloc_chipset_flush_resource(void)
 950 {
 951         int ret;
 952         ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
 953                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
 954                                      pcibios_align_resource, intel_private.bridge_dev);
 955
 956         return ret;
 957 }
 958
 959 static void intel_i915_setup_chipset_flush(void)
 960 {
 961         int ret;
 962         u32 temp;
 963
 964         pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
 965         if (!(temp & 0x1)) {
 966                 intel_alloc_chipset_flush_resource();
 967                 intel_private.resource_valid = 1;
 968                 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
 969         } else {
 970                 temp &= ~1;
 971
 972                 intel_private.resource_valid = 1;
 973                 intel_private.ifp_resource.start = temp;
 974                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
 975                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
 976                 /* some BIOSes reserve this area in a pnp some don't */
 977                 if (ret)
 978                         intel_private.resource_valid = 0;
 979         }
 980 }
 981
 982 static void intel_i965_g33_setup_chipset_flush(void)
 983 {
 984         u32 temp_hi, temp_lo;
 985         int ret;
 986
 987         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
 988         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
 989
 990         if (!(temp_lo & 0x1)) {
 991
 992                 intel_alloc_chipset_flush_resource();
 993
 994                 intel_private.resource_valid = 1;
 995                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
 996                         upper_32_bits(intel_private.ifp_resource.start));
 997                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
 998         } else {
 999                 u64 l64;
1000
1001                 temp_lo &= ~0x1;
1002                 l64 = ((u64)temp_hi << 32) | temp_lo;
1003
1004                 intel_private.resource_valid = 1;
1005                 intel_private.ifp_resource.start = l64;
1006                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1007                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1008                 /* some BIOSes reserve this area in a pnp some don't */
1009                 if (ret)
1010                         intel_private.resource_valid = 0;
1011         }
1012 }
1013
1014 static void intel_i9xx_setup_flush(void)
1015 {
1016         /* return if already configured */
1017         if (intel_private.ifp_resource.start)
1018                 return;
1019
1020         if (INTEL_GTT_GEN == 6)
1021                 return;
1022
1023         /* setup a resource for this object */
1024         intel_private.ifp_resource.name = "Intel Flush Page";
1025         intel_private.ifp_resource.flags = IORESOURCE_MEM;
1026
1027         /* Setup chipset flush for 915 */
1028         if (IS_G33 || INTEL_GTT_GEN >= 4) {
1029                 intel_i965_g33_setup_chipset_flush();
1030         } else {
1031                 intel_i915_setup_chipset_flush();
1032         }
1033
1034         if (intel_private.ifp_resource.start)
1035                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1036         if (!intel_private.i9xx_flush_page)
1037                 dev_err(&intel_private.pcidev->dev,
1038                         "can't ioremap flush page - no chipset flushing\n");
1039 }
1040
1041 static void i9xx_cleanup(void)
1042 {
1043         if (intel_private.i9xx_flush_page)
1044                 iounmap(intel_private.i9xx_flush_page);
1045         if (intel_private.resource_valid)
1046                 release_resource(&intel_private.ifp_resource);
1047         intel_private.ifp_resource.start = 0;
1048         intel_private.resource_valid = 0;
1049 }
1050
1051 static void i9xx_chipset_flush(void)
1052 {
1053         if (intel_private.i9xx_flush_page)
1054                 writel(1, intel_private.i9xx_flush_page);
1055 }
1056
1057 static void i965_write_entry(dma_addr_t addr,
1058                              unsigned int entry,
1059                              unsigned int flags)
1060 {
1061         u32 pte_flags;
1062
1063         pte_flags = I810_PTE_VALID;
1064         if (flags == AGP_USER_CACHED_MEMORY)
1065                 pte_flags |= I830_PTE_SYSTEM_CACHED;
1066
1067         /* Shift high bits down */
1068         addr |= (addr >> 28) & 0xf0;
1069         writel(addr | pte_flags, intel_private.gtt + entry);
1070 }
1071
1072 /* Certain Gen5 chipsets require require idling the GPU before
1073  * unmapping anything from the GTT when VT-d is enabled.
1074  */
1075 static inline int needs_idle_maps(void)
1076 {
1077 #ifdef CONFIG_INTEL_IOMMU
1078         const unsigned short gpu_devid = intel_private.pcidev->device;
1079
1080         /* Query intel_iommu to see if we need the workaround. Presumably that
1081          * was loaded first.
1082          */
1083         if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB ||
1084              gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
1085              intel_iommu_gfx_mapped)
1086                 return 1;
1087 #endif
1088         return 0;
1089 }
1090
1091 static int i9xx_setup(void)
1092 {
1093         u32 reg_addr, gtt_addr;
1094         int size = KB(512);
1095
1096         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1097
1098         reg_addr &= 0xfff80000;
1099
1100         intel_private.registers = ioremap(reg_addr, size);
1101         if (!intel_private.registers)
1102                 return -ENOMEM;
1103
1104         switch (INTEL_GTT_GEN) {
1105         case 3:
1106                 pci_read_config_dword(intel_private.pcidev,
1107                                       I915_PTEADDR, &gtt_addr);
1108                 intel_private.gtt_bus_addr = gtt_addr;
1109                 break;
1110         case 5:
1111                 intel_private.gtt_bus_addr = reg_addr + MB(2);
1112                 break;
1113         default:
1114                 intel_private.gtt_bus_addr = reg_addr + KB(512);
1115                 break;
1116         }
1117
1118         if (needs_idle_maps())
1119                 intel_private.base.do_idle_maps = 1;
1120
1121         intel_i9xx_setup_flush();
1122
1123         return 0;
1124 }
1125
1126 static const struct agp_bridge_driver intel_fake_agp_driver = {
1127         .owner                  = THIS_MODULE,
1128         .size_type              = FIXED_APER_SIZE,
1129         .aperture_sizes         = intel_fake_agp_sizes,
1130         .num_aperture_sizes     = ARRAY_SIZE(intel_fake_agp_sizes),
1131         .configure              = intel_fake_agp_configure,
1132         .fetch_size             = intel_fake_agp_fetch_size,
1133         .cleanup                = intel_gtt_cleanup,
1134         .agp_enable             = intel_fake_agp_enable,
1135         .cache_flush            = global_cache_flush,
1136         .create_gatt_table      = intel_fake_agp_create_gatt_table,
1137         .free_gatt_table        = intel_fake_agp_free_gatt_table,
1138         .insert_memory          = intel_fake_agp_insert_entries,
1139         .remove_memory          = intel_fake_agp_remove_entries,
1140         .alloc_by_type          = intel_fake_agp_alloc_by_type,
1141         .free_by_type           = intel_i810_free_by_type,
1142         .agp_alloc_page         = agp_generic_alloc_page,
1143         .agp_alloc_pages        = agp_generic_alloc_pages,
1144         .agp_destroy_page       = agp_generic_destroy_page,
1145         .agp_destroy_pages      = agp_generic_destroy_pages,
1146 };
1147
1148 static const struct intel_gtt_driver i81x_gtt_driver = {
1149         .gen = 1,
1150         .has_pgtbl_enable = 1,
1151         .dma_mask_size = 32,
1152         .setup = i810_setup,
1153         .cleanup = i810_cleanup,
1154         .check_flags = i830_check_flags,
1155         .write_entry = i810_write_entry,
1156 };
1157 static const struct intel_gtt_driver i8xx_gtt_driver = {
1158         .gen = 2,
1159         .has_pgtbl_enable = 1,
1160         .setup = i830_setup,
1161         .cleanup = i830_cleanup,
1162         .write_entry = i830_write_entry,
1163         .dma_mask_size = 32,
1164         .check_flags = i830_check_flags,
1165         .chipset_flush = i830_chipset_flush,
1166 };
1167 static const struct intel_gtt_driver i915_gtt_driver = {
1168         .gen = 3,
1169         .has_pgtbl_enable = 1,
1170         .setup = i9xx_setup,
1171         .cleanup = i9xx_cleanup,
1172         /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1173         .write_entry = i830_write_entry,
1174         .dma_mask_size = 32,
1175         .check_flags = i830_check_flags,
1176         .chipset_flush = i9xx_chipset_flush,
1177 };
1178 static const struct intel_gtt_driver g33_gtt_driver = {
1179         .gen = 3,
1180         .is_g33 = 1,
1181         .setup = i9xx_setup,
1182         .cleanup = i9xx_cleanup,
1183         .write_entry = i965_write_entry,
1184         .dma_mask_size = 36,
1185         .check_flags = i830_check_flags,
1186         .chipset_flush = i9xx_chipset_flush,
1187 };
1188 static const struct intel_gtt_driver pineview_gtt_driver = {
1189         .gen = 3,
1190         .is_pineview = 1, .is_g33 = 1,
1191         .setup = i9xx_setup,
1192         .cleanup = i9xx_cleanup,
1193         .write_entry = i965_write_entry,
1194         .dma_mask_size = 36,
1195         .check_flags = i830_check_flags,
1196         .chipset_flush = i9xx_chipset_flush,
1197 };
1198 static const struct intel_gtt_driver i965_gtt_driver = {
1199         .gen = 4,
1200         .has_pgtbl_enable = 1,
1201         .setup = i9xx_setup,
1202         .cleanup = i9xx_cleanup,
1203         .write_entry = i965_write_entry,
1204         .dma_mask_size = 36,
1205         .check_flags = i830_check_flags,
1206         .chipset_flush = i9xx_chipset_flush,
1207 };
1208 static const struct intel_gtt_driver g4x_gtt_driver = {
1209         .gen = 5,
1210         .setup = i9xx_setup,
1211         .cleanup = i9xx_cleanup,
1212         .write_entry = i965_write_entry,
1213         .dma_mask_size = 36,
1214         .check_flags = i830_check_flags,
1215         .chipset_flush = i9xx_chipset_flush,
1216 };
1217 static const struct intel_gtt_driver ironlake_gtt_driver = {
1218         .gen = 5,
1219         .is_ironlake = 1,
1220         .setup = i9xx_setup,
1221         .cleanup = i9xx_cleanup,
1222         .write_entry = i965_write_entry,
1223         .dma_mask_size = 36,
1224         .check_flags = i830_check_flags,
1225         .chipset_flush = i9xx_chipset_flush,
1226 };
1227
1228 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1229  * driver and gmch_driver must be non-null, and find_gmch will determine
1230  * which one should be used if a gmch_chip_id is present.
1231  */
1232 static const struct intel_gtt_driver_description {
1233         unsigned int gmch_chip_id;
1234         char *name;
1235         const struct intel_gtt_driver *gtt_driver;
1236 } intel_gtt_chipsets[] = {
1237         { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1238                 &i81x_gtt_driver},
1239         { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1240                 &i81x_gtt_driver},
1241         { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1242                 &i81x_gtt_driver},
1243         { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1244                 &i81x_gtt_driver},
1245         { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1246                 &i8xx_gtt_driver},
1247         { PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
1248                 &i8xx_gtt_driver},
1249         { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1250                 &i8xx_gtt_driver},
1251         { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1252                 &i8xx_gtt_driver},
1253         { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1254                 &i8xx_gtt_driver},
1255         { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1256                 &i915_gtt_driver },
1257         { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1258                 &i915_gtt_driver },
1259         { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1260                 &i915_gtt_driver },
1261         { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1262                 &i915_gtt_driver },
1263         { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1264                 &i915_gtt_driver },
1265         { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1266                 &i915_gtt_driver },
1267         { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1268                 &i965_gtt_driver },
1269         { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1270                 &i965_gtt_driver },
1271         { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1272                 &i965_gtt_driver },
1273         { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1274                 &i965_gtt_driver },
1275         { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1276                 &i965_gtt_driver },
1277         { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1278                 &i965_gtt_driver },
1279         { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1280                 &g33_gtt_driver },
1281         { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1282                 &g33_gtt_driver },
1283         { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1284                 &g33_gtt_driver },
1285         { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1286                 &pineview_gtt_driver },
1287         { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1288                 &pineview_gtt_driver },
1289         { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1290                 &g4x_gtt_driver },
1291         { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1292                 &g4x_gtt_driver },
1293         { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1294                 &g4x_gtt_driver },
1295         { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1296                 &g4x_gtt_driver },
1297         { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1298                 &g4x_gtt_driver },
1299         { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1300                 &g4x_gtt_driver },
1301         { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1302                 &g4x_gtt_driver },
1303         { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1304             "HD Graphics", &ironlake_gtt_driver },
1305         { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1306             "HD Graphics", &ironlake_gtt_driver },
1307         { 0, NULL, NULL }
1308 };
1309
1310 static int find_gmch(u16 device)
1311 {
1312         struct pci_dev *gmch_device;
1313
1314         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1315         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1316                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1317                                              device, gmch_device);
1318         }
1319
1320         if (!gmch_device)
1321                 return 0;
1322
1323         intel_private.pcidev = gmch_device;
1324         return 1;
1325 }
1326
1327 int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
1328                      struct agp_bridge_data *bridge)
1329 {
1330         int i, mask;
1331
1332         /*
1333          * Can be called from the fake agp driver but also directly from
1334          * drm/i915.ko. Hence we need to check whether everything is set up
1335          * already.
1336          */
1337         if (intel_private.driver) {
1338                 intel_private.refcount++;
1339                 return 1;
1340         }
1341
1342         for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1343                 if (gpu_pdev) {
1344                         if (gpu_pdev->device ==
1345                             intel_gtt_chipsets[i].gmch_chip_id) {
1346                                 intel_private.pcidev = pci_dev_get(gpu_pdev);
1347                                 intel_private.driver =
1348                                         intel_gtt_chipsets[i].gtt_driver;
1349
1350                                 break;
1351                         }
1352                 } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1353                         intel_private.driver =
1354                                 intel_gtt_chipsets[i].gtt_driver;
1355                         break;
1356                 }
1357         }
1358
1359         if (!intel_private.driver)
1360                 return 0;
1361
1362         intel_private.refcount++;
1363
1364         if (bridge) {
1365                 bridge->driver = &intel_fake_agp_driver;
1366                 bridge->dev_private_data = &intel_private;
1367                 bridge->dev = bridge_pdev;
1368         }
1369
1370         intel_private.bridge_dev = pci_dev_get(bridge_pdev);
1371
1372         dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1373
1374         mask = intel_private.driver->dma_mask_size;
1375         if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1376                 dev_err(&intel_private.pcidev->dev,
1377                         "set gfx device dma mask %d-bit failed!\n", mask);
1378         else
1379                 pci_set_consistent_dma_mask(intel_private.pcidev,
1380                                             DMA_BIT_MASK(mask));
1381
1382         if (intel_gtt_init() != 0) {
1383                 intel_gmch_remove();
1384
1385                 return 0;
1386         }
1387
1388         return 1;
1389 }
1390 EXPORT_SYMBOL(intel_gmch_probe);
1391
1392 struct intel_gtt *intel_gtt_get(void)
1393 {
1394         return &intel_private.base;
1395 }
1396 EXPORT_SYMBOL(intel_gtt_get);
1397
1398 void intel_gtt_chipset_flush(void)
1399 {
1400         if (intel_private.driver->chipset_flush)
1401                 intel_private.driver->chipset_flush();
1402 }
1403 EXPORT_SYMBOL(intel_gtt_chipset_flush);
1404
1405 void intel_gmch_remove(void)
1406 {
1407         if (--intel_private.refcount)
1408                 return;
1409
1410         if (intel_private.pcidev)
1411                 pci_dev_put(intel_private.pcidev);
1412         if (intel_private.bridge_dev)
1413                 pci_dev_put(intel_private.bridge_dev);
1414         intel_private.driver = NULL;
1415 }
1416 EXPORT_SYMBOL(intel_gmch_remove);
1417
1418 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1419 MODULE_LICENSE("GPL and additional rights");