2 * UniNorth AGPGART routines.
4 #include <linux/module.h>
6 #include <linux/slab.h>
7 #include <linux/init.h>
8 #include <linux/pagemap.h>
9 #include <linux/agp_backend.h>
10 #include <linux/delay.h>
11 #include <linux/vmalloc.h>
12 #include <asm/uninorth.h>
13 #include <asm/pci-bridge.h>
15 #include <asm/pmac_feature.h>
19 * NOTES for uninorth3 (G5 AGP) supports :
21 * There maybe also possibility to have bigger cache line size for
22 * agp (see pmac_pci.c and look for cache line). Need to be investigated
25 * PAGE size are hardcoded but this may change, see asm/page.h.
27 * Jerome Glisse <j.glisse@gmail.com>
29 static int uninorth_rev;
32 #define DEFAULT_APERTURE_SIZE 256
33 #define DEFAULT_APERTURE_STRING "256"
34 static char *aperture = NULL;
36 static int uninorth_fetch_size(void)
39 struct aper_size_info_32 *values =
40 A_SIZE_32(agp_bridge->driver->aperture_sizes);
43 char *save = aperture;
45 size = memparse(aperture, &aperture) >> 20;
48 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++)
49 if (size == values[i].size)
52 if (i == agp_bridge->driver->num_aperture_sizes) {
53 dev_err(&agp_bridge->dev->dev, "invalid aperture size, "
61 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++)
62 if (values[i].size == DEFAULT_APERTURE_SIZE)
66 agp_bridge->previous_size =
67 agp_bridge->current_size = (void *)(values + i);
68 agp_bridge->aperture_size_idx = i;
69 return values[i].size;
72 static void uninorth_tlbflush(struct agp_memory *mem)
74 u32 ctrl = UNI_N_CFG_GART_ENABLE;
77 ctrl |= U3_N_CFG_GART_PERFRD;
78 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
79 ctrl | UNI_N_CFG_GART_INVAL);
80 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl);
82 if (uninorth_rev <= 0x30) {
83 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
84 ctrl | UNI_N_CFG_GART_2xRESET);
85 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
90 static void uninorth_cleanup(void)
94 pci_read_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, &tmp);
95 if (!(tmp & UNI_N_CFG_GART_ENABLE))
97 tmp |= UNI_N_CFG_GART_INVAL;
98 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, tmp);
99 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 0);
101 if (uninorth_rev <= 0x30) {
102 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
103 UNI_N_CFG_GART_2xRESET);
104 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
109 static int uninorth_configure(void)
111 struct aper_size_info_32 *current_size;
113 current_size = A_SIZE_32(agp_bridge->current_size);
115 dev_info(&agp_bridge->dev->dev, "configuring for size idx: %d\n",
116 current_size->size_value);
118 /* aperture size and gatt addr */
119 pci_write_config_dword(agp_bridge->dev,
121 (agp_bridge->gatt_bus_addr & 0xfffff000)
122 | current_size->size_value);
125 * UniNorth seem to be buggy enough not to handle properly when
126 * the AGP aperture isn't mapped at bus physical address 0
128 agp_bridge->gart_bus_addr = 0;
130 /* Assume U3 or later on PPC64 systems */
131 /* high 4 bits of GART physical address go in UNI_N_CFG_AGP_BASE */
132 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_AGP_BASE,
133 (agp_bridge->gatt_bus_addr >> 32) & 0xf);
135 pci_write_config_dword(agp_bridge->dev,
136 UNI_N_CFG_AGP_BASE, agp_bridge->gart_bus_addr);
140 pci_write_config_dword(agp_bridge->dev,
141 UNI_N_CFG_GART_DUMMY_PAGE,
142 page_to_phys(agp_bridge->scratch_page_page) >> 12);
148 static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
155 if (type != mem->type)
158 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
159 if (mask_type != 0) {
160 /* We know nothing of memory types */
164 if (mem->page_count == 0)
167 temp = agp_bridge->current_size;
168 num_entries = A_SIZE_32(temp)->num_entries;
170 if ((pg_start + mem->page_count) > num_entries)
173 gp = (u32 *) &agp_bridge->gatt_table[pg_start];
174 for (i = 0; i < mem->page_count; ++i) {
176 dev_info(&agp_bridge->dev->dev,
177 "uninorth_insert_memory: entry 0x%x occupied (%x)\n",
183 for (i = 0; i < mem->page_count; i++) {
185 gp[i] = (page_to_phys(mem->pages[i]) >> PAGE_SHIFT) | 0x80000000UL;
187 gp[i] = cpu_to_le32((page_to_phys(mem->pages[i]) & 0xFFFFF000UL) |
189 flush_dcache_range((unsigned long)__va(page_to_phys(mem->pages[i])),
190 (unsigned long)__va(page_to_phys(mem->pages[i]))+0x1000);
193 uninorth_tlbflush(mem);
198 int uninorth_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
204 if (type != mem->type)
207 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
208 if (mask_type != 0) {
209 /* We know nothing of memory types */
213 if (mem->page_count == 0)
216 gp = (u32 *) &agp_bridge->gatt_table[pg_start];
217 for (i = 0; i < mem->page_count; ++i)
220 uninorth_tlbflush(mem);
225 static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode)
227 u32 command, scratch, status;
230 pci_read_config_dword(bridge->dev,
231 bridge->capndx + PCI_AGP_STATUS,
234 command = agp_collect_device_status(bridge, mode, status);
235 command |= PCI_AGP_COMMAND_AGP;
237 if (uninorth_rev == 0x21) {
239 * Darwin disable AGP 4x on this revision, thus we
240 * may assume it's broken. This is an AGP2 controller.
242 command &= ~AGPSTAT2_4X;
245 if ((uninorth_rev >= 0x30) && (uninorth_rev <= 0x33)) {
247 * We need to set REQ_DEPTH to 7 for U3 versions 1.0, 2.1,
248 * 2.2 and 2.3, Darwin do so.
250 if ((command >> AGPSTAT_RQ_DEPTH_SHIFT) > 7)
251 command = (command & ~AGPSTAT_RQ_DEPTH)
252 | (7 << AGPSTAT_RQ_DEPTH_SHIFT);
255 uninorth_tlbflush(NULL);
259 pci_write_config_dword(bridge->dev,
260 bridge->capndx + PCI_AGP_COMMAND,
262 pci_read_config_dword(bridge->dev,
263 bridge->capndx + PCI_AGP_COMMAND,
265 } while ((scratch & PCI_AGP_COMMAND_AGP) == 0 && ++timeout < 1000);
266 if ((scratch & PCI_AGP_COMMAND_AGP) == 0)
267 dev_err(&bridge->dev->dev, "can't write UniNorth AGP "
268 "command register\n");
270 if (uninorth_rev >= 0x30) {
271 /* This is an AGP V3 */
272 agp_device_command(command, (status & AGPSTAT_MODE_3_0) != 0);
275 agp_device_command(command, false);
278 uninorth_tlbflush(NULL);
283 * These Power Management routines are _not_ called by the normal PCI PM layer,
284 * but directly by the video driver through function pointers in the device
287 static int agp_uninorth_suspend(struct pci_dev *pdev)
289 struct agp_bridge_data *bridge;
292 struct pci_dev *device = NULL;
294 bridge = agp_find_bridge(pdev);
298 /* Only one suspend supported */
299 if (bridge->dev_private_data)
302 /* turn off AGP on the video chip, if it was enabled */
303 for_each_pci_dev(device) {
304 /* Don't touch the bridge yet, device first */
307 /* Only deal with devices on the same bus here, no Mac has a P2P
308 * bridge on the AGP port, and mucking around the entire PCI
309 * tree is source of problems on some machines because of a bug
310 * in some versions of pci_find_capability() when hitting a dead
313 if (device->bus != pdev->bus)
315 agp = pci_find_capability(device, PCI_CAP_ID_AGP);
318 pci_read_config_dword(device, agp + PCI_AGP_COMMAND, &cmd);
319 if (!(cmd & PCI_AGP_COMMAND_AGP))
321 dev_info(&pdev->dev, "disabling AGP on device %s\n",
323 cmd &= ~PCI_AGP_COMMAND_AGP;
324 pci_write_config_dword(device, agp + PCI_AGP_COMMAND, cmd);
327 /* turn off AGP on the bridge */
328 agp = pci_find_capability(pdev, PCI_CAP_ID_AGP);
329 pci_read_config_dword(pdev, agp + PCI_AGP_COMMAND, &cmd);
330 bridge->dev_private_data = (void *)(long)cmd;
331 if (cmd & PCI_AGP_COMMAND_AGP) {
332 dev_info(&pdev->dev, "disabling AGP on bridge\n");
333 cmd &= ~PCI_AGP_COMMAND_AGP;
334 pci_write_config_dword(pdev, agp + PCI_AGP_COMMAND, cmd);
336 /* turn off the GART */
342 static int agp_uninorth_resume(struct pci_dev *pdev)
344 struct agp_bridge_data *bridge;
347 bridge = agp_find_bridge(pdev);
351 command = (long)bridge->dev_private_data;
352 bridge->dev_private_data = NULL;
353 if (!(command & PCI_AGP_COMMAND_AGP))
356 uninorth_agp_enable(bridge, command);
360 #endif /* CONFIG_PM */
362 static int uninorth_create_gatt_table(struct agp_bridge_data *bridge)
374 /* We can't handle 2 level gatt's */
375 if (bridge->driver->size_type == LVL2_APER_SIZE)
379 i = bridge->aperture_size_idx;
380 temp = bridge->current_size;
381 size = page_order = num_entries = 0;
384 size = A_SIZE_32(temp)->size;
385 page_order = A_SIZE_32(temp)->page_order;
386 num_entries = A_SIZE_32(temp)->num_entries;
388 table = (char *) __get_free_pages(GFP_KERNEL, page_order);
392 bridge->current_size = A_IDX32(bridge);
394 bridge->aperture_size_idx = i;
396 } while (!table && (i < bridge->driver->num_aperture_sizes));
401 pages = kmalloc((1 << page_order) * sizeof(struct page*), GFP_KERNEL);
405 table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
407 for (page = virt_to_page(table), i = 0; page <= virt_to_page(table_end);
409 SetPageReserved(page);
413 bridge->gatt_table_real = (u32 *) table;
414 /* Need to clear out any dirty data still sitting in caches */
415 flush_dcache_range((unsigned long)table,
416 (unsigned long)(table_end + PAGE_SIZE));
417 bridge->gatt_table = vmap(pages, (1 << page_order), 0, PAGE_KERNEL_NCG);
419 if (bridge->gatt_table == NULL)
422 bridge->gatt_bus_addr = virt_to_phys(table);
424 for (i = 0; i < num_entries; i++)
425 bridge->gatt_table[i] = 0;
432 free_pages((unsigned long)table, page_order);
436 static int uninorth_free_gatt_table(struct agp_bridge_data *bridge)
439 char *table, *table_end;
443 temp = bridge->current_size;
444 page_order = A_SIZE_32(temp)->page_order;
446 /* Do not worry about freeing memory, because if this is
447 * called, then all agp memory is deallocated and removed
451 vunmap(bridge->gatt_table);
452 table = (char *) bridge->gatt_table_real;
453 table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
455 for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
456 ClearPageReserved(page);
458 free_pages((unsigned long) bridge->gatt_table_real, page_order);
463 void null_cache_flush(void)
470 static const struct aper_size_info_32 uninorth_sizes[] =
482 * Not sure that u3 supports that high aperture sizes but it
483 * would strange if it did not :)
485 static const struct aper_size_info_32 u3_sizes[] =
487 {512, 131072, 7, 128},
497 const struct agp_bridge_driver uninorth_agp_driver = {
498 .owner = THIS_MODULE,
499 .aperture_sizes = (void *)uninorth_sizes,
500 .size_type = U32_APER_SIZE,
501 .num_aperture_sizes = ARRAY_SIZE(uninorth_sizes),
502 .configure = uninorth_configure,
503 .fetch_size = uninorth_fetch_size,
504 .cleanup = uninorth_cleanup,
505 .tlb_flush = uninorth_tlbflush,
506 .mask_memory = agp_generic_mask_memory,
508 .cache_flush = null_cache_flush,
509 .agp_enable = uninorth_agp_enable,
510 .create_gatt_table = uninorth_create_gatt_table,
511 .free_gatt_table = uninorth_free_gatt_table,
512 .insert_memory = uninorth_insert_memory,
513 .remove_memory = uninorth_remove_memory,
514 .alloc_by_type = agp_generic_alloc_by_type,
515 .free_by_type = agp_generic_free_by_type,
516 .agp_alloc_page = agp_generic_alloc_page,
517 .agp_alloc_pages = agp_generic_alloc_pages,
518 .agp_destroy_page = agp_generic_destroy_page,
519 .agp_destroy_pages = agp_generic_destroy_pages,
520 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
521 .cant_use_aperture = true,
524 const struct agp_bridge_driver u3_agp_driver = {
525 .owner = THIS_MODULE,
526 .aperture_sizes = (void *)u3_sizes,
527 .size_type = U32_APER_SIZE,
528 .num_aperture_sizes = ARRAY_SIZE(u3_sizes),
529 .configure = uninorth_configure,
530 .fetch_size = uninorth_fetch_size,
531 .cleanup = uninorth_cleanup,
532 .tlb_flush = uninorth_tlbflush,
533 .mask_memory = agp_generic_mask_memory,
535 .cache_flush = null_cache_flush,
536 .agp_enable = uninorth_agp_enable,
537 .create_gatt_table = uninorth_create_gatt_table,
538 .free_gatt_table = uninorth_free_gatt_table,
539 .insert_memory = uninorth_insert_memory,
540 .remove_memory = uninorth_remove_memory,
541 .alloc_by_type = agp_generic_alloc_by_type,
542 .free_by_type = agp_generic_free_by_type,
543 .agp_alloc_page = agp_generic_alloc_page,
544 .agp_alloc_pages = agp_generic_alloc_pages,
545 .agp_destroy_page = agp_generic_destroy_page,
546 .agp_destroy_pages = agp_generic_destroy_pages,
547 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
548 .cant_use_aperture = true,
549 .needs_scratch_page = true,
552 static struct agp_device_ids uninorth_agp_device_ids[] __devinitdata = {
554 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP,
555 .chipset_name = "UniNorth",
558 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP_P,
559 .chipset_name = "UniNorth/Pangea",
562 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP15,
563 .chipset_name = "UniNorth 1.5",
566 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP2,
567 .chipset_name = "UniNorth 2",
570 .device_id = PCI_DEVICE_ID_APPLE_U3_AGP,
571 .chipset_name = "U3",
574 .device_id = PCI_DEVICE_ID_APPLE_U3L_AGP,
575 .chipset_name = "U3L",
578 .device_id = PCI_DEVICE_ID_APPLE_U3H_AGP,
579 .chipset_name = "U3H",
582 .device_id = PCI_DEVICE_ID_APPLE_IPID2_AGP,
583 .chipset_name = "UniNorth/Intrepid2",
587 static int __devinit agp_uninorth_probe(struct pci_dev *pdev,
588 const struct pci_device_id *ent)
590 struct agp_device_ids *devs = uninorth_agp_device_ids;
591 struct agp_bridge_data *bridge;
592 struct device_node *uninorth_node;
596 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
600 /* probe for known chipsets */
601 for (j = 0; devs[j].chipset_name != NULL; ++j) {
602 if (pdev->device == devs[j].device_id) {
603 dev_info(&pdev->dev, "Apple %s chipset\n",
604 devs[j].chipset_name);
609 dev_err(&pdev->dev, "unsupported Apple chipset [%04x/%04x]\n",
610 pdev->vendor, pdev->device);
614 /* Set revision to 0 if we could not read it. */
617 /* Locate core99 Uni-N */
618 uninorth_node = of_find_node_by_name(NULL, "uni-n");
620 if (uninorth_node == NULL) {
622 uninorth_node = of_find_node_by_name(NULL, "u3");
625 const int *revprop = of_get_property(uninorth_node,
628 uninorth_rev = *revprop & 0x3f;
629 of_node_put(uninorth_node);
633 /* Inform platform of our suspend/resume caps */
634 pmac_register_agp_pm(pdev, agp_uninorth_suspend, agp_uninorth_resume);
637 /* Allocate & setup our driver */
638 bridge = agp_alloc_bridge();
643 bridge->driver = &u3_agp_driver;
645 bridge->driver = &uninorth_agp_driver;
648 bridge->capndx = cap_ptr;
649 bridge->flags = AGP_ERRATA_FASTWRITES;
651 /* Fill in the mode register */
652 pci_read_config_dword(pdev, cap_ptr+PCI_AGP_STATUS, &bridge->mode);
654 pci_set_drvdata(pdev, bridge);
655 return agp_add_bridge(bridge);
658 static void __devexit agp_uninorth_remove(struct pci_dev *pdev)
660 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
663 /* Inform platform of our suspend/resume caps */
664 pmac_register_agp_pm(pdev, NULL, NULL);
667 agp_remove_bridge(bridge);
668 agp_put_bridge(bridge);
671 static struct pci_device_id agp_uninorth_pci_table[] = {
673 .class = (PCI_CLASS_BRIDGE_HOST << 8),
675 .vendor = PCI_VENDOR_ID_APPLE,
676 .device = PCI_ANY_ID,
677 .subvendor = PCI_ANY_ID,
678 .subdevice = PCI_ANY_ID,
683 MODULE_DEVICE_TABLE(pci, agp_uninorth_pci_table);
685 static struct pci_driver agp_uninorth_pci_driver = {
686 .name = "agpgart-uninorth",
687 .id_table = agp_uninorth_pci_table,
688 .probe = agp_uninorth_probe,
689 .remove = agp_uninorth_remove,
692 static int __init agp_uninorth_init(void)
696 return pci_register_driver(&agp_uninorth_pci_driver);
699 static void __exit agp_uninorth_cleanup(void)
701 pci_unregister_driver(&agp_uninorth_pci_driver);
704 module_init(agp_uninorth_init);
705 module_exit(agp_uninorth_cleanup);
707 module_param(aperture, charp, 0);
708 MODULE_PARM_DESC(aperture,
709 "Aperture size, must be power of two between 4MB and an\n"
710 "\t\tupper limit specific to the UniNorth revision.\n"
711 "\t\tDefault: " DEFAULT_APERTURE_STRING "M");
713 MODULE_AUTHOR("Ben Herrenschmidt & Paul Mackerras");
714 MODULE_LICENSE("GPL");