drivers/char/drm/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2007 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  */
  31
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "radeon_drm.h"
  35 #include "radeon_drv.h"
  36 #include "r300_reg.h"
  37
  38 #include "radeon_microcode.h"
  39
  40 #define RADEON_FIFO_DEBUG       0
  41
  42 static int radeon_do_cleanup_cp(struct drm_device * dev);
  43
  44 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  45 {
  46         u32 ret;
  47         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
  48         ret = RADEON_READ(R520_MC_IND_DATA);
  49         RADEON_WRITE(R520_MC_IND_INDEX, 0);
  50         return ret;
  51 }
  52
  53 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  54 {
  55         u32 ret;
  56         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
  57         ret = RADEON_READ(RS480_NB_MC_DATA);
  58         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
  59         return ret;
  60 }
  61
  62 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  63 {
  64         u32 ret;
  65         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
  66         ret = RADEON_READ(RS690_MC_DATA);
  67         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
  68         return ret;
  69 }
  70
  71 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  72 {
  73         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  74                 return RS690_READ_MCIND(dev_priv, addr);
  75         else
  76                 return RS480_READ_MCIND(dev_priv, addr);
  77 }
  78
  79 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
  80 {
  81
  82         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  83                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
  84         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  85                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
  86         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
  87                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
  88         else
  89                 return RADEON_READ(RADEON_MC_FB_LOCATION);
  90 }
  91
  92 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
  93 {
  94         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  95                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
  96         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  97                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
  98         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
  99                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 100         else
 101                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 102 }
 103
 104 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 105 {
 106         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 107                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 108         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 109                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 110         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 111                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 112         else
 113                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 114 }
 115
 116 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 117 {
 118         drm_radeon_private_t *dev_priv = dev->dev_private;
 119
 120         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 121         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 122 }
 123
 124 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 125 {
 126         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 127         return RADEON_READ(RADEON_PCIE_DATA);
 128 }
 129
 130 #if RADEON_FIFO_DEBUG
 131 static void radeon_status(drm_radeon_private_t * dev_priv)
 132 {
 133         printk("%s:\n", __func__);
 134         printk("RBBM_STATUS = 0x%08x\n",
 135                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 136         printk("CP_RB_RTPR = 0x%08x\n",
 137                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 138         printk("CP_RB_WTPR = 0x%08x\n",
 139                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 140         printk("AIC_CNTL = 0x%08x\n",
 141                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 142         printk("AIC_STAT = 0x%08x\n",
 143                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 144         printk("AIC_PT_BASE = 0x%08x\n",
 145                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 146         printk("TLB_ADDR = 0x%08x\n",
 147                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 148         printk("TLB_DATA = 0x%08x\n",
 149                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 150 }
 151 #endif
 152
 153 /* ================================================================
 154  * Engine, FIFO control
 155  */
 156
 157 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 158 {
 159         u32 tmp;
 160         int i;
 161
 162         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 163
 164         tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 165         tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 166         RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 167
 168         for (i = 0; i < dev_priv->usec_timeout; i++) {
 169                 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 170                       & RADEON_RB3D_DC_BUSY)) {
 171                         return 0;
 172                 }
 173                 DRM_UDELAY(1);
 174         }
 175
 176 #if RADEON_FIFO_DEBUG
 177         DRM_ERROR("failed!\n");
 178         radeon_status(dev_priv);
 179 #endif
 180         return -EBUSY;
 181 }
 182
 183 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 184 {
 185         int i;
 186
 187         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 188
 189         for (i = 0; i < dev_priv->usec_timeout; i++) {
 190                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 191                              & RADEON_RBBM_FIFOCNT_MASK);
 192                 if (slots >= entries)
 193                         return 0;
 194                 DRM_UDELAY(1);
 195         }
 196
 197 #if RADEON_FIFO_DEBUG
 198         DRM_ERROR("failed!\n");
 199         radeon_status(dev_priv);
 200 #endif
 201         return -EBUSY;
 202 }
 203
 204 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 205 {
 206         int i, ret;
 207
 208         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 209
 210         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 211         if (ret)
 212                 return ret;
 213
 214         for (i = 0; i < dev_priv->usec_timeout; i++) {
 215                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 216                       & RADEON_RBBM_ACTIVE)) {
 217                         radeon_do_pixcache_flush(dev_priv);
 218                         return 0;
 219                 }
 220                 DRM_UDELAY(1);
 221         }
 222
 223 #if RADEON_FIFO_DEBUG
 224         DRM_ERROR("failed!\n");
 225         radeon_status(dev_priv);
 226 #endif
 227         return -EBUSY;
 228 }
 229
 230 /* ================================================================
 231  * CP control, initialization
 232  */
 233
 234 /* Load the microcode for the CP */
 235 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 236 {
 237         int i;
 238         DRM_DEBUG("\n");
 239
 240         radeon_do_wait_for_idle(dev_priv);
 241
 242         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 243         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 244             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 245             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 246             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 247             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 248                 DRM_INFO("Loading R100 Microcode\n");
 249                 for (i = 0; i < 256; i++) {
 250                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 251                                      R100_cp_microcode[i][1]);
 252                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 253                                      R100_cp_microcode[i][0]);
 254                 }
 255         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 256                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 257                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 258                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 259                 DRM_INFO("Loading R200 Microcode\n");
 260                 for (i = 0; i < 256; i++) {
 261                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 262                                      R200_cp_microcode[i][1]);
 263                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 264                                      R200_cp_microcode[i][0]);
 265                 }
 266         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 267                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 268                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 269                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 270                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 271                 DRM_INFO("Loading R300 Microcode\n");
 272                 for (i = 0; i < 256; i++) {
 273                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 274                                      R300_cp_microcode[i][1]);
 275                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 276                                      R300_cp_microcode[i][0]);
 277                 }
 278         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 279                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 280                 DRM_INFO("Loading R400 Microcode\n");
 281                 for (i = 0; i < 256; i++) {
 282                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 283                                      R420_cp_microcode[i][1]);
 284                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 285                                      R420_cp_microcode[i][0]);
 286                 }
 287         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 288                 DRM_INFO("Loading RS690 Microcode\n");
 289                 for (i = 0; i < 256; i++) {
 290                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 291                                      RS690_cp_microcode[i][1]);
 292                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 293                                      RS690_cp_microcode[i][0]);
 294                 }
 295         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 296                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 297                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 298                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 299                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 300                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 301                 DRM_INFO("Loading R500 Microcode\n");
 302                 for (i = 0; i < 256; i++) {
 303                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 304                                      R520_cp_microcode[i][1]);
 305                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 306                                      R520_cp_microcode[i][0]);
 307                 }
 308         }
 309 }
 310
 311 /* Flush any pending commands to the CP.  This should only be used just
 312  * prior to a wait for idle, as it informs the engine that the command
 313  * stream is ending.
 314  */
 315 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 316 {
 317         DRM_DEBUG("\n");
 318 #if 0
 319         u32 tmp;
 320
 321         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 322         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 323 #endif
 324 }
 325
 326 /* Wait for the CP to go idle.
 327  */
 328 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 329 {
 330         RING_LOCALS;
 331         DRM_DEBUG("\n");
 332
 333         BEGIN_RING(6);
 334
 335         RADEON_PURGE_CACHE();
 336         RADEON_PURGE_ZCACHE();
 337         RADEON_WAIT_UNTIL_IDLE();
 338
 339         ADVANCE_RING();
 340         COMMIT_RING();
 341
 342         return radeon_do_wait_for_idle(dev_priv);
 343 }
 344
 345 /* Start the Command Processor.
 346  */
 347 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 348 {
 349         RING_LOCALS;
 350         DRM_DEBUG("\n");
 351
 352         radeon_do_wait_for_idle(dev_priv);
 353
 354         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 355
 356         dev_priv->cp_running = 1;
 357
 358         BEGIN_RING(6);
 359
 360         RADEON_PURGE_CACHE();
 361         RADEON_PURGE_ZCACHE();
 362         RADEON_WAIT_UNTIL_IDLE();
 363
 364         ADVANCE_RING();
 365         COMMIT_RING();
 366 }
 367
 368 /* Reset the Command Processor.  This will not flush any pending
 369  * commands, so you must wait for the CP command stream to complete
 370  * before calling this routine.
 371  */
 372 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 373 {
 374         u32 cur_read_ptr;
 375         DRM_DEBUG("\n");
 376
 377         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 378         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 379         SET_RING_HEAD(dev_priv, cur_read_ptr);
 380         dev_priv->ring.tail = cur_read_ptr;
 381 }
 382
 383 /* Stop the Command Processor.  This will not flush any pending
 384  * commands, so you must flush the command stream and wait for the CP
 385  * to go idle before calling this routine.
 386  */
 387 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 388 {
 389         DRM_DEBUG("\n");
 390
 391         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 392
 393         dev_priv->cp_running = 0;
 394 }
 395
 396 /* Reset the engine.  This will stop the CP if it is running.
 397  */
 398 static int radeon_do_engine_reset(struct drm_device * dev)
 399 {
 400         drm_radeon_private_t *dev_priv = dev->dev_private;
 401         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
 402         DRM_DEBUG("\n");
 403
 404         radeon_do_pixcache_flush(dev_priv);
 405
 406         if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
 407                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 408                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 409
 410                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 411                                                     RADEON_FORCEON_MCLKA |
 412                                                     RADEON_FORCEON_MCLKB |
 413                                                     RADEON_FORCEON_YCLKA |
 414                                                     RADEON_FORCEON_YCLKB |
 415                                                     RADEON_FORCEON_MC |
 416                                                     RADEON_FORCEON_AIC));
 417
 418                 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 419
 420                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 421                                                       RADEON_SOFT_RESET_CP |
 422                                                       RADEON_SOFT_RESET_HI |
 423                                                       RADEON_SOFT_RESET_SE |
 424                                                       RADEON_SOFT_RESET_RE |
 425                                                       RADEON_SOFT_RESET_PP |
 426                                                       RADEON_SOFT_RESET_E2 |
 427                                                       RADEON_SOFT_RESET_RB));
 428                 RADEON_READ(RADEON_RBBM_SOFT_RESET);
 429                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 430                                                       ~(RADEON_SOFT_RESET_CP |
 431                                                         RADEON_SOFT_RESET_HI |
 432                                                         RADEON_SOFT_RESET_SE |
 433                                                         RADEON_SOFT_RESET_RE |
 434                                                         RADEON_SOFT_RESET_PP |
 435                                                         RADEON_SOFT_RESET_E2 |
 436                                                         RADEON_SOFT_RESET_RB)));
 437                 RADEON_READ(RADEON_RBBM_SOFT_RESET);
 438
 439                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 440                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 441                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 442         }
 443
 444         /* Reset the CP ring */
 445         radeon_do_cp_reset(dev_priv);
 446
 447         /* The CP is no longer running after an engine reset */
 448         dev_priv->cp_running = 0;
 449
 450         /* Reset any pending vertex, indirect buffers */
 451         radeon_freelist_reset(dev);
 452
 453         return 0;
 454 }
 455
 456 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 457                                        drm_radeon_private_t * dev_priv)
 458 {
 459         u32 ring_start, cur_read_ptr;
 460         u32 tmp;
 461
 462         /* Initialize the memory controller. With new memory map, the fb location
 463          * is not changed, it should have been properly initialized already. Part
 464          * of the problem is that the code below is bogus, assuming the GART is
 465          * always appended to the fb which is not necessarily the case
 466          */
 467         if (!dev_priv->new_memmap)
 468                 radeon_write_fb_location(dev_priv,
 469                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 470                              | (dev_priv->fb_location >> 16));
 471
 472 #if __OS_HAS_AGP
 473         if (dev_priv->flags & RADEON_IS_AGP) {
 474                 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
 475                 radeon_write_agp_location(dev_priv,
 476                              (((dev_priv->gart_vm_start - 1 +
 477                                 dev_priv->gart_size) & 0xffff0000) |
 478                               (dev_priv->gart_vm_start >> 16)));
 479
 480                 ring_start = (dev_priv->cp_ring->offset
 481                               - dev->agp->base
 482                               + dev_priv->gart_vm_start);
 483         } else
 484 #endif
 485                 ring_start = (dev_priv->cp_ring->offset
 486                               - (unsigned long)dev->sg->virtual
 487                               + dev_priv->gart_vm_start);
 488
 489         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 490
 491         /* Set the write pointer delay */
 492         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 493
 494         /* Initialize the ring buffer's read and write pointers */
 495         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 496         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 497         SET_RING_HEAD(dev_priv, cur_read_ptr);
 498         dev_priv->ring.tail = cur_read_ptr;
 499
 500 #if __OS_HAS_AGP
 501         if (dev_priv->flags & RADEON_IS_AGP) {
 502                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 503                              dev_priv->ring_rptr->offset
 504                              - dev->agp->base + dev_priv->gart_vm_start);
 505         } else
 506 #endif
 507         {
 508                 struct drm_sg_mem *entry = dev->sg;
 509                 unsigned long tmp_ofs, page_ofs;
 510
 511                 tmp_ofs = dev_priv->ring_rptr->offset -
 512                                 (unsigned long)dev->sg->virtual;
 513                 page_ofs = tmp_ofs >> PAGE_SHIFT;
 514
 515                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
 516                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
 517                           (unsigned long)entry->busaddr[page_ofs],
 518                           entry->handle + tmp_ofs);
 519         }
 520
 521         /* Set ring buffer size */
 522 #ifdef __BIG_ENDIAN
 523         RADEON_WRITE(RADEON_CP_RB_CNTL,
 524                      RADEON_BUF_SWAP_32BIT |
 525                      (dev_priv->ring.fetch_size_l2ow << 18) |
 526                      (dev_priv->ring.rptr_update_l2qw << 8) |
 527                      dev_priv->ring.size_l2qw);
 528 #else
 529         RADEON_WRITE(RADEON_CP_RB_CNTL,
 530                      (dev_priv->ring.fetch_size_l2ow << 18) |
 531                      (dev_priv->ring.rptr_update_l2qw << 8) |
 532                      dev_priv->ring.size_l2qw);
 533 #endif
 534
 535         /* Start with assuming that writeback doesn't work */
 536         dev_priv->writeback_works = 0;
 537
 538         /* Initialize the scratch register pointer.  This will cause
 539          * the scratch register values to be written out to memory
 540          * whenever they are updated.
 541          *
 542          * We simply put this behind the ring read pointer, this works
 543          * with PCI GART as well as (whatever kind of) AGP GART
 544          */
 545         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 546                      + RADEON_SCRATCH_REG_OFFSET);
 547
 548         dev_priv->scratch = ((__volatile__ u32 *)
 549                              dev_priv->ring_rptr->handle +
 550                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 551
 552         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 553
 554         /* Turn on bus mastering */
 555         tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 556         RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 557
 558         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
 559         RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
 560
 561         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
 562         RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
 563                      dev_priv->sarea_priv->last_dispatch);
 564
 565         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
 566         RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
 567
 568         radeon_do_wait_for_idle(dev_priv);
 569
 570         /* Sync everything up */
 571         RADEON_WRITE(RADEON_ISYNC_CNTL,
 572                      (RADEON_ISYNC_ANY2D_IDLE3D |
 573                       RADEON_ISYNC_ANY3D_IDLE2D |
 574                       RADEON_ISYNC_WAIT_IDLEGUI |
 575                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 576
 577 }
 578
 579 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 580 {
 581         u32 tmp;
 582
 583         /* Writeback doesn't seem to work everywhere, test it here and possibly
 584          * enable it if it appears to work
 585          */
 586         DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
 587         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 588
 589         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 590                 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
 591                     0xdeadbeef)
 592                         break;
 593                 DRM_UDELAY(1);
 594         }
 595
 596         if (tmp < dev_priv->usec_timeout) {
 597                 dev_priv->writeback_works = 1;
 598                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 599         } else {
 600                 dev_priv->writeback_works = 0;
 601                 DRM_INFO("writeback test failed\n");
 602         }
 603         if (radeon_no_wb == 1) {
 604                 dev_priv->writeback_works = 0;
 605                 DRM_INFO("writeback forced off\n");
 606         }
 607
 608         if (!dev_priv->writeback_works) {
 609                 /* Disable writeback to avoid unnecessary bus master transfer */
 610                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
 611                              RADEON_RB_NO_UPDATE);
 612                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 613         }
 614 }
 615
 616 /* Enable or disable IGP GART on the chip */
 617 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 618 {
 619         u32 temp;
 620
 621         if (on) {
 622                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 623                           dev_priv->gart_vm_start,
 624                           (long)dev_priv->gart_info.bus_addr,
 625                           dev_priv->gart_size);
 626
 627                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 628                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 629                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 630                                                              RS690_BLOCK_GFX_D3_EN));
 631                 else
 632                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 633
 634                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 635                                                                RS480_VA_SIZE_32MB));
 636
 637                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 638                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 639                                                         RS480_TLB_ENABLE |
 640                                                         RS480_GTW_LAC_EN |
 641                                                         RS480_1LEVEL_GART));
 642
 643                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 644                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 645                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 646
 647                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 648                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 649                                                       RS480_REQ_TYPE_SNOOP_DIS));
 650
 651                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 652                         IGP_WRITE_MCIND(RS690_MC_AGP_BASE,
 653                                         (unsigned int)dev_priv->gart_vm_start);
 654                         IGP_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0);
 655                 } else {
 656                         RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
 657                         RADEON_WRITE(RS480_AGP_BASE_2, 0);
 658                 }
 659
 660                 dev_priv->gart_size = 32*1024*1024;
 661                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 662                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 663
 664                 radeon_write_agp_location(dev_priv, temp);
 665
 666                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 667                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 668                                                                RS480_VA_SIZE_32MB));
 669
 670                 do {
 671                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 672                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 673                                 break;
 674                         DRM_UDELAY(1);
 675                 } while (1);
 676
 677                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 678                                 RS480_GART_CACHE_INVALIDATE);
 679
 680                 do {
 681                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 682                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 683                                 break;
 684                         DRM_UDELAY(1);
 685                 } while (1);
 686
 687                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 688         } else {
 689                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 690         }
 691 }
 692
 693 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 694 {
 695         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 696         if (on) {
 697
 698                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
 699                           dev_priv->gart_vm_start,
 700                           (long)dev_priv->gart_info.bus_addr,
 701                           dev_priv->gart_size);
 702                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
 703                                   dev_priv->gart_vm_start);
 704                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
 705                                   dev_priv->gart_info.bus_addr);
 706                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
 707                                   dev_priv->gart_vm_start);
 708                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
 709                                   dev_priv->gart_vm_start +
 710                                   dev_priv->gart_size - 1);
 711
 712                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
 713
 714                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 715                                   RADEON_PCIE_TX_GART_EN);
 716         } else {
 717                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 718                                   tmp & ~RADEON_PCIE_TX_GART_EN);
 719         }
 720 }
 721
 722 /* Enable or disable PCI GART on the chip */
 723 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 724 {
 725         u32 tmp;
 726
 727         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 728             (dev_priv->flags & RADEON_IS_IGPGART)) {
 729                 radeon_set_igpgart(dev_priv, on);
 730                 return;
 731         }
 732
 733         if (dev_priv->flags & RADEON_IS_PCIE) {
 734                 radeon_set_pciegart(dev_priv, on);
 735                 return;
 736         }
 737
 738         tmp = RADEON_READ(RADEON_AIC_CNTL);
 739
 740         if (on) {
 741                 RADEON_WRITE(RADEON_AIC_CNTL,
 742                              tmp | RADEON_PCIGART_TRANSLATE_EN);
 743
 744                 /* set PCI GART page-table base address
 745                  */
 746                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
 747
 748                 /* set address range for PCI address translate
 749                  */
 750                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
 751                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
 752                              + dev_priv->gart_size - 1);
 753
 754                 /* Turn off AGP aperture -- is this required for PCI GART?
 755                  */
 756                 radeon_write_agp_location(dev_priv, 0xffffffc0);
 757                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
 758         } else {
 759                 RADEON_WRITE(RADEON_AIC_CNTL,
 760                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 761         }
 762 }
 763
 764 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
 765 {
 766         drm_radeon_private_t *dev_priv = dev->dev_private;
 767
 768         DRM_DEBUG("\n");
 769
 770         /* if we require new memory map but we don't have it fail */
 771         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
 772                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
 773                 radeon_do_cleanup_cp(dev);
 774                 return -EINVAL;
 775         }
 776
 777         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
 778                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
 779                 dev_priv->flags &= ~RADEON_IS_AGP;
 780         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
 781                    && !init->is_pci) {
 782                 DRM_DEBUG("Restoring AGP flag\n");
 783                 dev_priv->flags |= RADEON_IS_AGP;
 784         }
 785
 786         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
 787                 DRM_ERROR("PCI GART memory not allocated!\n");
 788                 radeon_do_cleanup_cp(dev);
 789                 return -EINVAL;
 790         }
 791
 792         dev_priv->usec_timeout = init->usec_timeout;
 793         if (dev_priv->usec_timeout < 1 ||
 794             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
 795                 DRM_DEBUG("TIMEOUT problem!\n");
 796                 radeon_do_cleanup_cp(dev);
 797                 return -EINVAL;
 798         }
 799
 800         /* Enable vblank on CRTC1 for older X servers
 801          */
 802         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
 803
 804         switch(init->func) {
 805         case RADEON_INIT_R200_CP:
 806                 dev_priv->microcode_version = UCODE_R200;
 807                 break;
 808         case RADEON_INIT_R300_CP:
 809                 dev_priv->microcode_version = UCODE_R300;
 810                 break;
 811         default:
 812                 dev_priv->microcode_version = UCODE_R100;
 813         }
 814
 815         dev_priv->do_boxes = 0;
 816         dev_priv->cp_mode = init->cp_mode;
 817
 818         /* We don't support anything other than bus-mastering ring mode,
 819          * but the ring can be in either AGP or PCI space for the ring
 820          * read pointer.
 821          */
 822         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
 823             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
 824                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
 825                 radeon_do_cleanup_cp(dev);
 826                 return -EINVAL;
 827         }
 828
 829         switch (init->fb_bpp) {
 830         case 16:
 831                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
 832                 break;
 833         case 32:
 834         default:
 835                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
 836                 break;
 837         }
 838         dev_priv->front_offset = init->front_offset;
 839         dev_priv->front_pitch = init->front_pitch;
 840         dev_priv->back_offset = init->back_offset;
 841         dev_priv->back_pitch = init->back_pitch;
 842
 843         switch (init->depth_bpp) {
 844         case 16:
 845                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
 846                 break;
 847         case 32:
 848         default:
 849                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
 850                 break;
 851         }
 852         dev_priv->depth_offset = init->depth_offset;
 853         dev_priv->depth_pitch = init->depth_pitch;
 854
 855         /* Hardware state for depth clears.  Remove this if/when we no
 856          * longer clear the depth buffer with a 3D rectangle.  Hard-code
 857          * all values to prevent unwanted 3D state from slipping through
 858          * and screwing with the clear operation.
 859          */
 860         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
 861                                            (dev_priv->color_fmt << 10) |
 862                                            (dev_priv->microcode_version ==
 863                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
 864
 865         dev_priv->depth_clear.rb3d_zstencilcntl =
 866             (dev_priv->depth_fmt |
 867              RADEON_Z_TEST_ALWAYS |
 868              RADEON_STENCIL_TEST_ALWAYS |
 869              RADEON_STENCIL_S_FAIL_REPLACE |
 870              RADEON_STENCIL_ZPASS_REPLACE |
 871              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
 872
 873         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
 874                                          RADEON_BFACE_SOLID |
 875                                          RADEON_FFACE_SOLID |
 876                                          RADEON_FLAT_SHADE_VTX_LAST |
 877                                          RADEON_DIFFUSE_SHADE_FLAT |
 878                                          RADEON_ALPHA_SHADE_FLAT |
 879                                          RADEON_SPECULAR_SHADE_FLAT |
 880                                          RADEON_FOG_SHADE_FLAT |
 881                                          RADEON_VTX_PIX_CENTER_OGL |
 882                                          RADEON_ROUND_MODE_TRUNC |
 883                                          RADEON_ROUND_PREC_8TH_PIX);
 884
 885
 886         dev_priv->ring_offset = init->ring_offset;
 887         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
 888         dev_priv->buffers_offset = init->buffers_offset;
 889         dev_priv->gart_textures_offset = init->gart_textures_offset;
 890
 891         dev_priv->sarea = drm_getsarea(dev);
 892         if (!dev_priv->sarea) {
 893                 DRM_ERROR("could not find sarea!\n");
 894                 radeon_do_cleanup_cp(dev);
 895                 return -EINVAL;
 896         }
 897
 898         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
 899         if (!dev_priv->cp_ring) {
 900                 DRM_ERROR("could not find cp ring region!\n");
 901                 radeon_do_cleanup_cp(dev);
 902                 return -EINVAL;
 903         }
 904         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
 905         if (!dev_priv->ring_rptr) {
 906                 DRM_ERROR("could not find ring read pointer!\n");
 907                 radeon_do_cleanup_cp(dev);
 908                 return -EINVAL;
 909         }
 910         dev->agp_buffer_token = init->buffers_offset;
 911         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
 912         if (!dev->agp_buffer_map) {
 913                 DRM_ERROR("could not find dma buffer region!\n");
 914                 radeon_do_cleanup_cp(dev);
 915                 return -EINVAL;
 916         }
 917
 918         if (init->gart_textures_offset) {
 919                 dev_priv->gart_textures =
 920                     drm_core_findmap(dev, init->gart_textures_offset);
 921                 if (!dev_priv->gart_textures) {
 922                         DRM_ERROR("could not find GART texture region!\n");
 923                         radeon_do_cleanup_cp(dev);
 924                         return -EINVAL;
 925                 }
 926         }
 927
 928         dev_priv->sarea_priv =
 929             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
 930                                     init->sarea_priv_offset);
 931
 932 #if __OS_HAS_AGP
 933         if (dev_priv->flags & RADEON_IS_AGP) {
 934                 drm_core_ioremap(dev_priv->cp_ring, dev);
 935                 drm_core_ioremap(dev_priv->ring_rptr, dev);
 936                 drm_core_ioremap(dev->agp_buffer_map, dev);
 937                 if (!dev_priv->cp_ring->handle ||
 938                     !dev_priv->ring_rptr->handle ||
 939                     !dev->agp_buffer_map->handle) {
 940                         DRM_ERROR("could not find ioremap agp regions!\n");
 941                         radeon_do_cleanup_cp(dev);
 942                         return -EINVAL;
 943                 }
 944         } else
 945 #endif
 946         {
 947                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
 948                 dev_priv->ring_rptr->handle =
 949                     (void *)dev_priv->ring_rptr->offset;
 950                 dev->agp_buffer_map->handle =
 951                     (void *)dev->agp_buffer_map->offset;
 952
 953                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
 954                           dev_priv->cp_ring->handle);
 955                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
 956                           dev_priv->ring_rptr->handle);
 957                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
 958                           dev->agp_buffer_map->handle);
 959         }
 960
 961         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
 962         dev_priv->fb_size =
 963                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
 964                 - dev_priv->fb_location;
 965
 966         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
 967                                         ((dev_priv->front_offset
 968                                           + dev_priv->fb_location) >> 10));
 969
 970         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
 971                                        ((dev_priv->back_offset
 972                                          + dev_priv->fb_location) >> 10));
 973
 974         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
 975                                         ((dev_priv->depth_offset
 976                                           + dev_priv->fb_location) >> 10));
 977
 978         dev_priv->gart_size = init->gart_size;
 979
 980         /* New let's set the memory map ... */
 981         if (dev_priv->new_memmap) {
 982                 u32 base = 0;
 983
 984                 DRM_INFO("Setting GART location based on new memory map\n");
 985
 986                 /* If using AGP, try to locate the AGP aperture at the same
 987                  * location in the card and on the bus, though we have to
 988                  * align it down.
 989                  */
 990 #if __OS_HAS_AGP
 991                 if (dev_priv->flags & RADEON_IS_AGP) {
 992                         base = dev->agp->base;
 993                         /* Check if valid */
 994                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
 995                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
 996                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
 997                                          dev->agp->base);
 998                                 base = 0;
 999                         }
1000                 }
1001 #endif
1002                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1003                 if (base == 0) {
1004                         base = dev_priv->fb_location + dev_priv->fb_size;
1005                         if (base < dev_priv->fb_location ||
1006                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1007                                 base = dev_priv->fb_location
1008                                         - dev_priv->gart_size;
1009                 }
1010                 dev_priv->gart_vm_start = base & 0xffc00000u;
1011                 if (dev_priv->gart_vm_start != base)
1012                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1013                                  base, dev_priv->gart_vm_start);
1014         } else {
1015                 DRM_INFO("Setting GART location based on old memory map\n");
1016                 dev_priv->gart_vm_start = dev_priv->fb_location +
1017                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1018         }
1019
1020 #if __OS_HAS_AGP
1021         if (dev_priv->flags & RADEON_IS_AGP)
1022                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1023                                                  - dev->agp->base
1024                                                  + dev_priv->gart_vm_start);
1025         else
1026 #endif
1027                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1028                                         - (unsigned long)dev->sg->virtual
1029                                         + dev_priv->gart_vm_start);
1030
1031         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1032         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1033         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1034                   dev_priv->gart_buffers_offset);
1035
1036         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1037         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1038                               + init->ring_size / sizeof(u32));
1039         dev_priv->ring.size = init->ring_size;
1040         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1041
1042         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1043         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1044
1045         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1046         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1047         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1048
1049         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1050
1051 #if __OS_HAS_AGP
1052         if (dev_priv->flags & RADEON_IS_AGP) {
1053                 /* Turn off PCI GART */
1054                 radeon_set_pcigart(dev_priv, 0);
1055         } else
1056 #endif
1057         {
1058                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1059                 /* if we have an offset set from userspace */
1060                 if (dev_priv->pcigart_offset_set) {
1061                         dev_priv->gart_info.bus_addr =
1062                             dev_priv->pcigart_offset + dev_priv->fb_location;
1063                         dev_priv->gart_info.mapping.offset =
1064                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1065                         dev_priv->gart_info.mapping.size =
1066                             dev_priv->gart_info.table_size;
1067
1068                         drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1069                         dev_priv->gart_info.addr =
1070                             dev_priv->gart_info.mapping.handle;
1071
1072                         if (dev_priv->flags & RADEON_IS_PCIE)
1073                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1074                         else
1075                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1076                         dev_priv->gart_info.gart_table_location =
1077                             DRM_ATI_GART_FB;
1078
1079                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1080                                   dev_priv->gart_info.addr,
1081                                   dev_priv->pcigart_offset);
1082                 } else {
1083                         if (dev_priv->flags & RADEON_IS_IGPGART)
1084                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1085                         else
1086                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1087                         dev_priv->gart_info.gart_table_location =
1088                             DRM_ATI_GART_MAIN;
1089                         dev_priv->gart_info.addr = NULL;
1090                         dev_priv->gart_info.bus_addr = 0;
1091                         if (dev_priv->flags & RADEON_IS_PCIE) {
1092                                 DRM_ERROR
1093                                     ("Cannot use PCI Express without GART in FB memory\n");
1094                                 radeon_do_cleanup_cp(dev);
1095                                 return -EINVAL;
1096                         }
1097                 }
1098
1099                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1100                         DRM_ERROR("failed to init PCI GART!\n");
1101                         radeon_do_cleanup_cp(dev);
1102                         return -ENOMEM;
1103                 }
1104
1105                 /* Turn on PCI GART */
1106                 radeon_set_pcigart(dev_priv, 1);
1107         }
1108
1109         radeon_cp_load_microcode(dev_priv);
1110         radeon_cp_init_ring_buffer(dev, dev_priv);
1111
1112         dev_priv->last_buf = 0;
1113
1114         radeon_do_engine_reset(dev);
1115         radeon_test_writeback(dev_priv);
1116
1117         return 0;
1118 }
1119
1120 static int radeon_do_cleanup_cp(struct drm_device * dev)
1121 {
1122         drm_radeon_private_t *dev_priv = dev->dev_private;
1123         DRM_DEBUG("\n");
1124
1125         /* Make sure interrupts are disabled here because the uninstall ioctl
1126          * may not have been called from userspace and after dev_private
1127          * is freed, it's too late.
1128          */
1129         if (dev->irq_enabled)
1130                 drm_irq_uninstall(dev);
1131
1132 #if __OS_HAS_AGP
1133         if (dev_priv->flags & RADEON_IS_AGP) {
1134                 if (dev_priv->cp_ring != NULL) {
1135                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1136                         dev_priv->cp_ring = NULL;
1137                 }
1138                 if (dev_priv->ring_rptr != NULL) {
1139                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1140                         dev_priv->ring_rptr = NULL;
1141                 }
1142                 if (dev->agp_buffer_map != NULL) {
1143                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1144                         dev->agp_buffer_map = NULL;
1145                 }
1146         } else
1147 #endif
1148         {
1149
1150                 if (dev_priv->gart_info.bus_addr) {
1151                         /* Turn off PCI GART */
1152                         radeon_set_pcigart(dev_priv, 0);
1153                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1154                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1155                 }
1156
1157                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1158                 {
1159                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1160                         dev_priv->gart_info.addr = 0;
1161                 }
1162         }
1163         /* only clear to the start of flags */
1164         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1165
1166         return 0;
1167 }
1168
1169 /* This code will reinit the Radeon CP hardware after a resume from disc.
1170  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1171  * here we make sure that all Radeon hardware initialisation is re-done without
1172  * affecting running applications.
1173  *
1174  * Charl P. Botha <http://cpbotha.net>
1175  */
1176 static int radeon_do_resume_cp(struct drm_device * dev)
1177 {
1178         drm_radeon_private_t *dev_priv = dev->dev_private;
1179
1180         if (!dev_priv) {
1181                 DRM_ERROR("Called with no initialization\n");
1182                 return -EINVAL;
1183         }
1184
1185         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1186
1187 #if __OS_HAS_AGP
1188         if (dev_priv->flags & RADEON_IS_AGP) {
1189                 /* Turn off PCI GART */
1190                 radeon_set_pcigart(dev_priv, 0);
1191         } else
1192 #endif
1193         {
1194                 /* Turn on PCI GART */
1195                 radeon_set_pcigart(dev_priv, 1);
1196         }
1197
1198         radeon_cp_load_microcode(dev_priv);
1199         radeon_cp_init_ring_buffer(dev, dev_priv);
1200
1201         radeon_do_engine_reset(dev);
1202
1203         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1204
1205         return 0;
1206 }
1207
1208 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1209 {
1210         drm_radeon_init_t *init = data;
1211
1212         LOCK_TEST_WITH_RETURN(dev, file_priv);
1213
1214         if (init->func == RADEON_INIT_R300_CP)
1215                 r300_init_reg_flags(dev);
1216
1217         switch (init->func) {
1218         case RADEON_INIT_CP:
1219         case RADEON_INIT_R200_CP:
1220         case RADEON_INIT_R300_CP:
1221                 return radeon_do_init_cp(dev, init);
1222         case RADEON_CLEANUP_CP:
1223                 return radeon_do_cleanup_cp(dev);
1224         }
1225
1226         return -EINVAL;
1227 }
1228
1229 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1230 {
1231         drm_radeon_private_t *dev_priv = dev->dev_private;
1232         DRM_DEBUG("\n");
1233
1234         LOCK_TEST_WITH_RETURN(dev, file_priv);
1235
1236         if (dev_priv->cp_running) {
1237                 DRM_DEBUG("while CP running\n");
1238                 return 0;
1239         }
1240         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1241                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1242                           dev_priv->cp_mode);
1243                 return 0;
1244         }
1245
1246         radeon_do_cp_start(dev_priv);
1247
1248         return 0;
1249 }
1250
1251 /* Stop the CP.  The engine must have been idled before calling this
1252  * routine.
1253  */
1254 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1255 {
1256         drm_radeon_private_t *dev_priv = dev->dev_private;
1257         drm_radeon_cp_stop_t *stop = data;
1258         int ret;
1259         DRM_DEBUG("\n");
1260
1261         LOCK_TEST_WITH_RETURN(dev, file_priv);
1262
1263         if (!dev_priv->cp_running)
1264                 return 0;
1265
1266         /* Flush any pending CP commands.  This ensures any outstanding
1267          * commands are exectuted by the engine before we turn it off.
1268          */
1269         if (stop->flush) {
1270                 radeon_do_cp_flush(dev_priv);
1271         }
1272
1273         /* If we fail to make the engine go idle, we return an error
1274          * code so that the DRM ioctl wrapper can try again.
1275          */
1276         if (stop->idle) {
1277                 ret = radeon_do_cp_idle(dev_priv);
1278                 if (ret)
1279                         return ret;
1280         }
1281
1282         /* Finally, we can turn off the CP.  If the engine isn't idle,
1283          * we will get some dropped triangles as they won't be fully
1284          * rendered before the CP is shut down.
1285          */
1286         radeon_do_cp_stop(dev_priv);
1287
1288         /* Reset the engine */
1289         radeon_do_engine_reset(dev);
1290
1291         return 0;
1292 }
1293
1294 void radeon_do_release(struct drm_device * dev)
1295 {
1296         drm_radeon_private_t *dev_priv = dev->dev_private;
1297         int i, ret;
1298
1299         if (dev_priv) {
1300                 if (dev_priv->cp_running) {
1301                         /* Stop the cp */
1302                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1303                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1304 #ifdef __linux__
1305                                 schedule();
1306 #else
1307                                 tsleep(&ret, PZERO, "rdnrel", 1);
1308 #endif
1309                         }
1310                         radeon_do_cp_stop(dev_priv);
1311                         radeon_do_engine_reset(dev);
1312                 }
1313
1314                 /* Disable *all* interrupts */
1315                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1316                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1317
1318                 if (dev_priv->mmio) {   /* remove all surfaces */
1319                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1320                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1321                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1322                                              16 * i, 0);
1323                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1324                                              16 * i, 0);
1325                         }
1326                 }
1327
1328                 /* Free memory heap structures */
1329                 radeon_mem_takedown(&(dev_priv->gart_heap));
1330                 radeon_mem_takedown(&(dev_priv->fb_heap));
1331
1332                 /* deallocate kernel resources */
1333                 radeon_do_cleanup_cp(dev);
1334         }
1335 }
1336
1337 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1338  */
1339 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1340 {
1341         drm_radeon_private_t *dev_priv = dev->dev_private;
1342         DRM_DEBUG("\n");
1343
1344         LOCK_TEST_WITH_RETURN(dev, file_priv);
1345
1346         if (!dev_priv) {
1347                 DRM_DEBUG("called before init done\n");
1348                 return -EINVAL;
1349         }
1350
1351         radeon_do_cp_reset(dev_priv);
1352
1353         /* The CP is no longer running after an engine reset */
1354         dev_priv->cp_running = 0;
1355
1356         return 0;
1357 }
1358
1359 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1360 {
1361         drm_radeon_private_t *dev_priv = dev->dev_private;
1362         DRM_DEBUG("\n");
1363
1364         LOCK_TEST_WITH_RETURN(dev, file_priv);
1365
1366         return radeon_do_cp_idle(dev_priv);
1367 }
1368
1369 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1370  */
1371 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1372 {
1373
1374         return radeon_do_resume_cp(dev);
1375 }
1376
1377 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1378 {
1379         DRM_DEBUG("\n");
1380
1381         LOCK_TEST_WITH_RETURN(dev, file_priv);
1382
1383         return radeon_do_engine_reset(dev);
1384 }
1385
1386 /* ================================================================
1387  * Fullscreen mode
1388  */
1389
1390 /* KW: Deprecated to say the least:
1391  */
1392 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1393 {
1394         return 0;
1395 }
1396
1397 /* ================================================================
1398  * Freelist management
1399  */
1400
1401 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1402  *   bufs until freelist code is used.  Note this hides a problem with
1403  *   the scratch register * (used to keep track of last buffer
1404  *   completed) being written to before * the last buffer has actually
1405  *   completed rendering.
1406  *
1407  * KW:  It's also a good way to find free buffers quickly.
1408  *
1409  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1410  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1411  * we essentially have to do this, else old clients will break.
1412  *
1413  * However, it does leave open a potential deadlock where all the
1414  * buffers are held by other clients, which can't release them because
1415  * they can't get the lock.
1416  */
1417
1418 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1419 {
1420         struct drm_device_dma *dma = dev->dma;
1421         drm_radeon_private_t *dev_priv = dev->dev_private;
1422         drm_radeon_buf_priv_t *buf_priv;
1423         struct drm_buf *buf;
1424         int i, t;
1425         int start;
1426
1427         if (++dev_priv->last_buf >= dma->buf_count)
1428                 dev_priv->last_buf = 0;
1429
1430         start = dev_priv->last_buf;
1431
1432         for (t = 0; t < dev_priv->usec_timeout; t++) {
1433                 u32 done_age = GET_SCRATCH(1);
1434                 DRM_DEBUG("done_age = %d\n", done_age);
1435                 for (i = start; i < dma->buf_count; i++) {
1436                         buf = dma->buflist[i];
1437                         buf_priv = buf->dev_private;
1438                         if (buf->file_priv == NULL || (buf->pending &&
1439                                                        buf_priv->age <=
1440                                                        done_age)) {
1441                                 dev_priv->stats.requested_bufs++;
1442                                 buf->pending = 0;
1443                                 return buf;
1444                         }
1445                         start = 0;
1446                 }
1447
1448                 if (t) {
1449                         DRM_UDELAY(1);
1450                         dev_priv->stats.freelist_loops++;
1451                 }
1452         }
1453
1454         DRM_DEBUG("returning NULL!\n");
1455         return NULL;
1456 }
1457
1458 #if 0
1459 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1460 {
1461         struct drm_device_dma *dma = dev->dma;
1462         drm_radeon_private_t *dev_priv = dev->dev_private;
1463         drm_radeon_buf_priv_t *buf_priv;
1464         struct drm_buf *buf;
1465         int i, t;
1466         int start;
1467         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1468
1469         if (++dev_priv->last_buf >= dma->buf_count)
1470                 dev_priv->last_buf = 0;
1471
1472         start = dev_priv->last_buf;
1473         dev_priv->stats.freelist_loops++;
1474
1475         for (t = 0; t < 2; t++) {
1476                 for (i = start; i < dma->buf_count; i++) {
1477                         buf = dma->buflist[i];
1478                         buf_priv = buf->dev_private;
1479                         if (buf->file_priv == 0 || (buf->pending &&
1480                                                     buf_priv->age <=
1481                                                     done_age)) {
1482                                 dev_priv->stats.requested_bufs++;
1483                                 buf->pending = 0;
1484                                 return buf;
1485                         }
1486                 }
1487                 start = 0;
1488         }
1489
1490         return NULL;
1491 }
1492 #endif
1493
1494 void radeon_freelist_reset(struct drm_device * dev)
1495 {
1496         struct drm_device_dma *dma = dev->dma;
1497         drm_radeon_private_t *dev_priv = dev->dev_private;
1498         int i;
1499
1500         dev_priv->last_buf = 0;
1501         for (i = 0; i < dma->buf_count; i++) {
1502                 struct drm_buf *buf = dma->buflist[i];
1503                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1504                 buf_priv->age = 0;
1505         }
1506 }
1507
1508 /* ================================================================
1509  * CP command submission
1510  */
1511
1512 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1513 {
1514         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1515         int i;
1516         u32 last_head = GET_RING_HEAD(dev_priv);
1517
1518         for (i = 0; i < dev_priv->usec_timeout; i++) {
1519                 u32 head = GET_RING_HEAD(dev_priv);
1520
1521                 ring->space = (head - ring->tail) * sizeof(u32);
1522                 if (ring->space <= 0)
1523                         ring->space += ring->size;
1524                 if (ring->space > n)
1525                         return 0;
1526
1527                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1528
1529                 if (head != last_head)
1530                         i = 0;
1531                 last_head = head;
1532
1533                 DRM_UDELAY(1);
1534         }
1535
1536         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1537 #if RADEON_FIFO_DEBUG
1538         radeon_status(dev_priv);
1539         DRM_ERROR("failed!\n");
1540 #endif
1541         return -EBUSY;
1542 }
1543
1544 static int radeon_cp_get_buffers(struct drm_device *dev,
1545                                  struct drm_file *file_priv,
1546                                  struct drm_dma * d)
1547 {
1548         int i;
1549         struct drm_buf *buf;
1550
1551         for (i = d->granted_count; i < d->request_count; i++) {
1552                 buf = radeon_freelist_get(dev);
1553                 if (!buf)
1554                         return -EBUSY;  /* NOTE: broken client */
1555
1556                 buf->file_priv = file_priv;
1557
1558                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1559                                      sizeof(buf->idx)))
1560                         return -EFAULT;
1561                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1562                                      sizeof(buf->total)))
1563                         return -EFAULT;
1564
1565                 d->granted_count++;
1566         }
1567         return 0;
1568 }
1569
1570 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1571 {
1572         struct drm_device_dma *dma = dev->dma;
1573         int ret = 0;
1574         struct drm_dma *d = data;
1575
1576         LOCK_TEST_WITH_RETURN(dev, file_priv);
1577
1578         /* Please don't send us buffers.
1579          */
1580         if (d->send_count != 0) {
1581                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1582                           DRM_CURRENTPID, d->send_count);
1583                 return -EINVAL;
1584         }
1585
1586         /* We'll send you buffers.
1587          */
1588         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1589                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1590                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1591                 return -EINVAL;
1592         }
1593
1594         d->granted_count = 0;
1595
1596         if (d->request_count) {
1597                 ret = radeon_cp_get_buffers(dev, file_priv, d);
1598         }
1599
1600         return ret;
1601 }
1602
1603 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1604 {
1605         drm_radeon_private_t *dev_priv;
1606         int ret = 0;
1607
1608         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1609         if (dev_priv == NULL)
1610                 return -ENOMEM;
1611
1612         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1613         dev->dev_private = (void *)dev_priv;
1614         dev_priv->flags = flags;
1615
1616         switch (flags & RADEON_FAMILY_MASK) {
1617         case CHIP_R100:
1618         case CHIP_RV200:
1619         case CHIP_R200:
1620         case CHIP_R300:
1621         case CHIP_R350:
1622         case CHIP_R420:
1623         case CHIP_RV410:
1624         case CHIP_RV515:
1625         case CHIP_R520:
1626         case CHIP_RV570:
1627         case CHIP_R580:
1628                 dev_priv->flags |= RADEON_HAS_HIERZ;
1629                 break;
1630         default:
1631                 /* all other chips have no hierarchical z buffer */
1632                 break;
1633         }
1634
1635         if (drm_device_is_agp(dev))
1636                 dev_priv->flags |= RADEON_IS_AGP;
1637         else if (drm_device_is_pcie(dev))
1638                 dev_priv->flags |= RADEON_IS_PCIE;
1639         else
1640                 dev_priv->flags |= RADEON_IS_PCI;
1641
1642         DRM_DEBUG("%s card detected\n",
1643                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1644         return ret;
1645 }
1646
1647 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1648  * have to find them.
1649  */
1650 int radeon_driver_firstopen(struct drm_device *dev)
1651 {
1652         int ret;
1653         drm_local_map_t *map;
1654         drm_radeon_private_t *dev_priv = dev->dev_private;
1655
1656         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1657
1658         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1659                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1660                          _DRM_READ_ONLY, &dev_priv->mmio);
1661         if (ret != 0)
1662                 return ret;
1663
1664         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1665         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1666                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1667                          _DRM_WRITE_COMBINING, &map);
1668         if (ret != 0)
1669                 return ret;
1670
1671         return 0;
1672 }
1673
1674 int radeon_driver_unload(struct drm_device *dev)
1675 {
1676         drm_radeon_private_t *dev_priv = dev->dev_private;
1677
1678         DRM_DEBUG("\n");
1679         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1680
1681         dev->dev_private = NULL;
1682         return 0;
1683 }