1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
34 #include "radeon_drm.h"
35 #include "radeon_drv.h"
38 #include "radeon_microcode.h"
40 #define RADEON_FIFO_DEBUG 0
42 static int radeon_do_cleanup_cp(struct drm_device * dev);
44 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
47 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
48 ret = RADEON_READ(R520_MC_IND_DATA);
49 RADEON_WRITE(R520_MC_IND_INDEX, 0);
53 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
56 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
57 ret = RADEON_READ(RS480_NB_MC_DATA);
58 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
62 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
65 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
66 ret = RADEON_READ(RS690_MC_DATA);
67 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
71 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
73 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
74 return RS690_READ_MCIND(dev_priv, addr);
76 return RS480_READ_MCIND(dev_priv, addr);
79 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
82 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
83 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
84 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
85 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
86 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
87 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
89 return RADEON_READ(RADEON_MC_FB_LOCATION);
92 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
94 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
95 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
96 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
97 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
98 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
99 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
101 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
104 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
106 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
107 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
108 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
109 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
110 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
111 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
113 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
116 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
118 drm_radeon_private_t *dev_priv = dev->dev_private;
120 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
121 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
124 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
126 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
127 return RADEON_READ(RADEON_PCIE_DATA);
130 #if RADEON_FIFO_DEBUG
131 static void radeon_status(drm_radeon_private_t * dev_priv)
133 printk("%s:\n", __func__);
134 printk("RBBM_STATUS = 0x%08x\n",
135 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
136 printk("CP_RB_RTPR = 0x%08x\n",
137 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
138 printk("CP_RB_WTPR = 0x%08x\n",
139 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
140 printk("AIC_CNTL = 0x%08x\n",
141 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
142 printk("AIC_STAT = 0x%08x\n",
143 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
144 printk("AIC_PT_BASE = 0x%08x\n",
145 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
146 printk("TLB_ADDR = 0x%08x\n",
147 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
148 printk("TLB_DATA = 0x%08x\n",
149 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
153 /* ================================================================
154 * Engine, FIFO control
157 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
162 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
164 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
165 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
166 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
167 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
169 for (i = 0; i < dev_priv->usec_timeout; i++) {
170 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
171 & RADEON_RB3D_DC_BUSY)) {
178 tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT);
179 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
180 RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp);
183 tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
184 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
185 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
187 for (i = 0; i < dev_priv->usec_timeout; i++) {
188 if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
189 & RADEON_RB3D_DC_BUSY)) {
196 #if RADEON_FIFO_DEBUG
197 DRM_ERROR("failed!\n");
198 radeon_status(dev_priv);
203 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
207 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
209 for (i = 0; i < dev_priv->usec_timeout; i++) {
210 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
211 & RADEON_RBBM_FIFOCNT_MASK);
212 if (slots >= entries)
217 #if RADEON_FIFO_DEBUG
218 DRM_ERROR("failed!\n");
219 radeon_status(dev_priv);
224 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
228 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
230 ret = radeon_do_wait_for_fifo(dev_priv, 64);
234 for (i = 0; i < dev_priv->usec_timeout; i++) {
235 if (!(RADEON_READ(RADEON_RBBM_STATUS)
236 & RADEON_RBBM_ACTIVE)) {
237 radeon_do_pixcache_flush(dev_priv);
243 #if RADEON_FIFO_DEBUG
244 DRM_ERROR("failed!\n");
245 radeon_status(dev_priv);
250 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
252 uint32_t gb_tile_config, gb_pipe_sel = 0;
254 /* RS4xx/RS6xx/R4xx/R5xx */
255 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
256 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
257 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
260 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
261 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
262 dev_priv->num_gb_pipes = 2;
265 dev_priv->num_gb_pipes = 1;
268 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
270 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
272 switch (dev_priv->num_gb_pipes) {
273 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
274 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
275 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
277 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
280 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
281 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
282 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
284 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
285 radeon_do_wait_for_idle(dev_priv);
286 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
287 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
288 R300_DC_AUTOFLUSH_ENABLE |
289 R300_DC_DC_DISABLE_IGNORE_PE));
294 /* ================================================================
295 * CP control, initialization
298 /* Load the microcode for the CP */
299 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
304 radeon_do_wait_for_idle(dev_priv);
306 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
307 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
308 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
309 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
310 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
311 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
312 DRM_INFO("Loading R100 Microcode\n");
313 for (i = 0; i < 256; i++) {
314 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
315 R100_cp_microcode[i][1]);
316 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
317 R100_cp_microcode[i][0]);
319 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
320 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
321 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
322 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
323 DRM_INFO("Loading R200 Microcode\n");
324 for (i = 0; i < 256; i++) {
325 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
326 R200_cp_microcode[i][1]);
327 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
328 R200_cp_microcode[i][0]);
330 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
331 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
332 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
333 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
334 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
335 DRM_INFO("Loading R300 Microcode\n");
336 for (i = 0; i < 256; i++) {
337 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
338 R300_cp_microcode[i][1]);
339 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
340 R300_cp_microcode[i][0]);
342 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
343 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
344 DRM_INFO("Loading R400 Microcode\n");
345 for (i = 0; i < 256; i++) {
346 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
347 R420_cp_microcode[i][1]);
348 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
349 R420_cp_microcode[i][0]);
351 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
352 DRM_INFO("Loading RS690 Microcode\n");
353 for (i = 0; i < 256; i++) {
354 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
355 RS690_cp_microcode[i][1]);
356 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
357 RS690_cp_microcode[i][0]);
359 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
360 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
361 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
362 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
363 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
364 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
365 DRM_INFO("Loading R500 Microcode\n");
366 for (i = 0; i < 256; i++) {
367 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
368 R520_cp_microcode[i][1]);
369 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
370 R520_cp_microcode[i][0]);
375 /* Flush any pending commands to the CP. This should only be used just
376 * prior to a wait for idle, as it informs the engine that the command
379 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
385 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
386 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
390 /* Wait for the CP to go idle.
392 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
399 RADEON_PURGE_CACHE();
400 RADEON_PURGE_ZCACHE();
401 RADEON_WAIT_UNTIL_IDLE();
406 return radeon_do_wait_for_idle(dev_priv);
409 /* Start the Command Processor.
411 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
416 radeon_do_wait_for_idle(dev_priv);
418 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
420 dev_priv->cp_running = 1;
424 RADEON_PURGE_CACHE();
425 RADEON_PURGE_ZCACHE();
426 RADEON_WAIT_UNTIL_IDLE();
432 /* Reset the Command Processor. This will not flush any pending
433 * commands, so you must wait for the CP command stream to complete
434 * before calling this routine.
436 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
441 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
442 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
443 SET_RING_HEAD(dev_priv, cur_read_ptr);
444 dev_priv->ring.tail = cur_read_ptr;
447 /* Stop the Command Processor. This will not flush any pending
448 * commands, so you must flush the command stream and wait for the CP
449 * to go idle before calling this routine.
451 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
455 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
457 dev_priv->cp_running = 0;
460 /* Reset the engine. This will stop the CP if it is running.
462 static int radeon_do_engine_reset(struct drm_device * dev)
464 drm_radeon_private_t *dev_priv = dev->dev_private;
465 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
468 radeon_do_pixcache_flush(dev_priv);
470 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
471 /* may need something similar for newer chips */
472 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
473 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
475 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
476 RADEON_FORCEON_MCLKA |
477 RADEON_FORCEON_MCLKB |
478 RADEON_FORCEON_YCLKA |
479 RADEON_FORCEON_YCLKB |
481 RADEON_FORCEON_AIC));
484 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
486 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
487 RADEON_SOFT_RESET_CP |
488 RADEON_SOFT_RESET_HI |
489 RADEON_SOFT_RESET_SE |
490 RADEON_SOFT_RESET_RE |
491 RADEON_SOFT_RESET_PP |
492 RADEON_SOFT_RESET_E2 |
493 RADEON_SOFT_RESET_RB));
494 RADEON_READ(RADEON_RBBM_SOFT_RESET);
495 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
496 ~(RADEON_SOFT_RESET_CP |
497 RADEON_SOFT_RESET_HI |
498 RADEON_SOFT_RESET_SE |
499 RADEON_SOFT_RESET_RE |
500 RADEON_SOFT_RESET_PP |
501 RADEON_SOFT_RESET_E2 |
502 RADEON_SOFT_RESET_RB)));
503 RADEON_READ(RADEON_RBBM_SOFT_RESET);
505 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
506 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
507 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
508 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
511 /* setup the raster pipes */
512 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
513 radeon_init_pipes(dev_priv);
515 /* Reset the CP ring */
516 radeon_do_cp_reset(dev_priv);
518 /* The CP is no longer running after an engine reset */
519 dev_priv->cp_running = 0;
521 /* Reset any pending vertex, indirect buffers */
522 radeon_freelist_reset(dev);
527 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
528 drm_radeon_private_t * dev_priv)
530 u32 ring_start, cur_read_ptr;
533 /* Initialize the memory controller. With new memory map, the fb location
534 * is not changed, it should have been properly initialized already. Part
535 * of the problem is that the code below is bogus, assuming the GART is
536 * always appended to the fb which is not necessarily the case
538 if (!dev_priv->new_memmap)
539 radeon_write_fb_location(dev_priv,
540 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
541 | (dev_priv->fb_location >> 16));
544 if (dev_priv->flags & RADEON_IS_AGP) {
545 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
546 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
547 RADEON_WRITE(RADEON_AGP_BASE_2, 0);
548 radeon_write_agp_location(dev_priv,
549 (((dev_priv->gart_vm_start - 1 +
550 dev_priv->gart_size) & 0xffff0000) |
551 (dev_priv->gart_vm_start >> 16)));
553 ring_start = (dev_priv->cp_ring->offset
555 + dev_priv->gart_vm_start);
558 ring_start = (dev_priv->cp_ring->offset
559 - (unsigned long)dev->sg->virtual
560 + dev_priv->gart_vm_start);
562 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
564 /* Set the write pointer delay */
565 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
567 /* Initialize the ring buffer's read and write pointers */
568 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
569 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
570 SET_RING_HEAD(dev_priv, cur_read_ptr);
571 dev_priv->ring.tail = cur_read_ptr;
574 if (dev_priv->flags & RADEON_IS_AGP) {
575 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
576 dev_priv->ring_rptr->offset
577 - dev->agp->base + dev_priv->gart_vm_start);
581 struct drm_sg_mem *entry = dev->sg;
582 unsigned long tmp_ofs, page_ofs;
584 tmp_ofs = dev_priv->ring_rptr->offset -
585 (unsigned long)dev->sg->virtual;
586 page_ofs = tmp_ofs >> PAGE_SHIFT;
588 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
589 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
590 (unsigned long)entry->busaddr[page_ofs],
591 entry->handle + tmp_ofs);
594 /* Set ring buffer size */
596 RADEON_WRITE(RADEON_CP_RB_CNTL,
597 RADEON_BUF_SWAP_32BIT |
598 (dev_priv->ring.fetch_size_l2ow << 18) |
599 (dev_priv->ring.rptr_update_l2qw << 8) |
600 dev_priv->ring.size_l2qw);
602 RADEON_WRITE(RADEON_CP_RB_CNTL,
603 (dev_priv->ring.fetch_size_l2ow << 18) |
604 (dev_priv->ring.rptr_update_l2qw << 8) |
605 dev_priv->ring.size_l2qw);
608 /* Start with assuming that writeback doesn't work */
609 dev_priv->writeback_works = 0;
611 /* Initialize the scratch register pointer. This will cause
612 * the scratch register values to be written out to memory
613 * whenever they are updated.
615 * We simply put this behind the ring read pointer, this works
616 * with PCI GART as well as (whatever kind of) AGP GART
618 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
619 + RADEON_SCRATCH_REG_OFFSET);
621 dev_priv->scratch = ((__volatile__ u32 *)
622 dev_priv->ring_rptr->handle +
623 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
625 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
627 /* Turn on bus mastering */
628 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
629 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
631 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
632 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
634 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
635 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
636 dev_priv->sarea_priv->last_dispatch);
638 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
639 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
641 radeon_do_wait_for_idle(dev_priv);
643 /* Sync everything up */
644 RADEON_WRITE(RADEON_ISYNC_CNTL,
645 (RADEON_ISYNC_ANY2D_IDLE3D |
646 RADEON_ISYNC_ANY3D_IDLE2D |
647 RADEON_ISYNC_WAIT_IDLEGUI |
648 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
652 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
656 /* Writeback doesn't seem to work everywhere, test it here and possibly
657 * enable it if it appears to work
659 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
660 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
662 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
663 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
669 if (tmp < dev_priv->usec_timeout) {
670 dev_priv->writeback_works = 1;
671 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
673 dev_priv->writeback_works = 0;
674 DRM_INFO("writeback test failed\n");
676 if (radeon_no_wb == 1) {
677 dev_priv->writeback_works = 0;
678 DRM_INFO("writeback forced off\n");
681 if (!dev_priv->writeback_works) {
682 /* Disable writeback to avoid unnecessary bus master transfer */
683 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
684 RADEON_RB_NO_UPDATE);
685 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
689 /* Enable or disable IGP GART on the chip */
690 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
695 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
696 dev_priv->gart_vm_start,
697 (long)dev_priv->gart_info.bus_addr,
698 dev_priv->gart_size);
700 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
701 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
702 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
703 RS690_BLOCK_GFX_D3_EN));
705 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
707 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
708 RS480_VA_SIZE_32MB));
710 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
711 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
716 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
717 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
718 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
720 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
721 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
722 RS480_REQ_TYPE_SNOOP_DIS));
724 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
725 IGP_WRITE_MCIND(RS690_MC_AGP_BASE,
726 (unsigned int)dev_priv->gart_vm_start);
727 IGP_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0);
729 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
730 RADEON_WRITE(RS480_AGP_BASE_2, 0);
733 dev_priv->gart_size = 32*1024*1024;
734 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
735 0xffff0000) | (dev_priv->gart_vm_start >> 16));
737 radeon_write_agp_location(dev_priv, temp);
739 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
740 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
741 RS480_VA_SIZE_32MB));
744 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
745 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
750 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
751 RS480_GART_CACHE_INVALIDATE);
754 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
755 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
760 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
762 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
766 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
768 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
771 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
772 dev_priv->gart_vm_start,
773 (long)dev_priv->gart_info.bus_addr,
774 dev_priv->gart_size);
775 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
776 dev_priv->gart_vm_start);
777 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
778 dev_priv->gart_info.bus_addr);
779 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
780 dev_priv->gart_vm_start);
781 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
782 dev_priv->gart_vm_start +
783 dev_priv->gart_size - 1);
785 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
787 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
788 RADEON_PCIE_TX_GART_EN);
790 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
791 tmp & ~RADEON_PCIE_TX_GART_EN);
795 /* Enable or disable PCI GART on the chip */
796 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
800 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
801 (dev_priv->flags & RADEON_IS_IGPGART)) {
802 radeon_set_igpgart(dev_priv, on);
806 if (dev_priv->flags & RADEON_IS_PCIE) {
807 radeon_set_pciegart(dev_priv, on);
811 tmp = RADEON_READ(RADEON_AIC_CNTL);
814 RADEON_WRITE(RADEON_AIC_CNTL,
815 tmp | RADEON_PCIGART_TRANSLATE_EN);
817 /* set PCI GART page-table base address
819 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
821 /* set address range for PCI address translate
823 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
824 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
825 + dev_priv->gart_size - 1);
827 /* Turn off AGP aperture -- is this required for PCI GART?
829 radeon_write_agp_location(dev_priv, 0xffffffc0);
830 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
832 RADEON_WRITE(RADEON_AIC_CNTL,
833 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
837 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
839 drm_radeon_private_t *dev_priv = dev->dev_private;
843 /* if we require new memory map but we don't have it fail */
844 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
845 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
846 radeon_do_cleanup_cp(dev);
850 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
851 DRM_DEBUG("Forcing AGP card to PCI mode\n");
852 dev_priv->flags &= ~RADEON_IS_AGP;
853 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
855 DRM_DEBUG("Restoring AGP flag\n");
856 dev_priv->flags |= RADEON_IS_AGP;
859 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
860 DRM_ERROR("PCI GART memory not allocated!\n");
861 radeon_do_cleanup_cp(dev);
865 dev_priv->usec_timeout = init->usec_timeout;
866 if (dev_priv->usec_timeout < 1 ||
867 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
868 DRM_DEBUG("TIMEOUT problem!\n");
869 radeon_do_cleanup_cp(dev);
873 /* Enable vblank on CRTC1 for older X servers
875 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
878 case RADEON_INIT_R200_CP:
879 dev_priv->microcode_version = UCODE_R200;
881 case RADEON_INIT_R300_CP:
882 dev_priv->microcode_version = UCODE_R300;
885 dev_priv->microcode_version = UCODE_R100;
888 dev_priv->do_boxes = 0;
889 dev_priv->cp_mode = init->cp_mode;
891 /* We don't support anything other than bus-mastering ring mode,
892 * but the ring can be in either AGP or PCI space for the ring
895 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
896 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
897 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
898 radeon_do_cleanup_cp(dev);
902 switch (init->fb_bpp) {
904 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
908 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
911 dev_priv->front_offset = init->front_offset;
912 dev_priv->front_pitch = init->front_pitch;
913 dev_priv->back_offset = init->back_offset;
914 dev_priv->back_pitch = init->back_pitch;
916 switch (init->depth_bpp) {
918 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
922 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
925 dev_priv->depth_offset = init->depth_offset;
926 dev_priv->depth_pitch = init->depth_pitch;
928 /* Hardware state for depth clears. Remove this if/when we no
929 * longer clear the depth buffer with a 3D rectangle. Hard-code
930 * all values to prevent unwanted 3D state from slipping through
931 * and screwing with the clear operation.
933 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
934 (dev_priv->color_fmt << 10) |
935 (dev_priv->microcode_version ==
936 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
938 dev_priv->depth_clear.rb3d_zstencilcntl =
939 (dev_priv->depth_fmt |
940 RADEON_Z_TEST_ALWAYS |
941 RADEON_STENCIL_TEST_ALWAYS |
942 RADEON_STENCIL_S_FAIL_REPLACE |
943 RADEON_STENCIL_ZPASS_REPLACE |
944 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
946 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
949 RADEON_FLAT_SHADE_VTX_LAST |
950 RADEON_DIFFUSE_SHADE_FLAT |
951 RADEON_ALPHA_SHADE_FLAT |
952 RADEON_SPECULAR_SHADE_FLAT |
953 RADEON_FOG_SHADE_FLAT |
954 RADEON_VTX_PIX_CENTER_OGL |
955 RADEON_ROUND_MODE_TRUNC |
956 RADEON_ROUND_PREC_8TH_PIX);
959 dev_priv->ring_offset = init->ring_offset;
960 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
961 dev_priv->buffers_offset = init->buffers_offset;
962 dev_priv->gart_textures_offset = init->gart_textures_offset;
964 dev_priv->sarea = drm_getsarea(dev);
965 if (!dev_priv->sarea) {
966 DRM_ERROR("could not find sarea!\n");
967 radeon_do_cleanup_cp(dev);
971 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
972 if (!dev_priv->cp_ring) {
973 DRM_ERROR("could not find cp ring region!\n");
974 radeon_do_cleanup_cp(dev);
977 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
978 if (!dev_priv->ring_rptr) {
979 DRM_ERROR("could not find ring read pointer!\n");
980 radeon_do_cleanup_cp(dev);
983 dev->agp_buffer_token = init->buffers_offset;
984 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
985 if (!dev->agp_buffer_map) {
986 DRM_ERROR("could not find dma buffer region!\n");
987 radeon_do_cleanup_cp(dev);
991 if (init->gart_textures_offset) {
992 dev_priv->gart_textures =
993 drm_core_findmap(dev, init->gart_textures_offset);
994 if (!dev_priv->gart_textures) {
995 DRM_ERROR("could not find GART texture region!\n");
996 radeon_do_cleanup_cp(dev);
1001 dev_priv->sarea_priv =
1002 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1003 init->sarea_priv_offset);
1006 if (dev_priv->flags & RADEON_IS_AGP) {
1007 drm_core_ioremap(dev_priv->cp_ring, dev);
1008 drm_core_ioremap(dev_priv->ring_rptr, dev);
1009 drm_core_ioremap(dev->agp_buffer_map, dev);
1010 if (!dev_priv->cp_ring->handle ||
1011 !dev_priv->ring_rptr->handle ||
1012 !dev->agp_buffer_map->handle) {
1013 DRM_ERROR("could not find ioremap agp regions!\n");
1014 radeon_do_cleanup_cp(dev);
1020 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1021 dev_priv->ring_rptr->handle =
1022 (void *)dev_priv->ring_rptr->offset;
1023 dev->agp_buffer_map->handle =
1024 (void *)dev->agp_buffer_map->offset;
1026 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1027 dev_priv->cp_ring->handle);
1028 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1029 dev_priv->ring_rptr->handle);
1030 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1031 dev->agp_buffer_map->handle);
1034 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1036 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1037 - dev_priv->fb_location;
1039 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1040 ((dev_priv->front_offset
1041 + dev_priv->fb_location) >> 10));
1043 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1044 ((dev_priv->back_offset
1045 + dev_priv->fb_location) >> 10));
1047 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1048 ((dev_priv->depth_offset
1049 + dev_priv->fb_location) >> 10));
1051 dev_priv->gart_size = init->gart_size;
1053 /* New let's set the memory map ... */
1054 if (dev_priv->new_memmap) {
1057 DRM_INFO("Setting GART location based on new memory map\n");
1059 /* If using AGP, try to locate the AGP aperture at the same
1060 * location in the card and on the bus, though we have to
1064 if (dev_priv->flags & RADEON_IS_AGP) {
1065 base = dev->agp->base;
1066 /* Check if valid */
1067 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1068 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1069 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1075 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1077 base = dev_priv->fb_location + dev_priv->fb_size;
1078 if (base < dev_priv->fb_location ||
1079 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1080 base = dev_priv->fb_location
1081 - dev_priv->gart_size;
1083 dev_priv->gart_vm_start = base & 0xffc00000u;
1084 if (dev_priv->gart_vm_start != base)
1085 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1086 base, dev_priv->gart_vm_start);
1088 DRM_INFO("Setting GART location based on old memory map\n");
1089 dev_priv->gart_vm_start = dev_priv->fb_location +
1090 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1094 if (dev_priv->flags & RADEON_IS_AGP)
1095 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1097 + dev_priv->gart_vm_start);
1100 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1101 - (unsigned long)dev->sg->virtual
1102 + dev_priv->gart_vm_start);
1104 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1105 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1106 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1107 dev_priv->gart_buffers_offset);
1109 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1110 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1111 + init->ring_size / sizeof(u32));
1112 dev_priv->ring.size = init->ring_size;
1113 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1115 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1116 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1118 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1119 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1120 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1122 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1125 if (dev_priv->flags & RADEON_IS_AGP) {
1126 /* Turn off PCI GART */
1127 radeon_set_pcigart(dev_priv, 0);
1131 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1132 /* if we have an offset set from userspace */
1133 if (dev_priv->pcigart_offset_set) {
1134 dev_priv->gart_info.bus_addr =
1135 dev_priv->pcigart_offset + dev_priv->fb_location;
1136 dev_priv->gart_info.mapping.offset =
1137 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1138 dev_priv->gart_info.mapping.size =
1139 dev_priv->gart_info.table_size;
1141 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1142 dev_priv->gart_info.addr =
1143 dev_priv->gart_info.mapping.handle;
1145 if (dev_priv->flags & RADEON_IS_PCIE)
1146 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1148 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1149 dev_priv->gart_info.gart_table_location =
1152 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1153 dev_priv->gart_info.addr,
1154 dev_priv->pcigart_offset);
1156 if (dev_priv->flags & RADEON_IS_IGPGART)
1157 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1159 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1160 dev_priv->gart_info.gart_table_location =
1162 dev_priv->gart_info.addr = NULL;
1163 dev_priv->gart_info.bus_addr = 0;
1164 if (dev_priv->flags & RADEON_IS_PCIE) {
1166 ("Cannot use PCI Express without GART in FB memory\n");
1167 radeon_do_cleanup_cp(dev);
1172 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1173 DRM_ERROR("failed to init PCI GART!\n");
1174 radeon_do_cleanup_cp(dev);
1178 /* Turn on PCI GART */
1179 radeon_set_pcigart(dev_priv, 1);
1182 radeon_cp_load_microcode(dev_priv);
1183 radeon_cp_init_ring_buffer(dev, dev_priv);
1185 dev_priv->last_buf = 0;
1187 radeon_do_engine_reset(dev);
1188 radeon_test_writeback(dev_priv);
1193 static int radeon_do_cleanup_cp(struct drm_device * dev)
1195 drm_radeon_private_t *dev_priv = dev->dev_private;
1198 /* Make sure interrupts are disabled here because the uninstall ioctl
1199 * may not have been called from userspace and after dev_private
1200 * is freed, it's too late.
1202 if (dev->irq_enabled)
1203 drm_irq_uninstall(dev);
1206 if (dev_priv->flags & RADEON_IS_AGP) {
1207 if (dev_priv->cp_ring != NULL) {
1208 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1209 dev_priv->cp_ring = NULL;
1211 if (dev_priv->ring_rptr != NULL) {
1212 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1213 dev_priv->ring_rptr = NULL;
1215 if (dev->agp_buffer_map != NULL) {
1216 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1217 dev->agp_buffer_map = NULL;
1223 if (dev_priv->gart_info.bus_addr) {
1224 /* Turn off PCI GART */
1225 radeon_set_pcigart(dev_priv, 0);
1226 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1227 DRM_ERROR("failed to cleanup PCI GART!\n");
1230 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1232 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1233 dev_priv->gart_info.addr = 0;
1236 /* only clear to the start of flags */
1237 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1242 /* This code will reinit the Radeon CP hardware after a resume from disc.
1243 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1244 * here we make sure that all Radeon hardware initialisation is re-done without
1245 * affecting running applications.
1247 * Charl P. Botha <http://cpbotha.net>
1249 static int radeon_do_resume_cp(struct drm_device * dev)
1251 drm_radeon_private_t *dev_priv = dev->dev_private;
1254 DRM_ERROR("Called with no initialization\n");
1258 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1261 if (dev_priv->flags & RADEON_IS_AGP) {
1262 /* Turn off PCI GART */
1263 radeon_set_pcigart(dev_priv, 0);
1267 /* Turn on PCI GART */
1268 radeon_set_pcigart(dev_priv, 1);
1271 radeon_cp_load_microcode(dev_priv);
1272 radeon_cp_init_ring_buffer(dev, dev_priv);
1274 radeon_do_engine_reset(dev);
1276 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1281 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1283 drm_radeon_init_t *init = data;
1285 LOCK_TEST_WITH_RETURN(dev, file_priv);
1287 if (init->func == RADEON_INIT_R300_CP)
1288 r300_init_reg_flags(dev);
1290 switch (init->func) {
1291 case RADEON_INIT_CP:
1292 case RADEON_INIT_R200_CP:
1293 case RADEON_INIT_R300_CP:
1294 return radeon_do_init_cp(dev, init);
1295 case RADEON_CLEANUP_CP:
1296 return radeon_do_cleanup_cp(dev);
1302 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1304 drm_radeon_private_t *dev_priv = dev->dev_private;
1307 LOCK_TEST_WITH_RETURN(dev, file_priv);
1309 if (dev_priv->cp_running) {
1310 DRM_DEBUG("while CP running\n");
1313 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1314 DRM_DEBUG("called with bogus CP mode (%d)\n",
1319 radeon_do_cp_start(dev_priv);
1324 /* Stop the CP. The engine must have been idled before calling this
1327 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1329 drm_radeon_private_t *dev_priv = dev->dev_private;
1330 drm_radeon_cp_stop_t *stop = data;
1334 LOCK_TEST_WITH_RETURN(dev, file_priv);
1336 if (!dev_priv->cp_running)
1339 /* Flush any pending CP commands. This ensures any outstanding
1340 * commands are exectuted by the engine before we turn it off.
1343 radeon_do_cp_flush(dev_priv);
1346 /* If we fail to make the engine go idle, we return an error
1347 * code so that the DRM ioctl wrapper can try again.
1350 ret = radeon_do_cp_idle(dev_priv);
1355 /* Finally, we can turn off the CP. If the engine isn't idle,
1356 * we will get some dropped triangles as they won't be fully
1357 * rendered before the CP is shut down.
1359 radeon_do_cp_stop(dev_priv);
1361 /* Reset the engine */
1362 radeon_do_engine_reset(dev);
1367 void radeon_do_release(struct drm_device * dev)
1369 drm_radeon_private_t *dev_priv = dev->dev_private;
1373 if (dev_priv->cp_running) {
1375 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1376 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1380 tsleep(&ret, PZERO, "rdnrel", 1);
1383 radeon_do_cp_stop(dev_priv);
1384 radeon_do_engine_reset(dev);
1387 /* Disable *all* interrupts */
1388 if (dev_priv->mmio) /* remove this after permanent addmaps */
1389 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1391 if (dev_priv->mmio) { /* remove all surfaces */
1392 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1393 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1394 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1396 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1401 /* Free memory heap structures */
1402 radeon_mem_takedown(&(dev_priv->gart_heap));
1403 radeon_mem_takedown(&(dev_priv->fb_heap));
1405 /* deallocate kernel resources */
1406 radeon_do_cleanup_cp(dev);
1410 /* Just reset the CP ring. Called as part of an X Server engine reset.
1412 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1414 drm_radeon_private_t *dev_priv = dev->dev_private;
1417 LOCK_TEST_WITH_RETURN(dev, file_priv);
1420 DRM_DEBUG("called before init done\n");
1424 radeon_do_cp_reset(dev_priv);
1426 /* The CP is no longer running after an engine reset */
1427 dev_priv->cp_running = 0;
1432 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1434 drm_radeon_private_t *dev_priv = dev->dev_private;
1437 LOCK_TEST_WITH_RETURN(dev, file_priv);
1439 return radeon_do_cp_idle(dev_priv);
1442 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1444 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1447 return radeon_do_resume_cp(dev);
1450 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1454 LOCK_TEST_WITH_RETURN(dev, file_priv);
1456 return radeon_do_engine_reset(dev);
1459 /* ================================================================
1463 /* KW: Deprecated to say the least:
1465 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1470 /* ================================================================
1471 * Freelist management
1474 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1475 * bufs until freelist code is used. Note this hides a problem with
1476 * the scratch register * (used to keep track of last buffer
1477 * completed) being written to before * the last buffer has actually
1478 * completed rendering.
1480 * KW: It's also a good way to find free buffers quickly.
1482 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1483 * sleep. However, bugs in older versions of radeon_accel.c mean that
1484 * we essentially have to do this, else old clients will break.
1486 * However, it does leave open a potential deadlock where all the
1487 * buffers are held by other clients, which can't release them because
1488 * they can't get the lock.
1491 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1493 struct drm_device_dma *dma = dev->dma;
1494 drm_radeon_private_t *dev_priv = dev->dev_private;
1495 drm_radeon_buf_priv_t *buf_priv;
1496 struct drm_buf *buf;
1500 if (++dev_priv->last_buf >= dma->buf_count)
1501 dev_priv->last_buf = 0;
1503 start = dev_priv->last_buf;
1505 for (t = 0; t < dev_priv->usec_timeout; t++) {
1506 u32 done_age = GET_SCRATCH(1);
1507 DRM_DEBUG("done_age = %d\n", done_age);
1508 for (i = start; i < dma->buf_count; i++) {
1509 buf = dma->buflist[i];
1510 buf_priv = buf->dev_private;
1511 if (buf->file_priv == NULL || (buf->pending &&
1514 dev_priv->stats.requested_bufs++;
1523 dev_priv->stats.freelist_loops++;
1527 DRM_DEBUG("returning NULL!\n");
1532 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1534 struct drm_device_dma *dma = dev->dma;
1535 drm_radeon_private_t *dev_priv = dev->dev_private;
1536 drm_radeon_buf_priv_t *buf_priv;
1537 struct drm_buf *buf;
1540 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1542 if (++dev_priv->last_buf >= dma->buf_count)
1543 dev_priv->last_buf = 0;
1545 start = dev_priv->last_buf;
1546 dev_priv->stats.freelist_loops++;
1548 for (t = 0; t < 2; t++) {
1549 for (i = start; i < dma->buf_count; i++) {
1550 buf = dma->buflist[i];
1551 buf_priv = buf->dev_private;
1552 if (buf->file_priv == 0 || (buf->pending &&
1555 dev_priv->stats.requested_bufs++;
1567 void radeon_freelist_reset(struct drm_device * dev)
1569 struct drm_device_dma *dma = dev->dma;
1570 drm_radeon_private_t *dev_priv = dev->dev_private;
1573 dev_priv->last_buf = 0;
1574 for (i = 0; i < dma->buf_count; i++) {
1575 struct drm_buf *buf = dma->buflist[i];
1576 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1581 /* ================================================================
1582 * CP command submission
1585 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1587 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1589 u32 last_head = GET_RING_HEAD(dev_priv);
1591 for (i = 0; i < dev_priv->usec_timeout; i++) {
1592 u32 head = GET_RING_HEAD(dev_priv);
1594 ring->space = (head - ring->tail) * sizeof(u32);
1595 if (ring->space <= 0)
1596 ring->space += ring->size;
1597 if (ring->space > n)
1600 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1602 if (head != last_head)
1609 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1610 #if RADEON_FIFO_DEBUG
1611 radeon_status(dev_priv);
1612 DRM_ERROR("failed!\n");
1617 static int radeon_cp_get_buffers(struct drm_device *dev,
1618 struct drm_file *file_priv,
1622 struct drm_buf *buf;
1624 for (i = d->granted_count; i < d->request_count; i++) {
1625 buf = radeon_freelist_get(dev);
1627 return -EBUSY; /* NOTE: broken client */
1629 buf->file_priv = file_priv;
1631 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1634 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1635 sizeof(buf->total)))
1643 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1645 struct drm_device_dma *dma = dev->dma;
1647 struct drm_dma *d = data;
1649 LOCK_TEST_WITH_RETURN(dev, file_priv);
1651 /* Please don't send us buffers.
1653 if (d->send_count != 0) {
1654 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1655 DRM_CURRENTPID, d->send_count);
1659 /* We'll send you buffers.
1661 if (d->request_count < 0 || d->request_count > dma->buf_count) {
1662 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1663 DRM_CURRENTPID, d->request_count, dma->buf_count);
1667 d->granted_count = 0;
1669 if (d->request_count) {
1670 ret = radeon_cp_get_buffers(dev, file_priv, d);
1676 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1678 drm_radeon_private_t *dev_priv;
1681 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1682 if (dev_priv == NULL)
1685 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1686 dev->dev_private = (void *)dev_priv;
1687 dev_priv->flags = flags;
1689 switch (flags & RADEON_FAMILY_MASK) {
1701 dev_priv->flags |= RADEON_HAS_HIERZ;
1704 /* all other chips have no hierarchical z buffer */
1708 if (drm_device_is_agp(dev))
1709 dev_priv->flags |= RADEON_IS_AGP;
1710 else if (drm_device_is_pcie(dev))
1711 dev_priv->flags |= RADEON_IS_PCIE;
1713 dev_priv->flags |= RADEON_IS_PCI;
1715 DRM_DEBUG("%s card detected\n",
1716 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1720 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1721 * have to find them.
1723 int radeon_driver_firstopen(struct drm_device *dev)
1726 drm_local_map_t *map;
1727 drm_radeon_private_t *dev_priv = dev->dev_private;
1729 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1731 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1732 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1733 _DRM_READ_ONLY, &dev_priv->mmio);
1737 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1738 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1739 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1740 _DRM_WRITE_COMBINING, &map);
1747 int radeon_driver_unload(struct drm_device *dev)
1749 drm_radeon_private_t *dev_priv = dev->dev_private;
1752 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1754 dev->dev_private = NULL;