1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
34 #include "radeon_drm.h"
35 #include "radeon_drv.h"
38 #include "radeon_microcode.h"
40 #define RADEON_FIFO_DEBUG 0
42 static int radeon_do_cleanup_cp(struct drm_device * dev);
44 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
47 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
48 ret = RADEON_READ(R520_MC_IND_DATA);
49 RADEON_WRITE(R520_MC_IND_INDEX, 0);
53 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
56 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
57 ret = RADEON_READ(RS480_NB_MC_DATA);
58 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
62 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
65 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
66 ret = RADEON_READ(RS690_MC_DATA);
67 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
71 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
73 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
74 return RS690_READ_MCIND(dev_priv, addr);
76 return RS480_READ_MCIND(dev_priv, addr);
79 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
82 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
83 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
84 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
85 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
86 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
87 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
89 return RADEON_READ(RADEON_MC_FB_LOCATION);
92 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
94 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
95 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
96 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
97 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
98 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
99 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
101 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
104 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
106 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
107 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
108 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
109 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
110 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
111 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
113 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
116 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
118 drm_radeon_private_t *dev_priv = dev->dev_private;
120 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
121 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
124 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
126 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
127 return RADEON_READ(RADEON_PCIE_DATA);
130 #if RADEON_FIFO_DEBUG
131 static void radeon_status(drm_radeon_private_t * dev_priv)
133 printk("%s:\n", __func__);
134 printk("RBBM_STATUS = 0x%08x\n",
135 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
136 printk("CP_RB_RTPR = 0x%08x\n",
137 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
138 printk("CP_RB_WTPR = 0x%08x\n",
139 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
140 printk("AIC_CNTL = 0x%08x\n",
141 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
142 printk("AIC_STAT = 0x%08x\n",
143 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
144 printk("AIC_PT_BASE = 0x%08x\n",
145 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
146 printk("TLB_ADDR = 0x%08x\n",
147 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
148 printk("TLB_DATA = 0x%08x\n",
149 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
153 /* ================================================================
154 * Engine, FIFO control
157 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
162 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
164 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
165 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
166 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
167 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
169 for (i = 0; i < dev_priv->usec_timeout; i++) {
170 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
171 & RADEON_RB3D_DC_BUSY)) {
178 tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT);
179 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
180 RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp);
183 tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
184 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
185 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
187 for (i = 0; i < dev_priv->usec_timeout; i++) {
188 if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
189 & RADEON_RB3D_DC_BUSY)) {
196 #if RADEON_FIFO_DEBUG
197 DRM_ERROR("failed!\n");
198 radeon_status(dev_priv);
203 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
207 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
209 for (i = 0; i < dev_priv->usec_timeout; i++) {
210 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
211 & RADEON_RBBM_FIFOCNT_MASK);
212 if (slots >= entries)
217 #if RADEON_FIFO_DEBUG
218 DRM_ERROR("failed!\n");
219 radeon_status(dev_priv);
224 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
228 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
230 ret = radeon_do_wait_for_fifo(dev_priv, 64);
234 for (i = 0; i < dev_priv->usec_timeout; i++) {
235 if (!(RADEON_READ(RADEON_RBBM_STATUS)
236 & RADEON_RBBM_ACTIVE)) {
237 radeon_do_pixcache_flush(dev_priv);
243 #if RADEON_FIFO_DEBUG
244 DRM_ERROR("failed!\n");
245 radeon_status(dev_priv);
250 /* ================================================================
251 * CP control, initialization
254 /* Load the microcode for the CP */
255 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
260 radeon_do_wait_for_idle(dev_priv);
262 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
263 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
264 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
265 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
266 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
267 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
268 DRM_INFO("Loading R100 Microcode\n");
269 for (i = 0; i < 256; i++) {
270 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
271 R100_cp_microcode[i][1]);
272 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
273 R100_cp_microcode[i][0]);
275 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
276 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
277 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
278 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
279 DRM_INFO("Loading R200 Microcode\n");
280 for (i = 0; i < 256; i++) {
281 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
282 R200_cp_microcode[i][1]);
283 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
284 R200_cp_microcode[i][0]);
286 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
287 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
288 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
289 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
290 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
291 DRM_INFO("Loading R300 Microcode\n");
292 for (i = 0; i < 256; i++) {
293 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
294 R300_cp_microcode[i][1]);
295 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
296 R300_cp_microcode[i][0]);
298 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
299 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
300 DRM_INFO("Loading R400 Microcode\n");
301 for (i = 0; i < 256; i++) {
302 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
303 R420_cp_microcode[i][1]);
304 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
305 R420_cp_microcode[i][0]);
307 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
308 DRM_INFO("Loading RS690 Microcode\n");
309 for (i = 0; i < 256; i++) {
310 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
311 RS690_cp_microcode[i][1]);
312 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
313 RS690_cp_microcode[i][0]);
315 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
316 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
317 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
318 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
319 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
320 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
321 DRM_INFO("Loading R500 Microcode\n");
322 for (i = 0; i < 256; i++) {
323 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
324 R520_cp_microcode[i][1]);
325 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
326 R520_cp_microcode[i][0]);
331 /* Flush any pending commands to the CP. This should only be used just
332 * prior to a wait for idle, as it informs the engine that the command
335 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
341 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
342 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
346 /* Wait for the CP to go idle.
348 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
355 RADEON_PURGE_CACHE();
356 RADEON_PURGE_ZCACHE();
357 RADEON_WAIT_UNTIL_IDLE();
362 return radeon_do_wait_for_idle(dev_priv);
365 /* Start the Command Processor.
367 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
372 radeon_do_wait_for_idle(dev_priv);
374 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
376 dev_priv->cp_running = 1;
380 RADEON_PURGE_CACHE();
381 RADEON_PURGE_ZCACHE();
382 RADEON_WAIT_UNTIL_IDLE();
388 /* Reset the Command Processor. This will not flush any pending
389 * commands, so you must wait for the CP command stream to complete
390 * before calling this routine.
392 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
397 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
398 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
399 SET_RING_HEAD(dev_priv, cur_read_ptr);
400 dev_priv->ring.tail = cur_read_ptr;
403 /* Stop the Command Processor. This will not flush any pending
404 * commands, so you must flush the command stream and wait for the CP
405 * to go idle before calling this routine.
407 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
411 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
413 dev_priv->cp_running = 0;
416 /* Reset the engine. This will stop the CP if it is running.
418 static int radeon_do_engine_reset(struct drm_device * dev)
420 drm_radeon_private_t *dev_priv = dev->dev_private;
421 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
424 radeon_do_pixcache_flush(dev_priv);
426 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
427 /* may need something similar for newer chips */
428 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
429 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
431 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
432 RADEON_FORCEON_MCLKA |
433 RADEON_FORCEON_MCLKB |
434 RADEON_FORCEON_YCLKA |
435 RADEON_FORCEON_YCLKB |
437 RADEON_FORCEON_AIC));
440 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
442 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
443 RADEON_SOFT_RESET_CP |
444 RADEON_SOFT_RESET_HI |
445 RADEON_SOFT_RESET_SE |
446 RADEON_SOFT_RESET_RE |
447 RADEON_SOFT_RESET_PP |
448 RADEON_SOFT_RESET_E2 |
449 RADEON_SOFT_RESET_RB));
450 RADEON_READ(RADEON_RBBM_SOFT_RESET);
451 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
452 ~(RADEON_SOFT_RESET_CP |
453 RADEON_SOFT_RESET_HI |
454 RADEON_SOFT_RESET_SE |
455 RADEON_SOFT_RESET_RE |
456 RADEON_SOFT_RESET_PP |
457 RADEON_SOFT_RESET_E2 |
458 RADEON_SOFT_RESET_RB)));
459 RADEON_READ(RADEON_RBBM_SOFT_RESET);
461 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
462 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
463 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
464 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
467 /* Reset the CP ring */
468 radeon_do_cp_reset(dev_priv);
470 /* The CP is no longer running after an engine reset */
471 dev_priv->cp_running = 0;
473 /* Reset any pending vertex, indirect buffers */
474 radeon_freelist_reset(dev);
479 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
480 drm_radeon_private_t * dev_priv)
482 u32 ring_start, cur_read_ptr;
485 /* Initialize the memory controller. With new memory map, the fb location
486 * is not changed, it should have been properly initialized already. Part
487 * of the problem is that the code below is bogus, assuming the GART is
488 * always appended to the fb which is not necessarily the case
490 if (!dev_priv->new_memmap)
491 radeon_write_fb_location(dev_priv,
492 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
493 | (dev_priv->fb_location >> 16));
496 if (dev_priv->flags & RADEON_IS_AGP) {
497 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
498 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
499 RADEON_WRITE(RADEON_AGP_BASE_2, 0);
500 radeon_write_agp_location(dev_priv,
501 (((dev_priv->gart_vm_start - 1 +
502 dev_priv->gart_size) & 0xffff0000) |
503 (dev_priv->gart_vm_start >> 16)));
505 ring_start = (dev_priv->cp_ring->offset
507 + dev_priv->gart_vm_start);
510 ring_start = (dev_priv->cp_ring->offset
511 - (unsigned long)dev->sg->virtual
512 + dev_priv->gart_vm_start);
514 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
516 /* Set the write pointer delay */
517 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
519 /* Initialize the ring buffer's read and write pointers */
520 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
521 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
522 SET_RING_HEAD(dev_priv, cur_read_ptr);
523 dev_priv->ring.tail = cur_read_ptr;
526 if (dev_priv->flags & RADEON_IS_AGP) {
527 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
528 dev_priv->ring_rptr->offset
529 - dev->agp->base + dev_priv->gart_vm_start);
533 struct drm_sg_mem *entry = dev->sg;
534 unsigned long tmp_ofs, page_ofs;
536 tmp_ofs = dev_priv->ring_rptr->offset -
537 (unsigned long)dev->sg->virtual;
538 page_ofs = tmp_ofs >> PAGE_SHIFT;
540 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
541 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
542 (unsigned long)entry->busaddr[page_ofs],
543 entry->handle + tmp_ofs);
546 /* Set ring buffer size */
548 RADEON_WRITE(RADEON_CP_RB_CNTL,
549 RADEON_BUF_SWAP_32BIT |
550 (dev_priv->ring.fetch_size_l2ow << 18) |
551 (dev_priv->ring.rptr_update_l2qw << 8) |
552 dev_priv->ring.size_l2qw);
554 RADEON_WRITE(RADEON_CP_RB_CNTL,
555 (dev_priv->ring.fetch_size_l2ow << 18) |
556 (dev_priv->ring.rptr_update_l2qw << 8) |
557 dev_priv->ring.size_l2qw);
560 /* Start with assuming that writeback doesn't work */
561 dev_priv->writeback_works = 0;
563 /* Initialize the scratch register pointer. This will cause
564 * the scratch register values to be written out to memory
565 * whenever they are updated.
567 * We simply put this behind the ring read pointer, this works
568 * with PCI GART as well as (whatever kind of) AGP GART
570 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
571 + RADEON_SCRATCH_REG_OFFSET);
573 dev_priv->scratch = ((__volatile__ u32 *)
574 dev_priv->ring_rptr->handle +
575 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
577 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
579 /* Turn on bus mastering */
580 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
581 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
583 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
584 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
586 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
587 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
588 dev_priv->sarea_priv->last_dispatch);
590 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
591 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
593 radeon_do_wait_for_idle(dev_priv);
595 /* Sync everything up */
596 RADEON_WRITE(RADEON_ISYNC_CNTL,
597 (RADEON_ISYNC_ANY2D_IDLE3D |
598 RADEON_ISYNC_ANY3D_IDLE2D |
599 RADEON_ISYNC_WAIT_IDLEGUI |
600 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
604 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
608 /* Writeback doesn't seem to work everywhere, test it here and possibly
609 * enable it if it appears to work
611 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
612 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
614 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
615 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
621 if (tmp < dev_priv->usec_timeout) {
622 dev_priv->writeback_works = 1;
623 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
625 dev_priv->writeback_works = 0;
626 DRM_INFO("writeback test failed\n");
628 if (radeon_no_wb == 1) {
629 dev_priv->writeback_works = 0;
630 DRM_INFO("writeback forced off\n");
633 if (!dev_priv->writeback_works) {
634 /* Disable writeback to avoid unnecessary bus master transfer */
635 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
636 RADEON_RB_NO_UPDATE);
637 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
641 /* Enable or disable IGP GART on the chip */
642 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
647 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
648 dev_priv->gart_vm_start,
649 (long)dev_priv->gart_info.bus_addr,
650 dev_priv->gart_size);
652 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
653 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
654 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
655 RS690_BLOCK_GFX_D3_EN));
657 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
659 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
660 RS480_VA_SIZE_32MB));
662 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
663 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
668 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
669 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
670 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
672 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
673 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
674 RS480_REQ_TYPE_SNOOP_DIS));
676 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
677 IGP_WRITE_MCIND(RS690_MC_AGP_BASE,
678 (unsigned int)dev_priv->gart_vm_start);
679 IGP_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0);
681 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
682 RADEON_WRITE(RS480_AGP_BASE_2, 0);
685 dev_priv->gart_size = 32*1024*1024;
686 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
687 0xffff0000) | (dev_priv->gart_vm_start >> 16));
689 radeon_write_agp_location(dev_priv, temp);
691 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
692 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
693 RS480_VA_SIZE_32MB));
696 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
697 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
702 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
703 RS480_GART_CACHE_INVALIDATE);
706 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
707 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
712 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
714 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
718 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
720 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
723 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
724 dev_priv->gart_vm_start,
725 (long)dev_priv->gart_info.bus_addr,
726 dev_priv->gart_size);
727 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
728 dev_priv->gart_vm_start);
729 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
730 dev_priv->gart_info.bus_addr);
731 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
732 dev_priv->gart_vm_start);
733 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
734 dev_priv->gart_vm_start +
735 dev_priv->gart_size - 1);
737 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
739 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
740 RADEON_PCIE_TX_GART_EN);
742 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
743 tmp & ~RADEON_PCIE_TX_GART_EN);
747 /* Enable or disable PCI GART on the chip */
748 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
752 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
753 (dev_priv->flags & RADEON_IS_IGPGART)) {
754 radeon_set_igpgart(dev_priv, on);
758 if (dev_priv->flags & RADEON_IS_PCIE) {
759 radeon_set_pciegart(dev_priv, on);
763 tmp = RADEON_READ(RADEON_AIC_CNTL);
766 RADEON_WRITE(RADEON_AIC_CNTL,
767 tmp | RADEON_PCIGART_TRANSLATE_EN);
769 /* set PCI GART page-table base address
771 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
773 /* set address range for PCI address translate
775 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
776 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
777 + dev_priv->gart_size - 1);
779 /* Turn off AGP aperture -- is this required for PCI GART?
781 radeon_write_agp_location(dev_priv, 0xffffffc0);
782 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
784 RADEON_WRITE(RADEON_AIC_CNTL,
785 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
789 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
791 drm_radeon_private_t *dev_priv = dev->dev_private;
795 /* if we require new memory map but we don't have it fail */
796 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
797 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
798 radeon_do_cleanup_cp(dev);
802 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
803 DRM_DEBUG("Forcing AGP card to PCI mode\n");
804 dev_priv->flags &= ~RADEON_IS_AGP;
805 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
807 DRM_DEBUG("Restoring AGP flag\n");
808 dev_priv->flags |= RADEON_IS_AGP;
811 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
812 DRM_ERROR("PCI GART memory not allocated!\n");
813 radeon_do_cleanup_cp(dev);
817 dev_priv->usec_timeout = init->usec_timeout;
818 if (dev_priv->usec_timeout < 1 ||
819 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
820 DRM_DEBUG("TIMEOUT problem!\n");
821 radeon_do_cleanup_cp(dev);
825 /* Enable vblank on CRTC1 for older X servers
827 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
830 case RADEON_INIT_R200_CP:
831 dev_priv->microcode_version = UCODE_R200;
833 case RADEON_INIT_R300_CP:
834 dev_priv->microcode_version = UCODE_R300;
837 dev_priv->microcode_version = UCODE_R100;
840 dev_priv->do_boxes = 0;
841 dev_priv->cp_mode = init->cp_mode;
843 /* We don't support anything other than bus-mastering ring mode,
844 * but the ring can be in either AGP or PCI space for the ring
847 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
848 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
849 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
850 radeon_do_cleanup_cp(dev);
854 switch (init->fb_bpp) {
856 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
860 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
863 dev_priv->front_offset = init->front_offset;
864 dev_priv->front_pitch = init->front_pitch;
865 dev_priv->back_offset = init->back_offset;
866 dev_priv->back_pitch = init->back_pitch;
868 switch (init->depth_bpp) {
870 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
874 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
877 dev_priv->depth_offset = init->depth_offset;
878 dev_priv->depth_pitch = init->depth_pitch;
880 /* Hardware state for depth clears. Remove this if/when we no
881 * longer clear the depth buffer with a 3D rectangle. Hard-code
882 * all values to prevent unwanted 3D state from slipping through
883 * and screwing with the clear operation.
885 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
886 (dev_priv->color_fmt << 10) |
887 (dev_priv->microcode_version ==
888 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
890 dev_priv->depth_clear.rb3d_zstencilcntl =
891 (dev_priv->depth_fmt |
892 RADEON_Z_TEST_ALWAYS |
893 RADEON_STENCIL_TEST_ALWAYS |
894 RADEON_STENCIL_S_FAIL_REPLACE |
895 RADEON_STENCIL_ZPASS_REPLACE |
896 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
898 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
901 RADEON_FLAT_SHADE_VTX_LAST |
902 RADEON_DIFFUSE_SHADE_FLAT |
903 RADEON_ALPHA_SHADE_FLAT |
904 RADEON_SPECULAR_SHADE_FLAT |
905 RADEON_FOG_SHADE_FLAT |
906 RADEON_VTX_PIX_CENTER_OGL |
907 RADEON_ROUND_MODE_TRUNC |
908 RADEON_ROUND_PREC_8TH_PIX);
911 dev_priv->ring_offset = init->ring_offset;
912 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
913 dev_priv->buffers_offset = init->buffers_offset;
914 dev_priv->gart_textures_offset = init->gart_textures_offset;
916 dev_priv->sarea = drm_getsarea(dev);
917 if (!dev_priv->sarea) {
918 DRM_ERROR("could not find sarea!\n");
919 radeon_do_cleanup_cp(dev);
923 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
924 if (!dev_priv->cp_ring) {
925 DRM_ERROR("could not find cp ring region!\n");
926 radeon_do_cleanup_cp(dev);
929 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
930 if (!dev_priv->ring_rptr) {
931 DRM_ERROR("could not find ring read pointer!\n");
932 radeon_do_cleanup_cp(dev);
935 dev->agp_buffer_token = init->buffers_offset;
936 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
937 if (!dev->agp_buffer_map) {
938 DRM_ERROR("could not find dma buffer region!\n");
939 radeon_do_cleanup_cp(dev);
943 if (init->gart_textures_offset) {
944 dev_priv->gart_textures =
945 drm_core_findmap(dev, init->gart_textures_offset);
946 if (!dev_priv->gart_textures) {
947 DRM_ERROR("could not find GART texture region!\n");
948 radeon_do_cleanup_cp(dev);
953 dev_priv->sarea_priv =
954 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
955 init->sarea_priv_offset);
958 if (dev_priv->flags & RADEON_IS_AGP) {
959 drm_core_ioremap(dev_priv->cp_ring, dev);
960 drm_core_ioremap(dev_priv->ring_rptr, dev);
961 drm_core_ioremap(dev->agp_buffer_map, dev);
962 if (!dev_priv->cp_ring->handle ||
963 !dev_priv->ring_rptr->handle ||
964 !dev->agp_buffer_map->handle) {
965 DRM_ERROR("could not find ioremap agp regions!\n");
966 radeon_do_cleanup_cp(dev);
972 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
973 dev_priv->ring_rptr->handle =
974 (void *)dev_priv->ring_rptr->offset;
975 dev->agp_buffer_map->handle =
976 (void *)dev->agp_buffer_map->offset;
978 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
979 dev_priv->cp_ring->handle);
980 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
981 dev_priv->ring_rptr->handle);
982 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
983 dev->agp_buffer_map->handle);
986 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
988 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
989 - dev_priv->fb_location;
991 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
992 ((dev_priv->front_offset
993 + dev_priv->fb_location) >> 10));
995 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
996 ((dev_priv->back_offset
997 + dev_priv->fb_location) >> 10));
999 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1000 ((dev_priv->depth_offset
1001 + dev_priv->fb_location) >> 10));
1003 dev_priv->gart_size = init->gart_size;
1005 /* New let's set the memory map ... */
1006 if (dev_priv->new_memmap) {
1009 DRM_INFO("Setting GART location based on new memory map\n");
1011 /* If using AGP, try to locate the AGP aperture at the same
1012 * location in the card and on the bus, though we have to
1016 if (dev_priv->flags & RADEON_IS_AGP) {
1017 base = dev->agp->base;
1018 /* Check if valid */
1019 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1020 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1021 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1027 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1029 base = dev_priv->fb_location + dev_priv->fb_size;
1030 if (base < dev_priv->fb_location ||
1031 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1032 base = dev_priv->fb_location
1033 - dev_priv->gart_size;
1035 dev_priv->gart_vm_start = base & 0xffc00000u;
1036 if (dev_priv->gart_vm_start != base)
1037 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1038 base, dev_priv->gart_vm_start);
1040 DRM_INFO("Setting GART location based on old memory map\n");
1041 dev_priv->gart_vm_start = dev_priv->fb_location +
1042 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1046 if (dev_priv->flags & RADEON_IS_AGP)
1047 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1049 + dev_priv->gart_vm_start);
1052 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1053 - (unsigned long)dev->sg->virtual
1054 + dev_priv->gart_vm_start);
1056 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1057 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1058 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1059 dev_priv->gart_buffers_offset);
1061 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1062 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1063 + init->ring_size / sizeof(u32));
1064 dev_priv->ring.size = init->ring_size;
1065 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1067 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1068 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1070 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1071 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1072 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1074 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1077 if (dev_priv->flags & RADEON_IS_AGP) {
1078 /* Turn off PCI GART */
1079 radeon_set_pcigart(dev_priv, 0);
1083 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1084 /* if we have an offset set from userspace */
1085 if (dev_priv->pcigart_offset_set) {
1086 dev_priv->gart_info.bus_addr =
1087 dev_priv->pcigart_offset + dev_priv->fb_location;
1088 dev_priv->gart_info.mapping.offset =
1089 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1090 dev_priv->gart_info.mapping.size =
1091 dev_priv->gart_info.table_size;
1093 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1094 dev_priv->gart_info.addr =
1095 dev_priv->gart_info.mapping.handle;
1097 if (dev_priv->flags & RADEON_IS_PCIE)
1098 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1100 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1101 dev_priv->gart_info.gart_table_location =
1104 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1105 dev_priv->gart_info.addr,
1106 dev_priv->pcigart_offset);
1108 if (dev_priv->flags & RADEON_IS_IGPGART)
1109 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1111 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1112 dev_priv->gart_info.gart_table_location =
1114 dev_priv->gart_info.addr = NULL;
1115 dev_priv->gart_info.bus_addr = 0;
1116 if (dev_priv->flags & RADEON_IS_PCIE) {
1118 ("Cannot use PCI Express without GART in FB memory\n");
1119 radeon_do_cleanup_cp(dev);
1124 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1125 DRM_ERROR("failed to init PCI GART!\n");
1126 radeon_do_cleanup_cp(dev);
1130 /* Turn on PCI GART */
1131 radeon_set_pcigart(dev_priv, 1);
1134 radeon_cp_load_microcode(dev_priv);
1135 radeon_cp_init_ring_buffer(dev, dev_priv);
1137 dev_priv->last_buf = 0;
1139 radeon_do_engine_reset(dev);
1140 radeon_test_writeback(dev_priv);
1145 static int radeon_do_cleanup_cp(struct drm_device * dev)
1147 drm_radeon_private_t *dev_priv = dev->dev_private;
1150 /* Make sure interrupts are disabled here because the uninstall ioctl
1151 * may not have been called from userspace and after dev_private
1152 * is freed, it's too late.
1154 if (dev->irq_enabled)
1155 drm_irq_uninstall(dev);
1158 if (dev_priv->flags & RADEON_IS_AGP) {
1159 if (dev_priv->cp_ring != NULL) {
1160 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1161 dev_priv->cp_ring = NULL;
1163 if (dev_priv->ring_rptr != NULL) {
1164 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1165 dev_priv->ring_rptr = NULL;
1167 if (dev->agp_buffer_map != NULL) {
1168 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1169 dev->agp_buffer_map = NULL;
1175 if (dev_priv->gart_info.bus_addr) {
1176 /* Turn off PCI GART */
1177 radeon_set_pcigart(dev_priv, 0);
1178 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1179 DRM_ERROR("failed to cleanup PCI GART!\n");
1182 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1184 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1185 dev_priv->gart_info.addr = 0;
1188 /* only clear to the start of flags */
1189 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1194 /* This code will reinit the Radeon CP hardware after a resume from disc.
1195 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1196 * here we make sure that all Radeon hardware initialisation is re-done without
1197 * affecting running applications.
1199 * Charl P. Botha <http://cpbotha.net>
1201 static int radeon_do_resume_cp(struct drm_device * dev)
1203 drm_radeon_private_t *dev_priv = dev->dev_private;
1206 DRM_ERROR("Called with no initialization\n");
1210 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1213 if (dev_priv->flags & RADEON_IS_AGP) {
1214 /* Turn off PCI GART */
1215 radeon_set_pcigart(dev_priv, 0);
1219 /* Turn on PCI GART */
1220 radeon_set_pcigart(dev_priv, 1);
1223 radeon_cp_load_microcode(dev_priv);
1224 radeon_cp_init_ring_buffer(dev, dev_priv);
1226 radeon_do_engine_reset(dev);
1228 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1233 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1235 drm_radeon_init_t *init = data;
1237 LOCK_TEST_WITH_RETURN(dev, file_priv);
1239 if (init->func == RADEON_INIT_R300_CP)
1240 r300_init_reg_flags(dev);
1242 switch (init->func) {
1243 case RADEON_INIT_CP:
1244 case RADEON_INIT_R200_CP:
1245 case RADEON_INIT_R300_CP:
1246 return radeon_do_init_cp(dev, init);
1247 case RADEON_CLEANUP_CP:
1248 return radeon_do_cleanup_cp(dev);
1254 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1256 drm_radeon_private_t *dev_priv = dev->dev_private;
1259 LOCK_TEST_WITH_RETURN(dev, file_priv);
1261 if (dev_priv->cp_running) {
1262 DRM_DEBUG("while CP running\n");
1265 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1266 DRM_DEBUG("called with bogus CP mode (%d)\n",
1271 radeon_do_cp_start(dev_priv);
1276 /* Stop the CP. The engine must have been idled before calling this
1279 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1281 drm_radeon_private_t *dev_priv = dev->dev_private;
1282 drm_radeon_cp_stop_t *stop = data;
1286 LOCK_TEST_WITH_RETURN(dev, file_priv);
1288 if (!dev_priv->cp_running)
1291 /* Flush any pending CP commands. This ensures any outstanding
1292 * commands are exectuted by the engine before we turn it off.
1295 radeon_do_cp_flush(dev_priv);
1298 /* If we fail to make the engine go idle, we return an error
1299 * code so that the DRM ioctl wrapper can try again.
1302 ret = radeon_do_cp_idle(dev_priv);
1307 /* Finally, we can turn off the CP. If the engine isn't idle,
1308 * we will get some dropped triangles as they won't be fully
1309 * rendered before the CP is shut down.
1311 radeon_do_cp_stop(dev_priv);
1313 /* Reset the engine */
1314 radeon_do_engine_reset(dev);
1319 void radeon_do_release(struct drm_device * dev)
1321 drm_radeon_private_t *dev_priv = dev->dev_private;
1325 if (dev_priv->cp_running) {
1327 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1328 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1332 tsleep(&ret, PZERO, "rdnrel", 1);
1335 radeon_do_cp_stop(dev_priv);
1336 radeon_do_engine_reset(dev);
1339 /* Disable *all* interrupts */
1340 if (dev_priv->mmio) /* remove this after permanent addmaps */
1341 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1343 if (dev_priv->mmio) { /* remove all surfaces */
1344 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1345 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1346 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1348 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1353 /* Free memory heap structures */
1354 radeon_mem_takedown(&(dev_priv->gart_heap));
1355 radeon_mem_takedown(&(dev_priv->fb_heap));
1357 /* deallocate kernel resources */
1358 radeon_do_cleanup_cp(dev);
1362 /* Just reset the CP ring. Called as part of an X Server engine reset.
1364 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1366 drm_radeon_private_t *dev_priv = dev->dev_private;
1369 LOCK_TEST_WITH_RETURN(dev, file_priv);
1372 DRM_DEBUG("called before init done\n");
1376 radeon_do_cp_reset(dev_priv);
1378 /* The CP is no longer running after an engine reset */
1379 dev_priv->cp_running = 0;
1384 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1386 drm_radeon_private_t *dev_priv = dev->dev_private;
1389 LOCK_TEST_WITH_RETURN(dev, file_priv);
1391 return radeon_do_cp_idle(dev_priv);
1394 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1396 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1399 return radeon_do_resume_cp(dev);
1402 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1406 LOCK_TEST_WITH_RETURN(dev, file_priv);
1408 return radeon_do_engine_reset(dev);
1411 /* ================================================================
1415 /* KW: Deprecated to say the least:
1417 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1422 /* ================================================================
1423 * Freelist management
1426 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1427 * bufs until freelist code is used. Note this hides a problem with
1428 * the scratch register * (used to keep track of last buffer
1429 * completed) being written to before * the last buffer has actually
1430 * completed rendering.
1432 * KW: It's also a good way to find free buffers quickly.
1434 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1435 * sleep. However, bugs in older versions of radeon_accel.c mean that
1436 * we essentially have to do this, else old clients will break.
1438 * However, it does leave open a potential deadlock where all the
1439 * buffers are held by other clients, which can't release them because
1440 * they can't get the lock.
1443 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1445 struct drm_device_dma *dma = dev->dma;
1446 drm_radeon_private_t *dev_priv = dev->dev_private;
1447 drm_radeon_buf_priv_t *buf_priv;
1448 struct drm_buf *buf;
1452 if (++dev_priv->last_buf >= dma->buf_count)
1453 dev_priv->last_buf = 0;
1455 start = dev_priv->last_buf;
1457 for (t = 0; t < dev_priv->usec_timeout; t++) {
1458 u32 done_age = GET_SCRATCH(1);
1459 DRM_DEBUG("done_age = %d\n", done_age);
1460 for (i = start; i < dma->buf_count; i++) {
1461 buf = dma->buflist[i];
1462 buf_priv = buf->dev_private;
1463 if (buf->file_priv == NULL || (buf->pending &&
1466 dev_priv->stats.requested_bufs++;
1475 dev_priv->stats.freelist_loops++;
1479 DRM_DEBUG("returning NULL!\n");
1484 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1486 struct drm_device_dma *dma = dev->dma;
1487 drm_radeon_private_t *dev_priv = dev->dev_private;
1488 drm_radeon_buf_priv_t *buf_priv;
1489 struct drm_buf *buf;
1492 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1494 if (++dev_priv->last_buf >= dma->buf_count)
1495 dev_priv->last_buf = 0;
1497 start = dev_priv->last_buf;
1498 dev_priv->stats.freelist_loops++;
1500 for (t = 0; t < 2; t++) {
1501 for (i = start; i < dma->buf_count; i++) {
1502 buf = dma->buflist[i];
1503 buf_priv = buf->dev_private;
1504 if (buf->file_priv == 0 || (buf->pending &&
1507 dev_priv->stats.requested_bufs++;
1519 void radeon_freelist_reset(struct drm_device * dev)
1521 struct drm_device_dma *dma = dev->dma;
1522 drm_radeon_private_t *dev_priv = dev->dev_private;
1525 dev_priv->last_buf = 0;
1526 for (i = 0; i < dma->buf_count; i++) {
1527 struct drm_buf *buf = dma->buflist[i];
1528 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1533 /* ================================================================
1534 * CP command submission
1537 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1539 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1541 u32 last_head = GET_RING_HEAD(dev_priv);
1543 for (i = 0; i < dev_priv->usec_timeout; i++) {
1544 u32 head = GET_RING_HEAD(dev_priv);
1546 ring->space = (head - ring->tail) * sizeof(u32);
1547 if (ring->space <= 0)
1548 ring->space += ring->size;
1549 if (ring->space > n)
1552 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1554 if (head != last_head)
1561 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1562 #if RADEON_FIFO_DEBUG
1563 radeon_status(dev_priv);
1564 DRM_ERROR("failed!\n");
1569 static int radeon_cp_get_buffers(struct drm_device *dev,
1570 struct drm_file *file_priv,
1574 struct drm_buf *buf;
1576 for (i = d->granted_count; i < d->request_count; i++) {
1577 buf = radeon_freelist_get(dev);
1579 return -EBUSY; /* NOTE: broken client */
1581 buf->file_priv = file_priv;
1583 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1586 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1587 sizeof(buf->total)))
1595 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1597 struct drm_device_dma *dma = dev->dma;
1599 struct drm_dma *d = data;
1601 LOCK_TEST_WITH_RETURN(dev, file_priv);
1603 /* Please don't send us buffers.
1605 if (d->send_count != 0) {
1606 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1607 DRM_CURRENTPID, d->send_count);
1611 /* We'll send you buffers.
1613 if (d->request_count < 0 || d->request_count > dma->buf_count) {
1614 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1615 DRM_CURRENTPID, d->request_count, dma->buf_count);
1619 d->granted_count = 0;
1621 if (d->request_count) {
1622 ret = radeon_cp_get_buffers(dev, file_priv, d);
1628 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1630 drm_radeon_private_t *dev_priv;
1633 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1634 if (dev_priv == NULL)
1637 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1638 dev->dev_private = (void *)dev_priv;
1639 dev_priv->flags = flags;
1641 switch (flags & RADEON_FAMILY_MASK) {
1653 dev_priv->flags |= RADEON_HAS_HIERZ;
1656 /* all other chips have no hierarchical z buffer */
1660 if (drm_device_is_agp(dev))
1661 dev_priv->flags |= RADEON_IS_AGP;
1662 else if (drm_device_is_pcie(dev))
1663 dev_priv->flags |= RADEON_IS_PCIE;
1665 dev_priv->flags |= RADEON_IS_PCI;
1667 DRM_DEBUG("%s card detected\n",
1668 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1672 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1673 * have to find them.
1675 int radeon_driver_firstopen(struct drm_device *dev)
1678 drm_local_map_t *map;
1679 drm_radeon_private_t *dev_priv = dev->dev_private;
1681 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1683 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1684 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1685 _DRM_READ_ONLY, &dev_priv->mmio);
1689 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1690 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1691 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1692 _DRM_WRITE_COMBINING, &map);
1699 int radeon_driver_unload(struct drm_device *dev)
1701 drm_radeon_private_t *dev_priv = dev->dev_private;
1704 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1706 dev->dev_private = NULL;