1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
34 /* General customization:
37 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
39 #define DRIVER_NAME "radeon"
40 #define DRIVER_DESC "ATI Radeon"
41 #define DRIVER_DATE "20080528"
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
71 * clients use to tell the DRM where they think the framebuffer is
72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading).
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
85 * 1.17- Add initial support for R300 (3D).
86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
90 * 1.19- Add support for gart table in FB memory and PCIE r300
91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
94 * 1.23- Add new radeon memory map work from benh
95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
98 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART
100 * 1.28- Add support for VBL on CRTC2
101 * 1.29- R500 3D cmd buffer support
103 #define DRIVER_MAJOR 1
104 #define DRIVER_MINOR 29
105 #define DRIVER_PATCHLEVEL 0
108 * Radeon chip families
137 enum radeon_cp_microcode_version {
146 enum radeon_chip_flags {
147 RADEON_FAMILY_MASK = 0x0000ffffUL,
148 RADEON_FLAGS_MASK = 0xffff0000UL,
149 RADEON_IS_MOBILITY = 0x00010000UL,
150 RADEON_IS_IGP = 0x00020000UL,
151 RADEON_SINGLE_CRTC = 0x00040000UL,
152 RADEON_IS_AGP = 0x00080000UL,
153 RADEON_HAS_HIERZ = 0x00100000UL,
154 RADEON_IS_PCIE = 0x00200000UL,
155 RADEON_NEW_MEMMAP = 0x00400000UL,
156 RADEON_IS_PCI = 0x00800000UL,
157 RADEON_IS_IGPGART = 0x01000000UL,
160 #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
161 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
162 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
164 typedef struct drm_radeon_freelist {
167 struct drm_radeon_freelist *next;
168 struct drm_radeon_freelist *prev;
169 } drm_radeon_freelist_t;
171 typedef struct drm_radeon_ring_buffer {
177 int rptr_update; /* Double Words */
178 int rptr_update_l2qw; /* log2 Quad Words */
180 int fetch_size; /* Double Words */
181 int fetch_size_l2ow; /* log2 Oct Words */
188 } drm_radeon_ring_buffer_t;
190 typedef struct drm_radeon_depth_clear_t {
192 u32 rb3d_zstencilcntl;
194 } drm_radeon_depth_clear_t;
196 struct drm_radeon_driver_file_fields {
197 int64_t radeon_fb_delta;
201 struct mem_block *next;
202 struct mem_block *prev;
205 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
208 struct radeon_surface {
215 struct radeon_virt_surface {
220 struct drm_file *file_priv;
223 typedef struct drm_radeon_private {
224 drm_radeon_ring_buffer_t ring;
225 drm_radeon_sarea_t *sarea_priv;
233 unsigned long gart_buffers_offset;
238 drm_radeon_freelist_t *head;
239 drm_radeon_freelist_t *tail;
241 volatile u32 *scratch;
246 int microcode_version;
250 int freelist_timeouts;
253 int last_frame_reads;
254 int last_clear_reads;
263 unsigned int front_offset;
264 unsigned int front_pitch;
265 unsigned int back_offset;
266 unsigned int back_pitch;
269 unsigned int depth_offset;
270 unsigned int depth_pitch;
272 u32 front_pitch_offset;
273 u32 back_pitch_offset;
274 u32 depth_pitch_offset;
276 drm_radeon_depth_clear_t depth_clear;
278 unsigned long ring_offset;
279 unsigned long ring_rptr_offset;
280 unsigned long buffers_offset;
281 unsigned long gart_textures_offset;
283 drm_local_map_t *sarea;
284 drm_local_map_t *mmio;
285 drm_local_map_t *cp_ring;
286 drm_local_map_t *ring_rptr;
287 drm_local_map_t *gart_textures;
289 struct mem_block *gart_heap;
290 struct mem_block *fb_heap;
293 wait_queue_head_t swi_queue;
294 atomic_t swi_emitted;
296 uint32_t irq_enable_reg;
298 uint32_t r500_disp_irq_reg;
300 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
301 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
303 unsigned long pcigart_offset;
304 unsigned int pcigart_offset_set;
305 struct drm_ati_pcigart_info gart_info;
309 /* starting from here on, data is preserved accross an open */
310 uint32_t flags; /* see radeon_chip_flags */
311 unsigned long fb_aper_offset;
314 } drm_radeon_private_t;
316 typedef struct drm_radeon_buf_priv {
318 } drm_radeon_buf_priv_t;
320 typedef struct drm_radeon_kcmd_buffer {
324 struct drm_clip_rect __user *boxes;
325 } drm_radeon_kcmd_buffer_t;
327 extern int radeon_no_wb;
328 extern struct drm_ioctl_desc radeon_ioctls[];
329 extern int radeon_max_ioctl;
331 /* Check whether the given hardware address is inside the framebuffer or the
334 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
337 u32 fb_start = dev_priv->fb_location;
338 u32 fb_end = fb_start + dev_priv->fb_size - 1;
339 u32 gart_start = dev_priv->gart_vm_start;
340 u32 gart_end = gart_start + dev_priv->gart_size - 1;
342 return ((off >= fb_start && off <= fb_end) ||
343 (off >= gart_start && off <= gart_end));
347 extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
348 extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
349 extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
350 extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
351 extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
352 extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
353 extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
354 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
355 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
356 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
358 extern void radeon_freelist_reset(struct drm_device * dev);
359 extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
361 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
363 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
365 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
366 extern int radeon_presetup(struct drm_device *dev);
367 extern int radeon_driver_postcleanup(struct drm_device *dev);
369 extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
370 extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
371 extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
372 extern void radeon_mem_takedown(struct mem_block **heap);
373 extern void radeon_mem_release(struct drm_file *file_priv,
374 struct mem_block *heap);
377 extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
378 extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
380 extern void radeon_do_release(struct drm_device * dev);
381 extern int radeon_driver_vblank_wait(struct drm_device * dev,
382 unsigned int *sequence);
383 extern int radeon_driver_vblank_wait2(struct drm_device * dev,
384 unsigned int *sequence);
385 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
386 extern void radeon_driver_irq_preinstall(struct drm_device * dev);
387 extern void radeon_driver_irq_postinstall(struct drm_device * dev);
388 extern void radeon_driver_irq_uninstall(struct drm_device * dev);
389 extern int radeon_vblank_crtc_get(struct drm_device *dev);
390 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
392 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
393 extern int radeon_driver_unload(struct drm_device *dev);
394 extern int radeon_driver_firstopen(struct drm_device *dev);
395 extern void radeon_driver_preclose(struct drm_device * dev, struct drm_file *file_priv);
396 extern void radeon_driver_postclose(struct drm_device * dev, struct drm_file * filp);
397 extern void radeon_driver_lastclose(struct drm_device * dev);
398 extern int radeon_driver_open(struct drm_device * dev, struct drm_file * filp_priv);
399 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
403 extern void r300_init_reg_flags(struct drm_device *dev);
405 extern int r300_do_cp_cmdbuf(struct drm_device * dev,
406 struct drm_file *file_priv,
407 drm_radeon_kcmd_buffer_t * cmdbuf);
409 /* Flags for stats.boxes
411 #define RADEON_BOX_DMA_IDLE 0x1
412 #define RADEON_BOX_RING_FULL 0x2
413 #define RADEON_BOX_FLIP 0x4
414 #define RADEON_BOX_WAIT_IDLE 0x8
415 #define RADEON_BOX_TEXTURE_LOAD 0x10
417 /* Register definitions, register access macros and drmAddMap constants
418 * for Radeon kernel driver.
421 #define RADEON_AGP_COMMAND 0x0f60
422 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
423 # define RADEON_AGP_ENABLE (1<<8)
424 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
425 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
426 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
427 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
428 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
429 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
430 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
432 #define RADEON_BUS_CNTL 0x0030
433 # define RADEON_BUS_MASTER_DIS (1 << 6)
435 #define RADEON_CLOCK_CNTL_DATA 0x000c
436 # define RADEON_PLL_WR_EN (1 << 7)
437 #define RADEON_CLOCK_CNTL_INDEX 0x0008
438 #define RADEON_CONFIG_APER_SIZE 0x0108
439 #define RADEON_CONFIG_MEMSIZE 0x00f8
440 #define RADEON_CRTC_OFFSET 0x0224
441 #define RADEON_CRTC_OFFSET_CNTL 0x0228
442 # define RADEON_CRTC_TILE_EN (1 << 15)
443 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
444 #define RADEON_CRTC2_OFFSET 0x0324
445 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
447 #define RADEON_PCIE_INDEX 0x0030
448 #define RADEON_PCIE_DATA 0x0034
449 #define RADEON_PCIE_TX_GART_CNTL 0x10
450 # define RADEON_PCIE_TX_GART_EN (1 << 0)
451 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
452 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
453 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
454 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
455 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
456 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
457 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
458 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
459 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
460 #define RADEON_PCIE_TX_GART_BASE 0x13
461 #define RADEON_PCIE_TX_GART_START_LO 0x14
462 #define RADEON_PCIE_TX_GART_START_HI 0x15
463 #define RADEON_PCIE_TX_GART_END_LO 0x16
464 #define RADEON_PCIE_TX_GART_END_HI 0x17
466 #define RS480_NB_MC_INDEX 0x168
467 # define RS480_NB_MC_IND_WR_EN (1 << 8)
468 #define RS480_NB_MC_DATA 0x16c
470 #define RS690_MC_INDEX 0x78
471 # define RS690_MC_INDEX_MASK 0x1ff
472 # define RS690_MC_INDEX_WR_EN (1 << 9)
473 # define RS690_MC_INDEX_WR_ACK 0x7f
474 #define RS690_MC_DATA 0x7c
476 /* MC indirect registers */
477 #define RS480_MC_MISC_CNTL 0x18
478 # define RS480_DISABLE_GTW (1 << 1)
479 /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
480 # define RS480_GART_INDEX_REG_EN (1 << 12)
481 # define RS690_BLOCK_GFX_D3_EN (1 << 14)
482 #define RS480_K8_FB_LOCATION 0x1e
483 #define RS480_GART_FEATURE_ID 0x2b
484 # define RS480_HANG_EN (1 << 11)
485 # define RS480_TLB_ENABLE (1 << 18)
486 # define RS480_P2P_ENABLE (1 << 19)
487 # define RS480_GTW_LAC_EN (1 << 25)
488 # define RS480_2LEVEL_GART (0 << 30)
489 # define RS480_1LEVEL_GART (1 << 30)
490 # define RS480_PDC_EN (1 << 31)
491 #define RS480_GART_BASE 0x2c
492 #define RS480_GART_CACHE_CNTRL 0x2e
493 # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
494 #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
495 # define RS480_GART_EN (1 << 0)
496 # define RS480_VA_SIZE_32MB (0 << 1)
497 # define RS480_VA_SIZE_64MB (1 << 1)
498 # define RS480_VA_SIZE_128MB (2 << 1)
499 # define RS480_VA_SIZE_256MB (3 << 1)
500 # define RS480_VA_SIZE_512MB (4 << 1)
501 # define RS480_VA_SIZE_1GB (5 << 1)
502 # define RS480_VA_SIZE_2GB (6 << 1)
503 #define RS480_AGP_MODE_CNTL 0x39
504 # define RS480_POST_GART_Q_SIZE (1 << 18)
505 # define RS480_NONGART_SNOOP (1 << 19)
506 # define RS480_AGP_RD_BUF_SIZE (1 << 20)
507 # define RS480_REQ_TYPE_SNOOP_SHIFT 22
508 # define RS480_REQ_TYPE_SNOOP_MASK 0x3
509 # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
510 #define RS480_MC_MISC_UMA_CNTL 0x5f
511 #define RS480_MC_MCLK_CNTL 0x7a
512 #define RS480_MC_UMA_DUALCH_CNTL 0x86
514 #define RS690_MC_FB_LOCATION 0x100
515 #define RS690_MC_AGP_LOCATION 0x101
516 #define RS690_MC_AGP_BASE 0x102
517 #define RS690_MC_AGP_BASE_2 0x103
519 #define R520_MC_IND_INDEX 0x70
520 #define R520_MC_IND_WR_EN (1 << 24)
521 #define R520_MC_IND_DATA 0x74
523 #define RV515_MC_FB_LOCATION 0x01
524 #define RV515_MC_AGP_LOCATION 0x02
526 #define R520_MC_FB_LOCATION 0x04
527 #define R520_MC_AGP_LOCATION 0x05
529 #define RADEON_MPP_TB_CONFIG 0x01c0
530 #define RADEON_MEM_CNTL 0x0140
531 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
532 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
533 #define RS480_AGP_BASE_2 0x0164
534 #define RADEON_AGP_BASE 0x0170
536 /* pipe config regs */
537 #define R400_GB_PIPE_SELECT 0x402c
538 #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
539 #define R500_SU_REG_DEST 0x42c8
540 #define R300_GB_TILE_CONFIG 0x4018
541 # define R300_ENABLE_TILING (1 << 0)
542 # define R300_PIPE_COUNT_RV350 (0 << 1)
543 # define R300_PIPE_COUNT_R300 (3 << 1)
544 # define R300_PIPE_COUNT_R420_3P (6 << 1)
545 # define R300_PIPE_COUNT_R420 (7 << 1)
546 # define R300_TILE_SIZE_8 (0 << 4)
547 # define R300_TILE_SIZE_16 (1 << 4)
548 # define R300_TILE_SIZE_32 (2 << 4)
549 # define R300_SUBPIXEL_1_12 (0 << 16)
550 # define R300_SUBPIXEL_1_16 (1 << 16)
551 #define R300_DST_PIPE_CONFIG 0x170c
552 # define R300_PIPE_AUTO_CONFIG (1 << 31)
553 #define R300_RB2D_DSTCACHE_MODE 0x3428
554 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
555 # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
557 #define RADEON_RB3D_COLOROFFSET 0x1c40
558 #define RADEON_RB3D_COLORPITCH 0x1c48
560 #define RADEON_SRC_X_Y 0x1590
562 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
563 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
564 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
565 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
566 # define RADEON_GMC_BRUSH_NONE (15 << 4)
567 # define RADEON_GMC_DST_16BPP (4 << 8)
568 # define RADEON_GMC_DST_24BPP (5 << 8)
569 # define RADEON_GMC_DST_32BPP (6 << 8)
570 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
571 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
572 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
573 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
574 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
575 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
576 # define RADEON_ROP3_S 0x00cc0000
577 # define RADEON_ROP3_P 0x00f00000
578 #define RADEON_DP_WRITE_MASK 0x16cc
579 #define RADEON_SRC_PITCH_OFFSET 0x1428
580 #define RADEON_DST_PITCH_OFFSET 0x142c
581 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
582 # define RADEON_DST_TILE_LINEAR (0 << 30)
583 # define RADEON_DST_TILE_MACRO (1 << 30)
584 # define RADEON_DST_TILE_MICRO (2 << 30)
585 # define RADEON_DST_TILE_BOTH (3 << 30)
587 #define RADEON_SCRATCH_REG0 0x15e0
588 #define RADEON_SCRATCH_REG1 0x15e4
589 #define RADEON_SCRATCH_REG2 0x15e8
590 #define RADEON_SCRATCH_REG3 0x15ec
591 #define RADEON_SCRATCH_REG4 0x15f0
592 #define RADEON_SCRATCH_REG5 0x15f4
593 #define RADEON_SCRATCH_UMSK 0x0770
594 #define RADEON_SCRATCH_ADDR 0x0774
596 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
598 #define GET_SCRATCH( x ) (dev_priv->writeback_works \
599 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
600 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
602 #define RADEON_GEN_INT_CNTL 0x0040
603 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
604 # define RADEON_CRTC2_VBLANK_MASK (1 << 9)
605 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
606 # define RADEON_SW_INT_ENABLE (1 << 25)
608 #define RADEON_GEN_INT_STATUS 0x0044
609 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
610 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
611 # define RADEON_CRTC2_VBLANK_STAT (1 << 9)
612 # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
613 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
614 # define RADEON_SW_INT_TEST (1 << 25)
615 # define RADEON_SW_INT_TEST_ACK (1 << 25)
616 # define RADEON_SW_INT_FIRE (1 << 26)
618 #define RADEON_HOST_PATH_CNTL 0x0130
619 # define RADEON_HDP_SOFT_RESET (1 << 26)
620 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
621 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
623 #define RADEON_ISYNC_CNTL 0x1724
624 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
625 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
626 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
627 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
628 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
629 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
631 #define RADEON_RBBM_GUICNTL 0x172c
632 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
633 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
634 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
635 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
637 #define RADEON_MC_AGP_LOCATION 0x014c
638 #define RADEON_MC_FB_LOCATION 0x0148
639 #define RADEON_MCLK_CNTL 0x0012
640 # define RADEON_FORCEON_MCLKA (1 << 16)
641 # define RADEON_FORCEON_MCLKB (1 << 17)
642 # define RADEON_FORCEON_YCLKA (1 << 18)
643 # define RADEON_FORCEON_YCLKB (1 << 19)
644 # define RADEON_FORCEON_MC (1 << 20)
645 # define RADEON_FORCEON_AIC (1 << 21)
647 #define RADEON_PP_BORDER_COLOR_0 0x1d40
648 #define RADEON_PP_BORDER_COLOR_1 0x1d44
649 #define RADEON_PP_BORDER_COLOR_2 0x1d48
650 #define RADEON_PP_CNTL 0x1c38
651 # define RADEON_SCISSOR_ENABLE (1 << 1)
652 #define RADEON_PP_LUM_MATRIX 0x1d00
653 #define RADEON_PP_MISC 0x1c14
654 #define RADEON_PP_ROT_MATRIX_0 0x1d58
655 #define RADEON_PP_TXFILTER_0 0x1c54
656 #define RADEON_PP_TXOFFSET_0 0x1c5c
657 #define RADEON_PP_TXFILTER_1 0x1c6c
658 #define RADEON_PP_TXFILTER_2 0x1c84
660 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
661 # define RADEON_RB2D_DC_FLUSH (3 << 0)
662 # define RADEON_RB2D_DC_FREE (3 << 2)
663 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
664 # define RADEON_RB2D_DC_BUSY (1 << 31)
665 #define RADEON_RB3D_CNTL 0x1c3c
666 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
667 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
668 # define RADEON_DITHER_ENABLE (1 << 2)
669 # define RADEON_ROUND_ENABLE (1 << 3)
670 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
671 # define RADEON_DITHER_INIT (1 << 5)
672 # define RADEON_ROP_ENABLE (1 << 6)
673 # define RADEON_STENCIL_ENABLE (1 << 7)
674 # define RADEON_Z_ENABLE (1 << 8)
675 # define RADEON_ZBLOCK16 (1 << 15)
676 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
677 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
678 #define RADEON_RB3D_DEPTHPITCH 0x1c28
679 #define RADEON_RB3D_PLANEMASK 0x1d84
680 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
681 #define RADEON_RB3D_ZCACHE_MODE 0x3250
682 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
683 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
684 # define RADEON_RB3D_ZC_FREE (1 << 2)
685 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
686 # define RADEON_RB3D_ZC_BUSY (1 << 31)
687 #define R300_ZB_ZCACHE_CTLSTAT 0x4f18
688 # define R300_ZC_FLUSH (1 << 0)
689 # define R300_ZC_FREE (1 << 1)
690 # define R300_ZC_FLUSH_ALL 0x3
691 # define R300_ZC_BUSY (1 << 31)
692 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
693 # define RADEON_RB3D_DC_FLUSH (3 << 0)
694 # define RADEON_RB3D_DC_FREE (3 << 2)
695 # define RADEON_RB3D_DC_FLUSH_ALL 0xf
696 # define RADEON_RB3D_DC_BUSY (1 << 31)
697 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
698 # define R300_RB3D_DC_FINISH (1 << 4)
699 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
700 # define RADEON_Z_TEST_MASK (7 << 4)
701 # define RADEON_Z_TEST_ALWAYS (7 << 4)
702 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
703 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
704 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
705 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
706 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
707 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
708 # define RADEON_FORCE_Z_DIRTY (1 << 29)
709 # define RADEON_Z_WRITE_ENABLE (1 << 30)
710 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
711 #define RADEON_RBBM_SOFT_RESET 0x00f0
712 # define RADEON_SOFT_RESET_CP (1 << 0)
713 # define RADEON_SOFT_RESET_HI (1 << 1)
714 # define RADEON_SOFT_RESET_SE (1 << 2)
715 # define RADEON_SOFT_RESET_RE (1 << 3)
716 # define RADEON_SOFT_RESET_PP (1 << 4)
717 # define RADEON_SOFT_RESET_E2 (1 << 5)
718 # define RADEON_SOFT_RESET_RB (1 << 6)
719 # define RADEON_SOFT_RESET_HDP (1 << 7)
721 * 6:0 Available slots in the FIFO
722 * 8 Host Interface active
723 * 9 CP request active
724 * 10 FIFO request active
725 * 11 Host Interface retry active
727 * 13 FIFO retry active
728 * 14 FIFO pipeline busy
729 * 15 Event engine busy
730 * 16 CP command stream busy
732 * 18 2D portion of render backend busy
733 * 20 3D setup engine busy
735 * 27 CBA 2D engine busy
736 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
737 * command stream queue not empty or Ring Buffer not empty
739 #define RADEON_RBBM_STATUS 0x0e40
740 /* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
741 /* #define RADEON_RBBM_STATUS 0x1740 */
742 /* bits 6:0 are dword slots available in the cmd fifo */
743 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
744 # define RADEON_HIRQ_ON_RBB (1 << 8)
745 # define RADEON_CPRQ_ON_RBB (1 << 9)
746 # define RADEON_CFRQ_ON_RBB (1 << 10)
747 # define RADEON_HIRQ_IN_RTBUF (1 << 11)
748 # define RADEON_CPRQ_IN_RTBUF (1 << 12)
749 # define RADEON_CFRQ_IN_RTBUF (1 << 13)
750 # define RADEON_PIPE_BUSY (1 << 14)
751 # define RADEON_ENG_EV_BUSY (1 << 15)
752 # define RADEON_CP_CMDSTRM_BUSY (1 << 16)
753 # define RADEON_E2_BUSY (1 << 17)
754 # define RADEON_RB2D_BUSY (1 << 18)
755 # define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
756 # define RADEON_VAP_BUSY (1 << 20)
757 # define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
758 # define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
759 # define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
760 # define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
761 # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
762 # define RADEON_GA_BUSY (1 << 26)
763 # define RADEON_CBA2D_BUSY (1 << 27)
764 # define RADEON_RBBM_ACTIVE (1 << 31)
765 #define RADEON_RE_LINE_PATTERN 0x1cd0
766 #define RADEON_RE_MISC 0x26c4
767 #define RADEON_RE_TOP_LEFT 0x26c0
768 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
769 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
770 #define RADEON_RE_STIPPLE_DATA 0x1ccc
772 #define RADEON_SCISSOR_TL_0 0x1cd8
773 #define RADEON_SCISSOR_BR_0 0x1cdc
774 #define RADEON_SCISSOR_TL_1 0x1ce0
775 #define RADEON_SCISSOR_BR_1 0x1ce4
776 #define RADEON_SCISSOR_TL_2 0x1ce8
777 #define RADEON_SCISSOR_BR_2 0x1cec
778 #define RADEON_SE_COORD_FMT 0x1c50
779 #define RADEON_SE_CNTL 0x1c4c
780 # define RADEON_FFACE_CULL_CW (0 << 0)
781 # define RADEON_BFACE_SOLID (3 << 1)
782 # define RADEON_FFACE_SOLID (3 << 3)
783 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
784 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
785 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
786 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
787 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
788 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
789 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
790 # define RADEON_FOG_SHADE_FLAT (1 << 14)
791 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
792 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
793 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
794 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
795 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
796 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
797 #define RADEON_SE_CNTL_STATUS 0x2140
798 #define RADEON_SE_LINE_WIDTH 0x1db8
799 #define RADEON_SE_VPORT_XSCALE 0x1d98
800 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
801 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
802 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
803 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
804 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
805 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
806 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
807 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
808 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
809 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
810 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
811 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
812 #define RADEON_SURFACE_CNTL 0x0b00
813 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
814 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
815 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
816 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
817 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
818 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
819 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
820 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
821 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
822 #define RADEON_SURFACE0_INFO 0x0b0c
823 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
824 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
825 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
826 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
827 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
828 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
829 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
830 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
831 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
832 #define RADEON_SURFACE1_INFO 0x0b1c
833 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
834 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
835 #define RADEON_SURFACE2_INFO 0x0b2c
836 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
837 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
838 #define RADEON_SURFACE3_INFO 0x0b3c
839 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
840 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
841 #define RADEON_SURFACE4_INFO 0x0b4c
842 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
843 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
844 #define RADEON_SURFACE5_INFO 0x0b5c
845 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
846 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
847 #define RADEON_SURFACE6_INFO 0x0b6c
848 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
849 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
850 #define RADEON_SURFACE7_INFO 0x0b7c
851 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
852 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
853 #define RADEON_SW_SEMAPHORE 0x013c
855 #define RADEON_WAIT_UNTIL 0x1720
856 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
857 # define RADEON_WAIT_2D_IDLE (1 << 14)
858 # define RADEON_WAIT_3D_IDLE (1 << 15)
859 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
860 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
861 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
863 #define RADEON_RB3D_ZMASKOFFSET 0x3234
864 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
865 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
866 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
869 #define RADEON_CP_ME_RAM_ADDR 0x07d4
870 #define RADEON_CP_ME_RAM_RADDR 0x07d8
871 #define RADEON_CP_ME_RAM_DATAH 0x07dc
872 #define RADEON_CP_ME_RAM_DATAL 0x07e0
874 #define RADEON_CP_RB_BASE 0x0700
875 #define RADEON_CP_RB_CNTL 0x0704
876 # define RADEON_BUF_SWAP_32BIT (2 << 16)
877 # define RADEON_RB_NO_UPDATE (1 << 27)
878 #define RADEON_CP_RB_RPTR_ADDR 0x070c
879 #define RADEON_CP_RB_RPTR 0x0710
880 #define RADEON_CP_RB_WPTR 0x0714
882 #define RADEON_CP_RB_WPTR_DELAY 0x0718
883 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
884 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
886 #define RADEON_CP_IB_BASE 0x0738
888 #define RADEON_CP_CSQ_CNTL 0x0740
889 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
890 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
891 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
892 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
893 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
894 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
895 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
897 #define RADEON_AIC_CNTL 0x01d0
898 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
899 #define RADEON_AIC_STAT 0x01d4
900 #define RADEON_AIC_PT_BASE 0x01d8
901 #define RADEON_AIC_LO_ADDR 0x01dc
902 #define RADEON_AIC_HI_ADDR 0x01e0
903 #define RADEON_AIC_TLB_ADDR 0x01e4
904 #define RADEON_AIC_TLB_DATA 0x01e8
906 /* CP command packets */
907 #define RADEON_CP_PACKET0 0x00000000
908 # define RADEON_ONE_REG_WR (1 << 15)
909 #define RADEON_CP_PACKET1 0x40000000
910 #define RADEON_CP_PACKET2 0x80000000
911 #define RADEON_CP_PACKET3 0xC0000000
912 # define RADEON_CP_NOP 0x00001000
913 # define RADEON_CP_NEXT_CHAR 0x00001900
914 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
915 # define RADEON_CP_SET_SCISSORS 0x00001E00
916 /* GEN_INDX_PRIM is unsupported starting with R300 */
917 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
918 # define RADEON_WAIT_FOR_IDLE 0x00002600
919 # define RADEON_3D_DRAW_VBUF 0x00002800
920 # define RADEON_3D_DRAW_IMMD 0x00002900
921 # define RADEON_3D_DRAW_INDX 0x00002A00
922 # define RADEON_CP_LOAD_PALETTE 0x00002C00
923 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
924 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
925 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
926 # define RADEON_3D_CLEAR_ZMASK 0x00003200
927 # define RADEON_CP_INDX_BUFFER 0x00003300
928 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
929 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
930 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
931 # define RADEON_3D_CLEAR_HIZ 0x00003700
932 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
933 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
934 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
935 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
936 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
938 #define RADEON_CP_PACKET_MASK 0xC0000000
939 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
940 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
941 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
942 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
944 #define RADEON_VTX_Z_PRESENT (1 << 31)
945 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
947 #define RADEON_PRIM_TYPE_NONE (0 << 0)
948 #define RADEON_PRIM_TYPE_POINT (1 << 0)
949 #define RADEON_PRIM_TYPE_LINE (2 << 0)
950 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
951 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
952 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
953 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
954 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
955 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
956 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
957 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
958 #define RADEON_PRIM_TYPE_MASK 0xf
959 #define RADEON_PRIM_WALK_IND (1 << 4)
960 #define RADEON_PRIM_WALK_LIST (2 << 4)
961 #define RADEON_PRIM_WALK_RING (3 << 4)
962 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
963 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
964 #define RADEON_MAOS_ENABLE (1 << 7)
965 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
966 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
967 #define RADEON_NUM_VERTICES_SHIFT 16
969 #define RADEON_COLOR_FORMAT_CI8 2
970 #define RADEON_COLOR_FORMAT_ARGB1555 3
971 #define RADEON_COLOR_FORMAT_RGB565 4
972 #define RADEON_COLOR_FORMAT_ARGB8888 6
973 #define RADEON_COLOR_FORMAT_RGB332 7
974 #define RADEON_COLOR_FORMAT_RGB8 9
975 #define RADEON_COLOR_FORMAT_ARGB4444 15
977 #define RADEON_TXFORMAT_I8 0
978 #define RADEON_TXFORMAT_AI88 1
979 #define RADEON_TXFORMAT_RGB332 2
980 #define RADEON_TXFORMAT_ARGB1555 3
981 #define RADEON_TXFORMAT_RGB565 4
982 #define RADEON_TXFORMAT_ARGB4444 5
983 #define RADEON_TXFORMAT_ARGB8888 6
984 #define RADEON_TXFORMAT_RGBA8888 7
985 #define RADEON_TXFORMAT_Y8 8
986 #define RADEON_TXFORMAT_VYUY422 10
987 #define RADEON_TXFORMAT_YVYU422 11
988 #define RADEON_TXFORMAT_DXT1 12
989 #define RADEON_TXFORMAT_DXT23 14
990 #define RADEON_TXFORMAT_DXT45 15
992 #define R200_PP_TXCBLEND_0 0x2f00
993 #define R200_PP_TXCBLEND_1 0x2f10
994 #define R200_PP_TXCBLEND_2 0x2f20
995 #define R200_PP_TXCBLEND_3 0x2f30
996 #define R200_PP_TXCBLEND_4 0x2f40
997 #define R200_PP_TXCBLEND_5 0x2f50
998 #define R200_PP_TXCBLEND_6 0x2f60
999 #define R200_PP_TXCBLEND_7 0x2f70
1000 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
1001 #define R200_PP_TFACTOR_0 0x2ee0
1002 #define R200_SE_VTX_FMT_0 0x2088
1003 #define R200_SE_VAP_CNTL 0x2080
1004 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
1005 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
1006 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
1007 #define R200_PP_TXFILTER_5 0x2ca0
1008 #define R200_PP_TXFILTER_4 0x2c80
1009 #define R200_PP_TXFILTER_3 0x2c60
1010 #define R200_PP_TXFILTER_2 0x2c40
1011 #define R200_PP_TXFILTER_1 0x2c20
1012 #define R200_PP_TXFILTER_0 0x2c00
1013 #define R200_PP_TXOFFSET_5 0x2d78
1014 #define R200_PP_TXOFFSET_4 0x2d60
1015 #define R200_PP_TXOFFSET_3 0x2d48
1016 #define R200_PP_TXOFFSET_2 0x2d30
1017 #define R200_PP_TXOFFSET_1 0x2d18
1018 #define R200_PP_TXOFFSET_0 0x2d00
1020 #define R200_PP_CUBIC_FACES_0 0x2c18
1021 #define R200_PP_CUBIC_FACES_1 0x2c38
1022 #define R200_PP_CUBIC_FACES_2 0x2c58
1023 #define R200_PP_CUBIC_FACES_3 0x2c78
1024 #define R200_PP_CUBIC_FACES_4 0x2c98
1025 #define R200_PP_CUBIC_FACES_5 0x2cb8
1026 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
1027 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
1028 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
1029 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
1030 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
1031 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
1032 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
1033 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
1034 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
1035 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
1036 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
1037 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
1038 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
1039 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
1040 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
1041 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
1042 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
1043 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
1044 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
1045 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
1046 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
1047 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1048 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1049 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1050 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1051 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1052 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1053 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1054 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1055 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1057 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1058 #define R200_SE_VTE_CNTL 0x20b0
1059 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1060 #define R200_PP_TAM_DEBUG3 0x2d9c
1061 #define R200_PP_CNTL_X 0x2cc4
1062 #define R200_SE_VAP_CNTL_STATUS 0x2140
1063 #define R200_RE_SCISSOR_TL_0 0x1cd8
1064 #define R200_RE_SCISSOR_TL_1 0x1ce0
1065 #define R200_RE_SCISSOR_TL_2 0x1ce8
1066 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1067 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1068 #define R200_SE_VTX_STATE_CNTL 0x2180
1069 #define R200_RE_POINTSIZE 0x2648
1070 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1072 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1073 #define RADEON_PP_TEX_SIZE_1 0x1d0c
1074 #define RADEON_PP_TEX_SIZE_2 0x1d14
1076 #define RADEON_PP_CUBIC_FACES_0 0x1d24
1077 #define RADEON_PP_CUBIC_FACES_1 0x1d28
1078 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
1079 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1080 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1081 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1083 #define RADEON_SE_TCL_STATE_FLUSH 0x2284
1085 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1086 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1087 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1088 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1089 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1090 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1091 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1092 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1093 #define R200_3D_DRAW_IMMD_2 0xC0003500
1094 #define R200_SE_VTX_FMT_1 0x208c
1095 #define R200_RE_CNTL 0x1c50
1097 #define R200_RB3D_BLENDCOLOR 0x3218
1099 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1101 #define R200_PP_TRI_PERF 0x2cf8
1103 #define R200_PP_AFS_0 0x2f80
1104 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
1106 #define R200_VAP_PVS_CNTL_1 0x22D0
1108 #define R500_D1CRTC_STATUS 0x609c
1109 #define R500_D2CRTC_STATUS 0x689c
1110 #define R500_CRTC_V_BLANK (1<<0)
1112 #define R500_D1CRTC_FRAME_COUNT 0x60a4
1113 #define R500_D2CRTC_FRAME_COUNT 0x68a4
1115 #define R500_D1MODE_V_COUNTER 0x6530
1116 #define R500_D2MODE_V_COUNTER 0x6d30
1118 #define R500_D1MODE_VBLANK_STATUS 0x6534
1119 #define R500_D2MODE_VBLANK_STATUS 0x6d34
1120 #define R500_VBLANK_OCCURED (1<<0)
1121 #define R500_VBLANK_ACK (1<<4)
1122 #define R500_VBLANK_STAT (1<<12)
1123 #define R500_VBLANK_INT (1<<16)
1125 #define R500_DxMODE_INT_MASK 0x6540
1126 #define R500_D1MODE_INT_MASK (1<<0)
1127 #define R500_D2MODE_INT_MASK (1<<8)
1129 #define R500_DISP_INTERRUPT_STATUS 0x7edc
1130 #define R500_D1_VBLANK_INTERRUPT (1 << 4)
1131 #define R500_D2_VBLANK_INTERRUPT (1 << 5)
1134 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1136 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1137 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1138 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1139 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1140 #define RADEON_LAST_DISPATCH 1
1142 #define RADEON_MAX_VB_AGE 0x7fffffff
1143 #define RADEON_MAX_VB_VERTS (0xffff)
1145 #define RADEON_RING_HIGH_MARK 128
1147 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
1149 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1150 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
1151 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1152 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1154 #define RADEON_WRITE_PLL(addr, val) \
1156 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
1157 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
1158 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1161 #define RADEON_WRITE_PCIE(addr, val) \
1163 RADEON_WRITE8(RADEON_PCIE_INDEX, \
1165 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1168 #define R500_WRITE_MCIND(addr, val) \
1170 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1171 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1172 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1175 #define RS480_WRITE_MCIND(addr, val) \
1177 RADEON_WRITE(RS480_NB_MC_INDEX, \
1178 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1179 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1180 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1183 #define RS690_WRITE_MCIND(addr, val) \
1185 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1186 RADEON_WRITE(RS690_MC_DATA, val); \
1187 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1190 #define IGP_WRITE_MCIND(addr, val) \
1192 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \
1193 RS690_WRITE_MCIND(addr, val); \
1195 RS480_WRITE_MCIND(addr, val); \
1198 #define CP_PACKET0( reg, n ) \
1199 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1200 #define CP_PACKET0_TABLE( reg, n ) \
1201 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1202 #define CP_PACKET1( reg0, reg1 ) \
1203 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1204 #define CP_PACKET2() \
1206 #define CP_PACKET3( pkt, n ) \
1207 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1209 /* ================================================================
1210 * Engine control helper macros
1213 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1214 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1215 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1216 RADEON_WAIT_HOST_IDLECLEAN) ); \
1219 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1220 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1221 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1222 RADEON_WAIT_HOST_IDLECLEAN) ); \
1225 #define RADEON_WAIT_UNTIL_IDLE() do { \
1226 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1227 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1228 RADEON_WAIT_3D_IDLECLEAN | \
1229 RADEON_WAIT_HOST_IDLECLEAN) ); \
1232 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1233 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1234 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1237 #define RADEON_FLUSH_CACHE() do { \
1238 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1239 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1240 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1242 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1243 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1247 #define RADEON_PURGE_CACHE() do { \
1248 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1249 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1250 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
1252 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1253 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
1257 #define RADEON_FLUSH_ZCACHE() do { \
1258 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1259 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1260 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1262 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1263 OUT_RING(R300_ZC_FLUSH); \
1267 #define RADEON_PURGE_ZCACHE() do { \
1268 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1269 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1270 OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \
1272 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1273 OUT_RING(R300_ZC_FLUSH_ALL); \
1277 /* ================================================================
1278 * Misc helper macros
1281 /* Perfbox functionality only.
1283 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1285 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1286 u32 head = GET_RING_HEAD( dev_priv ); \
1287 if (head == dev_priv->ring.tail) \
1288 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1292 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1294 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1295 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1296 int __ret = radeon_do_cp_idle( dev_priv ); \
1297 if ( __ret ) return __ret; \
1298 sarea_priv->last_dispatch = 0; \
1299 radeon_freelist_reset( dev ); \
1303 #define RADEON_DISPATCH_AGE( age ) do { \
1304 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1308 #define RADEON_FRAME_AGE( age ) do { \
1309 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1313 #define RADEON_CLEAR_AGE( age ) do { \
1314 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1318 /* ================================================================
1322 #define RADEON_VERBOSE 0
1324 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1326 #define BEGIN_RING( n ) do { \
1327 if ( RADEON_VERBOSE ) { \
1328 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
1330 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1332 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1334 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1335 ring = dev_priv->ring.start; \
1336 write = dev_priv->ring.tail; \
1337 mask = dev_priv->ring.tail_mask; \
1340 #define ADVANCE_RING() do { \
1341 if ( RADEON_VERBOSE ) { \
1342 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1343 write, dev_priv->ring.tail ); \
1345 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1347 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1348 ((dev_priv->ring.tail + _nr) & mask), \
1351 dev_priv->ring.tail = write; \
1354 #define COMMIT_RING() do { \
1355 /* Flush writes to ring */ \
1356 DRM_MEMORYBARRIER(); \
1357 GET_RING_HEAD( dev_priv ); \
1358 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1359 /* read from PCI bus to ensure correct posting */ \
1360 RADEON_READ( RADEON_CP_RB_RPTR ); \
1363 #define OUT_RING( x ) do { \
1364 if ( RADEON_VERBOSE ) { \
1365 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1366 (unsigned int)(x), write ); \
1368 ring[write++] = (x); \
1372 #define OUT_RING_REG( reg, val ) do { \
1373 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1377 #define OUT_RING_TABLE( tab, sz ) do { \
1379 int *_tab = (int *)(tab); \
1381 if (write + _size > mask) { \
1382 int _i = (mask+1) - write; \
1385 *(int *)(ring + write) = *_tab++; \
1392 while (_size > 0) { \
1393 *(ring + write) = *_tab++; \
1400 #endif /* __RADEON_DRV_H__ */