2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
7 * written by Paul Fulghum for Microgate Corporation
10 * Microgate and SyncLink are trademarks of Microgate Corporation
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
30 # define BREAKPOINT() asm(" int $3");
32 # define BREAKPOINT() { }
35 #define MAX_DEVICES 12
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
53 #include <linux/slab.h>
54 #include <linux/netdevice.h>
55 #include <linux/vmalloc.h>
56 #include <linux/init.h>
57 #include <linux/delay.h>
58 #include <linux/ioctl.h>
60 #include <asm/system.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69 #include <linux/synclink.h>
71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72 #define SYNCLINK_GENERIC_HDLC 1
74 #define SYNCLINK_GENERIC_HDLC 0
77 #define GET_USER(error,value,addr) error = get_user(value,addr)
78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
82 #include <asm/uaccess.h>
84 static MGSL_PARAMS default_params = {
85 MGSL_MODE_HDLC, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE /* unsigned char parity; */
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE 1024
102 #define SCA_MEM_SIZE 0x40000
103 #define SCA_BASE_SIZE 512
104 #define SCA_REG_SIZE 16
105 #define SCA_MAX_PORTS 4
106 #define SCAMAXDESC 128
108 #define BUFFERLISTSIZE 4096
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
113 u16 next; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr; /* lower 16 bits of buffer addr */
115 u8 buf_base; /* upper 8 bits of buffer addr */
117 u16 length; /* length of buffer */
118 u8 status; /* status of buffer */
120 } SCADESC, *PSCADESC;
122 typedef struct _SCADESC_EX
124 /* device driver bookkeeping section */
125 char *virt_addr; /* virtual address of data buffer */
126 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX, *PSCADESC_EX;
129 /* The queue of BH actions to be performed */
132 #define BH_TRANSMIT 2
135 #define IO_PIN_SHUTDOWN_LIMIT 100
137 struct _input_signal_events {
149 * Device instance data structure
151 typedef struct _synclinkmp_info {
152 void *if_ptr; /* General purpose pointer (used by SPPP) */
154 struct tty_port port;
156 unsigned short close_delay;
157 unsigned short closing_wait; /* time to wait before closing */
159 struct mgsl_icount icount;
162 int x_char; /* xon/xoff character */
163 u16 read_status_mask1; /* break detection (SR1 indications) */
164 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
165 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
166 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
167 unsigned char *tx_buf;
172 wait_queue_head_t status_event_wait_q;
173 wait_queue_head_t event_wait_q;
174 struct timer_list tx_timer; /* HDLC transmit timeout timer */
175 struct _synclinkmp_info *next_device; /* device list link */
176 struct timer_list status_timer; /* input signal status check timer */
178 spinlock_t lock; /* spinlock for synchronizing with ISR */
179 struct work_struct task; /* task structure for scheduling bh */
181 u32 max_frame_size; /* as set by device config */
185 bool bh_running; /* Protection from multiple */
189 int dcd_chkcount; /* check counts to prevent */
190 int cts_chkcount; /* too many IRQs if a signal */
191 int dsr_chkcount; /* is floating */
194 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
195 unsigned long buffer_list_phys;
197 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
198 SCADESC *rx_buf_list; /* list of receive buffer entries */
199 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
200 unsigned int current_rx_buf;
202 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
203 SCADESC *tx_buf_list; /* list of transmit buffer entries */
204 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
205 unsigned int last_tx_buf;
207 unsigned char *tmp_rx_buf;
208 unsigned int tmp_rx_buf_count;
217 unsigned char ie0_value;
218 unsigned char ie1_value;
219 unsigned char ie2_value;
220 unsigned char ctrlreg_value;
221 unsigned char old_signals;
223 char device_name[25]; /* device instance name */
229 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
231 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
233 unsigned int irq_level; /* interrupt level */
234 unsigned long irq_flags;
235 bool irq_requested; /* true if IRQ requested */
237 MGSL_PARAMS params; /* communications parameters */
239 unsigned char serial_signals; /* current serial signal states */
241 bool irq_occurred; /* for diagnostics use */
242 unsigned int init_error; /* Initialization startup error */
245 unsigned char* memory_base; /* shared memory address (PCI only) */
246 u32 phys_memory_base;
247 int shared_mem_requested;
249 unsigned char* sca_base; /* HD64570 SCA Memory address */
252 bool sca_base_requested;
254 unsigned char* lcr_base; /* local config registers (PCI only) */
257 int lcr_mem_requested;
259 unsigned char* statctrl_base; /* status/control register memory */
260 u32 phys_statctrl_base;
262 bool sca_statctrl_requested;
265 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
266 char char_buf[MAX_ASYNC_BUFFER_SIZE];
267 bool drop_rts_on_tx_done;
269 struct _input_signal_events input_signal_events;
271 /* SPPP/Cisco HDLC device parts */
276 #if SYNCLINK_GENERIC_HDLC
277 struct net_device *netdev;
282 #define MGSL_MAGIC 0x5401
285 * define serial signal status change macros
287 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
288 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
289 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
290 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
292 /* Common Register macros */
311 /* MSCI Register macros */
341 /* Timer Register Macros */
351 /* DMA Controller Register macros */
382 /* combine with timer or DMA register address */
390 /* SCA Command Codes */
393 #define TXENABLE 0x02
394 #define TXDISABLE 0x03
395 #define TXCRCINIT 0x04
396 #define TXCRCEXCL 0x05
400 #define TXBUFCLR 0x09
402 #define RXENABLE 0x12
403 #define RXDISABLE 0x13
404 #define RXCRCINIT 0x14
405 #define RXREJECT 0x15
406 #define SEARCHMP 0x16
407 #define RXCRCEXCL 0x17
408 #define RXCRCCALC 0x18
412 /* DMA command codes */
414 #define FEICLEAR 0x02
448 * Global linked list of SyncLink devices
450 static SLMP_INFO *synclinkmp_device_list = NULL;
451 static int synclinkmp_adapter_count = -1;
452 static int synclinkmp_device_count = 0;
455 * Set this param to non-zero to load eax with the
456 * .text section address and breakpoint on module load.
457 * This is useful for use with gdb and add-symbol-file command.
459 static int break_on_load = 0;
462 * Driver major number, defaults to zero to get auto
463 * assigned major number. May be forced as module parameter.
465 static int ttymajor = 0;
468 * Array of user specified options for ISA adapters.
470 static int debug_level = 0;
471 static int maxframe[MAX_DEVICES] = {0,};
472 static int dosyncppp[MAX_DEVICES] = {0,};
474 module_param(break_on_load, bool, 0);
475 module_param(ttymajor, int, 0);
476 module_param(debug_level, int, 0);
477 module_param_array(maxframe, int, NULL, 0);
478 module_param_array(dosyncppp, int, NULL, 0);
480 static char *driver_name = "SyncLink MultiPort driver";
481 static char *driver_version = "$Revision: 4.38 $";
483 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
484 static void synclinkmp_remove_one(struct pci_dev *dev);
486 static struct pci_device_id synclinkmp_pci_tbl[] = {
487 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
488 { 0, }, /* terminate list */
490 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
492 MODULE_LICENSE("GPL");
494 static struct pci_driver synclinkmp_pci_driver = {
495 .name = "synclinkmp",
496 .id_table = synclinkmp_pci_tbl,
497 .probe = synclinkmp_init_one,
498 .remove = __devexit_p(synclinkmp_remove_one),
502 static struct tty_driver *serial_driver;
504 /* number of characters left in xmit buffer before we ask for more */
505 #define WAKEUP_CHARS 256
510 static int open(struct tty_struct *tty, struct file * filp);
511 static void close(struct tty_struct *tty, struct file * filp);
512 static void hangup(struct tty_struct *tty);
513 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
515 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
516 static int put_char(struct tty_struct *tty, unsigned char ch);
517 static void send_xchar(struct tty_struct *tty, char ch);
518 static void wait_until_sent(struct tty_struct *tty, int timeout);
519 static int write_room(struct tty_struct *tty);
520 static void flush_chars(struct tty_struct *tty);
521 static void flush_buffer(struct tty_struct *tty);
522 static void tx_hold(struct tty_struct *tty);
523 static void tx_release(struct tty_struct *tty);
525 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
526 static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
527 static int chars_in_buffer(struct tty_struct *tty);
528 static void throttle(struct tty_struct * tty);
529 static void unthrottle(struct tty_struct * tty);
530 static void set_break(struct tty_struct *tty, int break_state);
532 #if SYNCLINK_GENERIC_HDLC
533 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
534 static void hdlcdev_tx_done(SLMP_INFO *info);
535 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
536 static int hdlcdev_init(SLMP_INFO *info);
537 static void hdlcdev_exit(SLMP_INFO *info);
542 static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
543 static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
544 static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
545 static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
546 static int set_txidle(SLMP_INFO *info, int idle_mode);
547 static int tx_enable(SLMP_INFO *info, int enable);
548 static int tx_abort(SLMP_INFO *info);
549 static int rx_enable(SLMP_INFO *info, int enable);
550 static int modem_input_wait(SLMP_INFO *info,int arg);
551 static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
552 static int tiocmget(struct tty_struct *tty, struct file *file);
553 static int tiocmset(struct tty_struct *tty, struct file *file,
554 unsigned int set, unsigned int clear);
555 static void set_break(struct tty_struct *tty, int break_state);
557 static void add_device(SLMP_INFO *info);
558 static void device_init(int adapter_num, struct pci_dev *pdev);
559 static int claim_resources(SLMP_INFO *info);
560 static void release_resources(SLMP_INFO *info);
562 static int startup(SLMP_INFO *info);
563 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
564 static void shutdown(SLMP_INFO *info);
565 static void program_hw(SLMP_INFO *info);
566 static void change_params(SLMP_INFO *info);
568 static bool init_adapter(SLMP_INFO *info);
569 static bool register_test(SLMP_INFO *info);
570 static bool irq_test(SLMP_INFO *info);
571 static bool loopback_test(SLMP_INFO *info);
572 static int adapter_test(SLMP_INFO *info);
573 static bool memory_test(SLMP_INFO *info);
575 static void reset_adapter(SLMP_INFO *info);
576 static void reset_port(SLMP_INFO *info);
577 static void async_mode(SLMP_INFO *info);
578 static void hdlc_mode(SLMP_INFO *info);
580 static void rx_stop(SLMP_INFO *info);
581 static void rx_start(SLMP_INFO *info);
582 static void rx_reset_buffers(SLMP_INFO *info);
583 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
584 static bool rx_get_frame(SLMP_INFO *info);
586 static void tx_start(SLMP_INFO *info);
587 static void tx_stop(SLMP_INFO *info);
588 static void tx_load_fifo(SLMP_INFO *info);
589 static void tx_set_idle(SLMP_INFO *info);
590 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
592 static void get_signals(SLMP_INFO *info);
593 static void set_signals(SLMP_INFO *info);
594 static void enable_loopback(SLMP_INFO *info, int enable);
595 static void set_rate(SLMP_INFO *info, u32 data_rate);
597 static int bh_action(SLMP_INFO *info);
598 static void bh_handler(struct work_struct *work);
599 static void bh_receive(SLMP_INFO *info);
600 static void bh_transmit(SLMP_INFO *info);
601 static void bh_status(SLMP_INFO *info);
602 static void isr_timer(SLMP_INFO *info);
603 static void isr_rxint(SLMP_INFO *info);
604 static void isr_rxrdy(SLMP_INFO *info);
605 static void isr_txint(SLMP_INFO *info);
606 static void isr_txrdy(SLMP_INFO *info);
607 static void isr_rxdmaok(SLMP_INFO *info);
608 static void isr_rxdmaerror(SLMP_INFO *info);
609 static void isr_txdmaok(SLMP_INFO *info);
610 static void isr_txdmaerror(SLMP_INFO *info);
611 static void isr_io_pin(SLMP_INFO *info, u16 status);
613 static int alloc_dma_bufs(SLMP_INFO *info);
614 static void free_dma_bufs(SLMP_INFO *info);
615 static int alloc_buf_list(SLMP_INFO *info);
616 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
617 static int alloc_tmp_rx_buf(SLMP_INFO *info);
618 static void free_tmp_rx_buf(SLMP_INFO *info);
620 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
621 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
622 static void tx_timeout(unsigned long context);
623 static void status_timeout(unsigned long context);
625 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
626 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
627 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
628 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
629 static unsigned char read_status_reg(SLMP_INFO * info);
630 static void write_control_reg(SLMP_INFO * info);
633 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
634 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
635 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
637 static u32 misc_ctrl_value = 0x007e4040;
638 static u32 lcr1_brdr_value = 0x00800028;
640 static u32 read_ahead_count = 8;
642 /* DPCR, DMA Priority Control
644 * 07..05 Not used, must be 0
645 * 04 BRC, bus release condition: 0=all transfers complete
646 * 1=release after 1 xfer on all channels
647 * 03 CCC, channel change condition: 0=every cycle
648 * 1=after each channel completes all xfers
649 * 02..00 PR<2..0>, priority 100=round robin
653 static unsigned char dma_priority = 0x04;
655 // Number of bytes that can be written to shared RAM
656 // in a single write operation
657 static u32 sca_pci_load_interval = 64;
660 * 1st function defined in .text section. Calling this function in
661 * init_module() followed by a breakpoint allows a remote debugger
662 * (gdb) to get the .text address for the add-symbol-file command.
663 * This allows remote debugging of dynamically loadable modules.
665 static void* synclinkmp_get_text_ptr(void);
666 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
668 static inline int sanity_check(SLMP_INFO *info,
669 char *name, const char *routine)
672 static const char *badmagic =
673 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
674 static const char *badinfo =
675 "Warning: null synclinkmp_struct for (%s) in %s\n";
678 printk(badinfo, name, routine);
681 if (info->magic != MGSL_MAGIC) {
682 printk(badmagic, name, routine);
693 * line discipline callback wrappers
695 * The wrappers maintain line discipline references
696 * while calling into the line discipline.
698 * ldisc_receive_buf - pass receive data to line discipline
701 static void ldisc_receive_buf(struct tty_struct *tty,
702 const __u8 *data, char *flags, int count)
704 struct tty_ldisc *ld;
707 ld = tty_ldisc_ref(tty);
709 if (ld->ops->receive_buf)
710 ld->ops->receive_buf(tty, data, flags, count);
717 /* Called when a port is opened. Init and enable port.
719 static int open(struct tty_struct *tty, struct file *filp)
726 if ((line < 0) || (line >= synclinkmp_device_count)) {
727 printk("%s(%d): open with invalid line #%d.\n",
728 __FILE__,__LINE__,line);
732 info = synclinkmp_device_list;
733 while(info && info->line != line)
734 info = info->next_device;
735 if (sanity_check(info, tty->name, "open"))
737 if ( info->init_error ) {
738 printk("%s(%d):%s device is not allocated, init error=%d\n",
739 __FILE__,__LINE__,info->device_name,info->init_error);
743 tty->driver_data = info;
744 info->port.tty = tty;
746 if (debug_level >= DEBUG_LEVEL_INFO)
747 printk("%s(%d):%s open(), old ref count = %d\n",
748 __FILE__,__LINE__,tty->driver->name, info->port.count);
750 /* If port is closing, signal caller to try again */
751 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
752 if (info->port.flags & ASYNC_CLOSING)
753 interruptible_sleep_on(&info->port.close_wait);
754 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
755 -EAGAIN : -ERESTARTSYS);
759 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
761 spin_lock_irqsave(&info->netlock, flags);
762 if (info->netcount) {
764 spin_unlock_irqrestore(&info->netlock, flags);
768 spin_unlock_irqrestore(&info->netlock, flags);
770 if (info->port.count == 1) {
771 /* 1st open on this device, init hardware */
772 retval = startup(info);
777 retval = block_til_ready(tty, filp, info);
779 if (debug_level >= DEBUG_LEVEL_INFO)
780 printk("%s(%d):%s block_til_ready() returned %d\n",
781 __FILE__,__LINE__, info->device_name, retval);
785 if (debug_level >= DEBUG_LEVEL_INFO)
786 printk("%s(%d):%s open() success\n",
787 __FILE__,__LINE__, info->device_name);
793 info->port.tty = NULL; /* tty layer will release tty struct */
801 /* Called when port is closed. Wait for remaining data to be
802 * sent. Disable port and free resources.
804 static void close(struct tty_struct *tty, struct file *filp)
806 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
808 if (sanity_check(info, tty->name, "close"))
811 if (debug_level >= DEBUG_LEVEL_INFO)
812 printk("%s(%d):%s close() entry, count=%d\n",
813 __FILE__,__LINE__, info->device_name, info->port.count);
815 if (!info->port.count)
818 if (tty_hung_up_p(filp))
821 if ((tty->count == 1) && (info->port.count != 1)) {
823 * tty->count is 1 and the tty structure will be freed.
824 * info->port.count should be one in this case.
825 * if it's not, correct it so that the port is shutdown.
827 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
828 "info->port.count is %d\n",
829 __FILE__,__LINE__, info->device_name, info->port.count);
830 info->port.count = 1;
835 /* if at least one open remaining, leave hardware active */
836 if (info->port.count)
839 info->port.flags |= ASYNC_CLOSING;
841 /* set tty->closing to notify line discipline to
842 * only process XON/XOFF characters. Only the N_TTY
843 * discipline appears to use this (ppp does not).
847 /* wait for transmit data to clear all layers */
849 if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE) {
850 if (debug_level >= DEBUG_LEVEL_INFO)
851 printk("%s(%d):%s close() calling tty_wait_until_sent\n",
852 __FILE__,__LINE__, info->device_name );
853 tty_wait_until_sent(tty, info->port.closing_wait);
856 if (info->port.flags & ASYNC_INITIALIZED)
857 wait_until_sent(tty, info->timeout);
861 tty_ldisc_flush(tty);
866 info->port.tty = NULL;
868 if (info->port.blocked_open) {
869 if (info->port.close_delay) {
870 msleep_interruptible(jiffies_to_msecs(info->port.close_delay));
872 wake_up_interruptible(&info->port.open_wait);
875 info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
877 wake_up_interruptible(&info->port.close_wait);
880 if (debug_level >= DEBUG_LEVEL_INFO)
881 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
882 tty->driver->name, info->port.count);
885 /* Called by tty_hangup() when a hangup is signaled.
886 * This is the same as closing all open descriptors for the port.
888 static void hangup(struct tty_struct *tty)
890 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
892 if (debug_level >= DEBUG_LEVEL_INFO)
893 printk("%s(%d):%s hangup()\n",
894 __FILE__,__LINE__, info->device_name );
896 if (sanity_check(info, tty->name, "hangup"))
902 info->port.count = 0;
903 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
904 info->port.tty = NULL;
906 wake_up_interruptible(&info->port.open_wait);
909 /* Set new termios settings
911 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
913 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
916 if (debug_level >= DEBUG_LEVEL_INFO)
917 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
922 /* Handle transition to B0 status */
923 if (old_termios->c_cflag & CBAUD &&
924 !(tty->termios->c_cflag & CBAUD)) {
925 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
926 spin_lock_irqsave(&info->lock,flags);
928 spin_unlock_irqrestore(&info->lock,flags);
931 /* Handle transition away from B0 status */
932 if (!(old_termios->c_cflag & CBAUD) &&
933 tty->termios->c_cflag & CBAUD) {
934 info->serial_signals |= SerialSignal_DTR;
935 if (!(tty->termios->c_cflag & CRTSCTS) ||
936 !test_bit(TTY_THROTTLED, &tty->flags)) {
937 info->serial_signals |= SerialSignal_RTS;
939 spin_lock_irqsave(&info->lock,flags);
941 spin_unlock_irqrestore(&info->lock,flags);
944 /* Handle turning off CRTSCTS */
945 if (old_termios->c_cflag & CRTSCTS &&
946 !(tty->termios->c_cflag & CRTSCTS)) {
952 /* Send a block of data
956 * tty pointer to tty information structure
957 * buf pointer to buffer containing send data
958 * count size of send data in bytes
960 * Return Value: number of characters written
962 static int write(struct tty_struct *tty,
963 const unsigned char *buf, int count)
966 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
969 if (debug_level >= DEBUG_LEVEL_INFO)
970 printk("%s(%d):%s write() count=%d\n",
971 __FILE__,__LINE__,info->device_name,count);
973 if (sanity_check(info, tty->name, "write"))
979 if (info->params.mode == MGSL_MODE_HDLC) {
980 if (count > info->max_frame_size) {
986 if (info->tx_count) {
987 /* send accumulated data from send_char() calls */
988 /* as frame and wait before accepting more data. */
989 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
992 ret = info->tx_count = count;
993 tx_load_dma_buffer(info, buf, count);
998 c = min_t(int, count,
999 min(info->max_frame_size - info->tx_count - 1,
1000 info->max_frame_size - info->tx_put));
1004 memcpy(info->tx_buf + info->tx_put, buf, c);
1006 spin_lock_irqsave(&info->lock,flags);
1008 if (info->tx_put >= info->max_frame_size)
1009 info->tx_put -= info->max_frame_size;
1010 info->tx_count += c;
1011 spin_unlock_irqrestore(&info->lock,flags);
1018 if (info->params.mode == MGSL_MODE_HDLC) {
1020 ret = info->tx_count = 0;
1023 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1026 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1027 spin_lock_irqsave(&info->lock,flags);
1028 if (!info->tx_active)
1030 spin_unlock_irqrestore(&info->lock,flags);
1034 if (debug_level >= DEBUG_LEVEL_INFO)
1035 printk( "%s(%d):%s write() returning=%d\n",
1036 __FILE__,__LINE__,info->device_name,ret);
1040 /* Add a character to the transmit buffer.
1042 static int put_char(struct tty_struct *tty, unsigned char ch)
1044 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1045 unsigned long flags;
1048 if ( debug_level >= DEBUG_LEVEL_INFO ) {
1049 printk( "%s(%d):%s put_char(%d)\n",
1050 __FILE__,__LINE__,info->device_name,ch);
1053 if (sanity_check(info, tty->name, "put_char"))
1059 spin_lock_irqsave(&info->lock,flags);
1061 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1062 !info->tx_active ) {
1064 if (info->tx_count < info->max_frame_size - 1) {
1065 info->tx_buf[info->tx_put++] = ch;
1066 if (info->tx_put >= info->max_frame_size)
1067 info->tx_put -= info->max_frame_size;
1073 spin_unlock_irqrestore(&info->lock,flags);
1077 /* Send a high-priority XON/XOFF character
1079 static void send_xchar(struct tty_struct *tty, char ch)
1081 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1082 unsigned long flags;
1084 if (debug_level >= DEBUG_LEVEL_INFO)
1085 printk("%s(%d):%s send_xchar(%d)\n",
1086 __FILE__,__LINE__, info->device_name, ch );
1088 if (sanity_check(info, tty->name, "send_xchar"))
1093 /* Make sure transmit interrupts are on */
1094 spin_lock_irqsave(&info->lock,flags);
1095 if (!info->tx_enabled)
1097 spin_unlock_irqrestore(&info->lock,flags);
1101 /* Wait until the transmitter is empty.
1103 static void wait_until_sent(struct tty_struct *tty, int timeout)
1105 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1106 unsigned long orig_jiffies, char_time;
1111 if (debug_level >= DEBUG_LEVEL_INFO)
1112 printk("%s(%d):%s wait_until_sent() entry\n",
1113 __FILE__,__LINE__, info->device_name );
1115 if (sanity_check(info, tty->name, "wait_until_sent"))
1120 if (!(info->port.flags & ASYNC_INITIALIZED))
1123 orig_jiffies = jiffies;
1125 /* Set check interval to 1/5 of estimated time to
1126 * send a character, and make it at least 1. The check
1127 * interval should also be less than the timeout.
1128 * Note: use tight timings here to satisfy the NIST-PCTS.
1131 if ( info->params.data_rate ) {
1132 char_time = info->timeout/(32 * 5);
1139 char_time = min_t(unsigned long, char_time, timeout);
1141 if ( info->params.mode == MGSL_MODE_HDLC ) {
1142 while (info->tx_active) {
1143 msleep_interruptible(jiffies_to_msecs(char_time));
1144 if (signal_pending(current))
1146 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1150 //TODO: determine if there is something similar to USC16C32
1151 // TXSTATUS_ALL_SENT status
1152 while ( info->tx_active && info->tx_enabled) {
1153 msleep_interruptible(jiffies_to_msecs(char_time));
1154 if (signal_pending(current))
1156 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1163 if (debug_level >= DEBUG_LEVEL_INFO)
1164 printk("%s(%d):%s wait_until_sent() exit\n",
1165 __FILE__,__LINE__, info->device_name );
1168 /* Return the count of free bytes in transmit buffer
1170 static int write_room(struct tty_struct *tty)
1172 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1175 if (sanity_check(info, tty->name, "write_room"))
1179 if (info->params.mode == MGSL_MODE_HDLC) {
1180 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1182 ret = info->max_frame_size - info->tx_count - 1;
1188 if (debug_level >= DEBUG_LEVEL_INFO)
1189 printk("%s(%d):%s write_room()=%d\n",
1190 __FILE__, __LINE__, info->device_name, ret);
1195 /* enable transmitter and send remaining buffered characters
1197 static void flush_chars(struct tty_struct *tty)
1199 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1200 unsigned long flags;
1202 if ( debug_level >= DEBUG_LEVEL_INFO )
1203 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1204 __FILE__,__LINE__,info->device_name,info->tx_count);
1206 if (sanity_check(info, tty->name, "flush_chars"))
1209 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1213 if ( debug_level >= DEBUG_LEVEL_INFO )
1214 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1215 __FILE__,__LINE__,info->device_name );
1217 spin_lock_irqsave(&info->lock,flags);
1219 if (!info->tx_active) {
1220 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1222 /* operating in synchronous (frame oriented) mode */
1223 /* copy data from circular tx_buf to */
1224 /* transmit DMA buffer. */
1225 tx_load_dma_buffer(info,
1226 info->tx_buf,info->tx_count);
1231 spin_unlock_irqrestore(&info->lock,flags);
1234 /* Discard all data in the send buffer
1236 static void flush_buffer(struct tty_struct *tty)
1238 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1239 unsigned long flags;
1241 if (debug_level >= DEBUG_LEVEL_INFO)
1242 printk("%s(%d):%s flush_buffer() entry\n",
1243 __FILE__,__LINE__, info->device_name );
1245 if (sanity_check(info, tty->name, "flush_buffer"))
1248 spin_lock_irqsave(&info->lock,flags);
1249 info->tx_count = info->tx_put = info->tx_get = 0;
1250 del_timer(&info->tx_timer);
1251 spin_unlock_irqrestore(&info->lock,flags);
1256 /* throttle (stop) transmitter
1258 static void tx_hold(struct tty_struct *tty)
1260 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1261 unsigned long flags;
1263 if (sanity_check(info, tty->name, "tx_hold"))
1266 if ( debug_level >= DEBUG_LEVEL_INFO )
1267 printk("%s(%d):%s tx_hold()\n",
1268 __FILE__,__LINE__,info->device_name);
1270 spin_lock_irqsave(&info->lock,flags);
1271 if (info->tx_enabled)
1273 spin_unlock_irqrestore(&info->lock,flags);
1276 /* release (start) transmitter
1278 static void tx_release(struct tty_struct *tty)
1280 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1281 unsigned long flags;
1283 if (sanity_check(info, tty->name, "tx_release"))
1286 if ( debug_level >= DEBUG_LEVEL_INFO )
1287 printk("%s(%d):%s tx_release()\n",
1288 __FILE__,__LINE__,info->device_name);
1290 spin_lock_irqsave(&info->lock,flags);
1291 if (!info->tx_enabled)
1293 spin_unlock_irqrestore(&info->lock,flags);
1296 /* Service an IOCTL request
1300 * tty pointer to tty instance data
1301 * file pointer to associated file object for device
1302 * cmd IOCTL command code
1303 * arg command argument/context
1305 * Return Value: 0 if success, otherwise error code
1307 static int do_ioctl(struct tty_struct *tty, struct file *file,
1308 unsigned int cmd, unsigned long arg)
1310 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1312 struct mgsl_icount cnow; /* kernel counter temps */
1313 struct serial_icounter_struct __user *p_cuser; /* user space */
1314 unsigned long flags;
1315 void __user *argp = (void __user *)arg;
1317 if (debug_level >= DEBUG_LEVEL_INFO)
1318 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1319 info->device_name, cmd );
1321 if (sanity_check(info, tty->name, "ioctl"))
1324 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1325 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1326 if (tty->flags & (1 << TTY_IO_ERROR))
1331 case MGSL_IOCGPARAMS:
1332 return get_params(info, argp);
1333 case MGSL_IOCSPARAMS:
1334 return set_params(info, argp);
1335 case MGSL_IOCGTXIDLE:
1336 return get_txidle(info, argp);
1337 case MGSL_IOCSTXIDLE:
1338 return set_txidle(info, (int)arg);
1339 case MGSL_IOCTXENABLE:
1340 return tx_enable(info, (int)arg);
1341 case MGSL_IOCRXENABLE:
1342 return rx_enable(info, (int)arg);
1343 case MGSL_IOCTXABORT:
1344 return tx_abort(info);
1345 case MGSL_IOCGSTATS:
1346 return get_stats(info, argp);
1347 case MGSL_IOCWAITEVENT:
1348 return wait_mgsl_event(info, argp);
1349 case MGSL_IOCLOOPTXDONE:
1350 return 0; // TODO: Not supported, need to document
1351 /* Wait for modem input (DCD,RI,DSR,CTS) change
1352 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1355 return modem_input_wait(info,(int)arg);
1358 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1359 * Return: write counters to the user passed counter struct
1360 * NB: both 1->0 and 0->1 transitions are counted except for
1361 * RI where only 0->1 is counted.
1364 spin_lock_irqsave(&info->lock,flags);
1365 cnow = info->icount;
1366 spin_unlock_irqrestore(&info->lock,flags);
1368 PUT_USER(error,cnow.cts, &p_cuser->cts);
1369 if (error) return error;
1370 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1371 if (error) return error;
1372 PUT_USER(error,cnow.rng, &p_cuser->rng);
1373 if (error) return error;
1374 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1375 if (error) return error;
1376 PUT_USER(error,cnow.rx, &p_cuser->rx);
1377 if (error) return error;
1378 PUT_USER(error,cnow.tx, &p_cuser->tx);
1379 if (error) return error;
1380 PUT_USER(error,cnow.frame, &p_cuser->frame);
1381 if (error) return error;
1382 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1383 if (error) return error;
1384 PUT_USER(error,cnow.parity, &p_cuser->parity);
1385 if (error) return error;
1386 PUT_USER(error,cnow.brk, &p_cuser->brk);
1387 if (error) return error;
1388 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1389 if (error) return error;
1392 return -ENOIOCTLCMD;
1397 static int ioctl(struct tty_struct *tty, struct file *file,
1398 unsigned int cmd, unsigned long arg)
1402 ret = do_ioctl(tty, file, cmd, arg);
1408 * /proc fs routines....
1411 static inline int line_info(char *buf, SLMP_INFO *info)
1415 unsigned long flags;
1417 ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1418 "\tIRQ=%d MaxFrameSize=%u\n",
1420 info->phys_sca_base,
1421 info->phys_memory_base,
1422 info->phys_statctrl_base,
1423 info->phys_lcr_base,
1425 info->max_frame_size );
1427 /* output current serial signal states */
1428 spin_lock_irqsave(&info->lock,flags);
1430 spin_unlock_irqrestore(&info->lock,flags);
1434 if (info->serial_signals & SerialSignal_RTS)
1435 strcat(stat_buf, "|RTS");
1436 if (info->serial_signals & SerialSignal_CTS)
1437 strcat(stat_buf, "|CTS");
1438 if (info->serial_signals & SerialSignal_DTR)
1439 strcat(stat_buf, "|DTR");
1440 if (info->serial_signals & SerialSignal_DSR)
1441 strcat(stat_buf, "|DSR");
1442 if (info->serial_signals & SerialSignal_DCD)
1443 strcat(stat_buf, "|CD");
1444 if (info->serial_signals & SerialSignal_RI)
1445 strcat(stat_buf, "|RI");
1447 if (info->params.mode == MGSL_MODE_HDLC) {
1448 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1449 info->icount.txok, info->icount.rxok);
1450 if (info->icount.txunder)
1451 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1452 if (info->icount.txabort)
1453 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1454 if (info->icount.rxshort)
1455 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1456 if (info->icount.rxlong)
1457 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1458 if (info->icount.rxover)
1459 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1460 if (info->icount.rxcrc)
1461 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1463 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1464 info->icount.tx, info->icount.rx);
1465 if (info->icount.frame)
1466 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1467 if (info->icount.parity)
1468 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1469 if (info->icount.brk)
1470 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1471 if (info->icount.overrun)
1472 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1475 /* Append serial signal status to end */
1476 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1478 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1479 info->tx_active,info->bh_requested,info->bh_running,
1485 /* Called to print information about devices
1487 static int read_proc(char *page, char **start, off_t off, int count,
1488 int *eof, void *data)
1494 len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1496 info = synclinkmp_device_list;
1498 l = line_info(page + len, info);
1500 if (len+begin > off+count)
1502 if (len+begin < off) {
1506 info = info->next_device;
1511 if (off >= len+begin)
1513 *start = page + (off-begin);
1514 return ((count < begin+len-off) ? count : begin+len-off);
1517 /* Return the count of bytes in transmit buffer
1519 static int chars_in_buffer(struct tty_struct *tty)
1521 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1523 if (sanity_check(info, tty->name, "chars_in_buffer"))
1526 if (debug_level >= DEBUG_LEVEL_INFO)
1527 printk("%s(%d):%s chars_in_buffer()=%d\n",
1528 __FILE__, __LINE__, info->device_name, info->tx_count);
1530 return info->tx_count;
1533 /* Signal remote device to throttle send data (our receive data)
1535 static void throttle(struct tty_struct * tty)
1537 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1538 unsigned long flags;
1540 if (debug_level >= DEBUG_LEVEL_INFO)
1541 printk("%s(%d):%s throttle() entry\n",
1542 __FILE__,__LINE__, info->device_name );
1544 if (sanity_check(info, tty->name, "throttle"))
1548 send_xchar(tty, STOP_CHAR(tty));
1550 if (tty->termios->c_cflag & CRTSCTS) {
1551 spin_lock_irqsave(&info->lock,flags);
1552 info->serial_signals &= ~SerialSignal_RTS;
1554 spin_unlock_irqrestore(&info->lock,flags);
1558 /* Signal remote device to stop throttling send data (our receive data)
1560 static void unthrottle(struct tty_struct * tty)
1562 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1563 unsigned long flags;
1565 if (debug_level >= DEBUG_LEVEL_INFO)
1566 printk("%s(%d):%s unthrottle() entry\n",
1567 __FILE__,__LINE__, info->device_name );
1569 if (sanity_check(info, tty->name, "unthrottle"))
1576 send_xchar(tty, START_CHAR(tty));
1579 if (tty->termios->c_cflag & CRTSCTS) {
1580 spin_lock_irqsave(&info->lock,flags);
1581 info->serial_signals |= SerialSignal_RTS;
1583 spin_unlock_irqrestore(&info->lock,flags);
1587 /* set or clear transmit break condition
1588 * break_state -1=set break condition, 0=clear
1590 static void set_break(struct tty_struct *tty, int break_state)
1592 unsigned char RegValue;
1593 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1594 unsigned long flags;
1596 if (debug_level >= DEBUG_LEVEL_INFO)
1597 printk("%s(%d):%s set_break(%d)\n",
1598 __FILE__,__LINE__, info->device_name, break_state);
1600 if (sanity_check(info, tty->name, "set_break"))
1603 spin_lock_irqsave(&info->lock,flags);
1604 RegValue = read_reg(info, CTL);
1605 if (break_state == -1)
1609 write_reg(info, CTL, RegValue);
1610 spin_unlock_irqrestore(&info->lock,flags);
1613 #if SYNCLINK_GENERIC_HDLC
1616 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1617 * set encoding and frame check sequence (FCS) options
1619 * dev pointer to network device structure
1620 * encoding serial encoding setting
1621 * parity FCS setting
1623 * returns 0 if success, otherwise error code
1625 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1626 unsigned short parity)
1628 SLMP_INFO *info = dev_to_port(dev);
1629 unsigned char new_encoding;
1630 unsigned short new_crctype;
1632 /* return error if TTY interface open */
1633 if (info->port.count)
1638 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1639 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1640 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1641 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1642 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1643 default: return -EINVAL;
1648 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1649 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1650 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1651 default: return -EINVAL;
1654 info->params.encoding = new_encoding;
1655 info->params.crc_type = new_crctype;
1657 /* if network interface up, reprogram hardware */
1665 * called by generic HDLC layer to send frame
1667 * skb socket buffer containing HDLC frame
1668 * dev pointer to network device structure
1670 * returns 0 if success, otherwise error code
1672 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1674 SLMP_INFO *info = dev_to_port(dev);
1675 unsigned long flags;
1677 if (debug_level >= DEBUG_LEVEL_INFO)
1678 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1680 /* stop sending until this frame completes */
1681 netif_stop_queue(dev);
1683 /* copy data to device buffers */
1684 info->tx_count = skb->len;
1685 tx_load_dma_buffer(info, skb->data, skb->len);
1687 /* update network statistics */
1688 dev->stats.tx_packets++;
1689 dev->stats.tx_bytes += skb->len;
1691 /* done with socket buffer, so free it */
1694 /* save start time for transmit timeout detection */
1695 dev->trans_start = jiffies;
1697 /* start hardware transmitter if necessary */
1698 spin_lock_irqsave(&info->lock,flags);
1699 if (!info->tx_active)
1701 spin_unlock_irqrestore(&info->lock,flags);
1707 * called by network layer when interface enabled
1708 * claim resources and initialize hardware
1710 * dev pointer to network device structure
1712 * returns 0 if success, otherwise error code
1714 static int hdlcdev_open(struct net_device *dev)
1716 SLMP_INFO *info = dev_to_port(dev);
1718 unsigned long flags;
1720 if (debug_level >= DEBUG_LEVEL_INFO)
1721 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1723 /* generic HDLC layer open processing */
1724 if ((rc = hdlc_open(dev)))
1727 /* arbitrate between network and tty opens */
1728 spin_lock_irqsave(&info->netlock, flags);
1729 if (info->port.count != 0 || info->netcount != 0) {
1730 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1731 spin_unlock_irqrestore(&info->netlock, flags);
1735 spin_unlock_irqrestore(&info->netlock, flags);
1737 /* claim resources and init adapter */
1738 if ((rc = startup(info)) != 0) {
1739 spin_lock_irqsave(&info->netlock, flags);
1741 spin_unlock_irqrestore(&info->netlock, flags);
1745 /* assert DTR and RTS, apply hardware settings */
1746 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1749 /* enable network layer transmit */
1750 dev->trans_start = jiffies;
1751 netif_start_queue(dev);
1753 /* inform generic HDLC layer of current DCD status */
1754 spin_lock_irqsave(&info->lock, flags);
1756 spin_unlock_irqrestore(&info->lock, flags);
1757 if (info->serial_signals & SerialSignal_DCD)
1758 netif_carrier_on(dev);
1760 netif_carrier_off(dev);
1765 * called by network layer when interface is disabled
1766 * shutdown hardware and release resources
1768 * dev pointer to network device structure
1770 * returns 0 if success, otherwise error code
1772 static int hdlcdev_close(struct net_device *dev)
1774 SLMP_INFO *info = dev_to_port(dev);
1775 unsigned long flags;
1777 if (debug_level >= DEBUG_LEVEL_INFO)
1778 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1780 netif_stop_queue(dev);
1782 /* shutdown adapter and release resources */
1787 spin_lock_irqsave(&info->netlock, flags);
1789 spin_unlock_irqrestore(&info->netlock, flags);
1795 * called by network layer to process IOCTL call to network device
1797 * dev pointer to network device structure
1798 * ifr pointer to network interface request structure
1799 * cmd IOCTL command code
1801 * returns 0 if success, otherwise error code
1803 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1805 const size_t size = sizeof(sync_serial_settings);
1806 sync_serial_settings new_line;
1807 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1808 SLMP_INFO *info = dev_to_port(dev);
1811 if (debug_level >= DEBUG_LEVEL_INFO)
1812 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1814 /* return error if TTY interface open */
1815 if (info->port.count)
1818 if (cmd != SIOCWANDEV)
1819 return hdlc_ioctl(dev, ifr, cmd);
1821 switch(ifr->ifr_settings.type) {
1822 case IF_GET_IFACE: /* return current sync_serial_settings */
1824 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1825 if (ifr->ifr_settings.size < size) {
1826 ifr->ifr_settings.size = size; /* data size wanted */
1830 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1831 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1832 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1833 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1836 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1837 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1838 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1839 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1840 default: new_line.clock_type = CLOCK_DEFAULT;
1843 new_line.clock_rate = info->params.clock_speed;
1844 new_line.loopback = info->params.loopback ? 1:0;
1846 if (copy_to_user(line, &new_line, size))
1850 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1852 if(!capable(CAP_NET_ADMIN))
1854 if (copy_from_user(&new_line, line, size))
1857 switch (new_line.clock_type)
1859 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1860 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1861 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1862 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1863 case CLOCK_DEFAULT: flags = info->params.flags &
1864 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1865 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1866 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1867 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1868 default: return -EINVAL;
1871 if (new_line.loopback != 0 && new_line.loopback != 1)
1874 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1875 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1876 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1877 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1878 info->params.flags |= flags;
1880 info->params.loopback = new_line.loopback;
1882 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1883 info->params.clock_speed = new_line.clock_rate;
1885 info->params.clock_speed = 0;
1887 /* if network interface up, reprogram hardware */
1893 return hdlc_ioctl(dev, ifr, cmd);
1898 * called by network layer when transmit timeout is detected
1900 * dev pointer to network device structure
1902 static void hdlcdev_tx_timeout(struct net_device *dev)
1904 SLMP_INFO *info = dev_to_port(dev);
1905 unsigned long flags;
1907 if (debug_level >= DEBUG_LEVEL_INFO)
1908 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1910 dev->stats.tx_errors++;
1911 dev->stats.tx_aborted_errors++;
1913 spin_lock_irqsave(&info->lock,flags);
1915 spin_unlock_irqrestore(&info->lock,flags);
1917 netif_wake_queue(dev);
1921 * called by device driver when transmit completes
1922 * reenable network layer transmit if stopped
1924 * info pointer to device instance information
1926 static void hdlcdev_tx_done(SLMP_INFO *info)
1928 if (netif_queue_stopped(info->netdev))
1929 netif_wake_queue(info->netdev);
1933 * called by device driver when frame received
1934 * pass frame to network layer
1936 * info pointer to device instance information
1937 * buf pointer to buffer contianing frame data
1938 * size count of data bytes in buf
1940 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1942 struct sk_buff *skb = dev_alloc_skb(size);
1943 struct net_device *dev = info->netdev;
1945 if (debug_level >= DEBUG_LEVEL_INFO)
1946 printk("hdlcdev_rx(%s)\n",dev->name);
1949 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1951 dev->stats.rx_dropped++;
1955 memcpy(skb_put(skb, size), buf, size);
1957 skb->protocol = hdlc_type_trans(skb, dev);
1959 dev->stats.rx_packets++;
1960 dev->stats.rx_bytes += size;
1964 dev->last_rx = jiffies;
1968 * called by device driver when adding device instance
1969 * do generic HDLC initialization
1971 * info pointer to device instance information
1973 * returns 0 if success, otherwise error code
1975 static int hdlcdev_init(SLMP_INFO *info)
1978 struct net_device *dev;
1981 /* allocate and initialize network and HDLC layer objects */
1983 if (!(dev = alloc_hdlcdev(info))) {
1984 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1988 /* for network layer reporting purposes only */
1989 dev->mem_start = info->phys_sca_base;
1990 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1991 dev->irq = info->irq_level;
1993 /* network layer callbacks and settings */
1994 dev->do_ioctl = hdlcdev_ioctl;
1995 dev->open = hdlcdev_open;
1996 dev->stop = hdlcdev_close;
1997 dev->tx_timeout = hdlcdev_tx_timeout;
1998 dev->watchdog_timeo = 10*HZ;
1999 dev->tx_queue_len = 50;
2001 /* generic HDLC layer callbacks and settings */
2002 hdlc = dev_to_hdlc(dev);
2003 hdlc->attach = hdlcdev_attach;
2004 hdlc->xmit = hdlcdev_xmit;
2006 /* register objects with HDLC layer */
2007 if ((rc = register_hdlc_device(dev))) {
2008 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2018 * called by device driver when removing device instance
2019 * do generic HDLC cleanup
2021 * info pointer to device instance information
2023 static void hdlcdev_exit(SLMP_INFO *info)
2025 unregister_hdlc_device(info->netdev);
2026 free_netdev(info->netdev);
2027 info->netdev = NULL;
2030 #endif /* CONFIG_HDLC */
2033 /* Return next bottom half action to perform.
2034 * Return Value: BH action code or 0 if nothing to do.
2036 static int bh_action(SLMP_INFO *info)
2038 unsigned long flags;
2041 spin_lock_irqsave(&info->lock,flags);
2043 if (info->pending_bh & BH_RECEIVE) {
2044 info->pending_bh &= ~BH_RECEIVE;
2046 } else if (info->pending_bh & BH_TRANSMIT) {
2047 info->pending_bh &= ~BH_TRANSMIT;
2049 } else if (info->pending_bh & BH_STATUS) {
2050 info->pending_bh &= ~BH_STATUS;
2055 /* Mark BH routine as complete */
2056 info->bh_running = false;
2057 info->bh_requested = false;
2060 spin_unlock_irqrestore(&info->lock,flags);
2065 /* Perform bottom half processing of work items queued by ISR.
2067 static void bh_handler(struct work_struct *work)
2069 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2075 if ( debug_level >= DEBUG_LEVEL_BH )
2076 printk( "%s(%d):%s bh_handler() entry\n",
2077 __FILE__,__LINE__,info->device_name);
2079 info->bh_running = true;
2081 while((action = bh_action(info)) != 0) {
2083 /* Process work item */
2084 if ( debug_level >= DEBUG_LEVEL_BH )
2085 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2086 __FILE__,__LINE__,info->device_name, action);
2100 /* unknown work item ID */
2101 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2102 __FILE__,__LINE__,info->device_name,action);
2107 if ( debug_level >= DEBUG_LEVEL_BH )
2108 printk( "%s(%d):%s bh_handler() exit\n",
2109 __FILE__,__LINE__,info->device_name);
2112 static void bh_receive(SLMP_INFO *info)
2114 if ( debug_level >= DEBUG_LEVEL_BH )
2115 printk( "%s(%d):%s bh_receive()\n",
2116 __FILE__,__LINE__,info->device_name);
2118 while( rx_get_frame(info) );
2121 static void bh_transmit(SLMP_INFO *info)
2123 struct tty_struct *tty = info->port.tty;
2125 if ( debug_level >= DEBUG_LEVEL_BH )
2126 printk( "%s(%d):%s bh_transmit() entry\n",
2127 __FILE__,__LINE__,info->device_name);
2133 static void bh_status(SLMP_INFO *info)
2135 if ( debug_level >= DEBUG_LEVEL_BH )
2136 printk( "%s(%d):%s bh_status() entry\n",
2137 __FILE__,__LINE__,info->device_name);
2139 info->ri_chkcount = 0;
2140 info->dsr_chkcount = 0;
2141 info->dcd_chkcount = 0;
2142 info->cts_chkcount = 0;
2145 static void isr_timer(SLMP_INFO * info)
2147 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2149 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2150 write_reg(info, IER2, 0);
2152 /* TMCS, Timer Control/Status Register
2154 * 07 CMF, Compare match flag (read only) 1=match
2155 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2156 * 05 Reserved, must be 0
2157 * 04 TME, Timer Enable
2158 * 03..00 Reserved, must be 0
2162 write_reg(info, (unsigned char)(timer + TMCS), 0);
2164 info->irq_occurred = true;
2166 if ( debug_level >= DEBUG_LEVEL_ISR )
2167 printk("%s(%d):%s isr_timer()\n",
2168 __FILE__,__LINE__,info->device_name);
2171 static void isr_rxint(SLMP_INFO * info)
2173 struct tty_struct *tty = info->port.tty;
2174 struct mgsl_icount *icount = &info->icount;
2175 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2176 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2178 /* clear status bits */
2180 write_reg(info, SR1, status);
2183 write_reg(info, SR2, status2);
2185 if ( debug_level >= DEBUG_LEVEL_ISR )
2186 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2187 __FILE__,__LINE__,info->device_name,status,status2);
2189 if (info->params.mode == MGSL_MODE_ASYNC) {
2190 if (status & BRKD) {
2193 /* process break detection if tty control
2194 * is not set to ignore it
2197 if (!(status & info->ignore_status_mask1)) {
2198 if (info->read_status_mask1 & BRKD) {
2199 tty_insert_flip_char(tty, 0, TTY_BREAK);
2200 if (info->port.flags & ASYNC_SAK)
2208 if (status & (FLGD|IDLD)) {
2210 info->icount.exithunt++;
2211 else if (status & IDLD)
2212 info->icount.rxidle++;
2213 wake_up_interruptible(&info->event_wait_q);
2217 if (status & CDCD) {
2218 /* simulate a common modem status change interrupt
2221 get_signals( info );
2223 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2228 * handle async rx data interrupts
2230 static void isr_rxrdy(SLMP_INFO * info)
2233 unsigned char DataByte;
2234 struct tty_struct *tty = info->port.tty;
2235 struct mgsl_icount *icount = &info->icount;
2237 if ( debug_level >= DEBUG_LEVEL_ISR )
2238 printk("%s(%d):%s isr_rxrdy\n",
2239 __FILE__,__LINE__,info->device_name);
2241 while((status = read_reg(info,CST0)) & BIT0)
2245 DataByte = read_reg(info,TRB);
2249 if ( status & (PE + FRME + OVRN) ) {
2250 printk("%s(%d):%s rxerr=%04X\n",
2251 __FILE__,__LINE__,info->device_name,status);
2253 /* update error statistics */
2256 else if (status & FRME)
2258 else if (status & OVRN)
2261 /* discard char if tty control flags say so */
2262 if (status & info->ignore_status_mask2)
2265 status &= info->read_status_mask2;
2270 else if (status & FRME)
2272 if (status & OVRN) {
2273 /* Overrun is special, since it's
2274 * reported immediately, and doesn't
2275 * affect the current character
2280 } /* end of if (error) */
2283 tty_insert_flip_char(tty, DataByte, flag);
2285 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2289 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2290 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2291 __FILE__,__LINE__,info->device_name,
2292 icount->rx,icount->brk,icount->parity,
2293 icount->frame,icount->overrun);
2297 tty_flip_buffer_push(tty);
2300 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2302 if ( debug_level >= DEBUG_LEVEL_ISR )
2303 printk("%s(%d):%s isr_txeom status=%02x\n",
2304 __FILE__,__LINE__,info->device_name,status);
2306 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2307 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2308 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2310 if (status & UDRN) {
2311 write_reg(info, CMD, TXRESET);
2312 write_reg(info, CMD, TXENABLE);
2314 write_reg(info, CMD, TXBUFCLR);
2316 /* disable and clear tx interrupts */
2317 info->ie0_value &= ~TXRDYE;
2318 info->ie1_value &= ~(IDLE + UDRN);
2319 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2320 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2322 if ( info->tx_active ) {
2323 if (info->params.mode != MGSL_MODE_ASYNC) {
2325 info->icount.txunder++;
2326 else if (status & IDLE)
2327 info->icount.txok++;
2330 info->tx_active = false;
2331 info->tx_count = info->tx_put = info->tx_get = 0;
2333 del_timer(&info->tx_timer);
2335 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2336 info->serial_signals &= ~SerialSignal_RTS;
2337 info->drop_rts_on_tx_done = false;
2341 #if SYNCLINK_GENERIC_HDLC
2343 hdlcdev_tx_done(info);
2347 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2351 info->pending_bh |= BH_TRANSMIT;
2358 * handle tx status interrupts
2360 static void isr_txint(SLMP_INFO * info)
2362 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2364 /* clear status bits */
2365 write_reg(info, SR1, status);
2367 if ( debug_level >= DEBUG_LEVEL_ISR )
2368 printk("%s(%d):%s isr_txint status=%02x\n",
2369 __FILE__,__LINE__,info->device_name,status);
2371 if (status & (UDRN + IDLE))
2372 isr_txeom(info, status);
2374 if (status & CCTS) {
2375 /* simulate a common modem status change interrupt
2378 get_signals( info );
2380 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2386 * handle async tx data interrupts
2388 static void isr_txrdy(SLMP_INFO * info)
2390 if ( debug_level >= DEBUG_LEVEL_ISR )
2391 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2392 __FILE__,__LINE__,info->device_name,info->tx_count);
2394 if (info->params.mode != MGSL_MODE_ASYNC) {
2395 /* disable TXRDY IRQ, enable IDLE IRQ */
2396 info->ie0_value &= ~TXRDYE;
2397 info->ie1_value |= IDLE;
2398 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2402 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2407 if ( info->tx_count )
2408 tx_load_fifo( info );
2410 info->tx_active = false;
2411 info->ie0_value &= ~TXRDYE;
2412 write_reg(info, IE0, info->ie0_value);
2415 if (info->tx_count < WAKEUP_CHARS)
2416 info->pending_bh |= BH_TRANSMIT;
2419 static void isr_rxdmaok(SLMP_INFO * info)
2421 /* BIT7 = EOT (end of transfer)
2422 * BIT6 = EOM (end of message/frame)
2424 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2426 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2427 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2429 if ( debug_level >= DEBUG_LEVEL_ISR )
2430 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2431 __FILE__,__LINE__,info->device_name,status);
2433 info->pending_bh |= BH_RECEIVE;
2436 static void isr_rxdmaerror(SLMP_INFO * info)
2438 /* BIT5 = BOF (buffer overflow)
2439 * BIT4 = COF (counter overflow)
2441 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2443 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2444 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2446 if ( debug_level >= DEBUG_LEVEL_ISR )
2447 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2448 __FILE__,__LINE__,info->device_name,status);
2450 info->rx_overflow = true;
2451 info->pending_bh |= BH_RECEIVE;
2454 static void isr_txdmaok(SLMP_INFO * info)
2456 unsigned char status_reg1 = read_reg(info, SR1);
2458 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2459 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2460 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2462 if ( debug_level >= DEBUG_LEVEL_ISR )
2463 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2464 __FILE__,__LINE__,info->device_name,status_reg1);
2466 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2467 write_reg16(info, TRC0, 0);
2468 info->ie0_value |= TXRDYE;
2469 write_reg(info, IE0, info->ie0_value);
2472 static void isr_txdmaerror(SLMP_INFO * info)
2474 /* BIT5 = BOF (buffer overflow)
2475 * BIT4 = COF (counter overflow)
2477 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2479 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2480 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2482 if ( debug_level >= DEBUG_LEVEL_ISR )
2483 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2484 __FILE__,__LINE__,info->device_name,status);
2487 /* handle input serial signal changes
2489 static void isr_io_pin( SLMP_INFO *info, u16 status )
2491 struct mgsl_icount *icount;
2493 if ( debug_level >= DEBUG_LEVEL_ISR )
2494 printk("%s(%d):isr_io_pin status=%04X\n",
2495 __FILE__,__LINE__,status);
2497 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2498 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2499 icount = &info->icount;
2500 /* update input line counters */
2501 if (status & MISCSTATUS_RI_LATCHED) {
2503 if ( status & SerialSignal_RI )
2504 info->input_signal_events.ri_up++;
2506 info->input_signal_events.ri_down++;
2508 if (status & MISCSTATUS_DSR_LATCHED) {
2510 if ( status & SerialSignal_DSR )
2511 info->input_signal_events.dsr_up++;
2513 info->input_signal_events.dsr_down++;
2515 if (status & MISCSTATUS_DCD_LATCHED) {
2516 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2517 info->ie1_value &= ~CDCD;
2518 write_reg(info, IE1, info->ie1_value);
2521 if (status & SerialSignal_DCD) {
2522 info->input_signal_events.dcd_up++;
2524 info->input_signal_events.dcd_down++;
2525 #if SYNCLINK_GENERIC_HDLC
2526 if (info->netcount) {
2527 if (status & SerialSignal_DCD)
2528 netif_carrier_on(info->netdev);
2530 netif_carrier_off(info->netdev);
2534 if (status & MISCSTATUS_CTS_LATCHED)
2536 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2537 info->ie1_value &= ~CCTS;
2538 write_reg(info, IE1, info->ie1_value);
2541 if ( status & SerialSignal_CTS )
2542 info->input_signal_events.cts_up++;
2544 info->input_signal_events.cts_down++;
2546 wake_up_interruptible(&info->status_event_wait_q);
2547 wake_up_interruptible(&info->event_wait_q);
2549 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2550 (status & MISCSTATUS_DCD_LATCHED) ) {
2551 if ( debug_level >= DEBUG_LEVEL_ISR )
2552 printk("%s CD now %s...", info->device_name,
2553 (status & SerialSignal_DCD) ? "on" : "off");
2554 if (status & SerialSignal_DCD)
2555 wake_up_interruptible(&info->port.open_wait);
2557 if ( debug_level >= DEBUG_LEVEL_ISR )
2558 printk("doing serial hangup...");
2560 tty_hangup(info->port.tty);
2564 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
2565 (status & MISCSTATUS_CTS_LATCHED) ) {
2566 if ( info->port.tty ) {
2567 if (info->port.tty->hw_stopped) {
2568 if (status & SerialSignal_CTS) {
2569 if ( debug_level >= DEBUG_LEVEL_ISR )
2570 printk("CTS tx start...");
2571 info->port.tty->hw_stopped = 0;
2573 info->pending_bh |= BH_TRANSMIT;
2577 if (!(status & SerialSignal_CTS)) {
2578 if ( debug_level >= DEBUG_LEVEL_ISR )
2579 printk("CTS tx stop...");
2580 info->port.tty->hw_stopped = 1;
2588 info->pending_bh |= BH_STATUS;
2591 /* Interrupt service routine entry point.
2594 * irq interrupt number that caused interrupt
2595 * dev_id device ID supplied during interrupt registration
2596 * regs interrupted processor context
2598 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2600 SLMP_INFO *info = dev_id;
2601 unsigned char status, status0, status1=0;
2602 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2603 unsigned char timerstatus0, timerstatus1=0;
2604 unsigned char shift;
2608 if ( debug_level >= DEBUG_LEVEL_ISR )
2609 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2610 __FILE__, __LINE__, info->irq_level);
2612 spin_lock(&info->lock);
2616 /* get status for SCA0 (ports 0-1) */
2617 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2618 status0 = (unsigned char)tmp;
2619 dmastatus0 = (unsigned char)(tmp>>8);
2620 timerstatus0 = read_reg(info, ISR2);
2622 if ( debug_level >= DEBUG_LEVEL_ISR )
2623 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2624 __FILE__, __LINE__, info->device_name,
2625 status0, dmastatus0, timerstatus0);
2627 if (info->port_count == 4) {
2628 /* get status for SCA1 (ports 2-3) */
2629 tmp = read_reg16(info->port_array[2], ISR0);
2630 status1 = (unsigned char)tmp;
2631 dmastatus1 = (unsigned char)(tmp>>8);
2632 timerstatus1 = read_reg(info->port_array[2], ISR2);
2634 if ( debug_level >= DEBUG_LEVEL_ISR )
2635 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2636 __FILE__,__LINE__,info->device_name,
2637 status1,dmastatus1,timerstatus1);
2640 if (!status0 && !dmastatus0 && !timerstatus0 &&
2641 !status1 && !dmastatus1 && !timerstatus1)
2644 for(i=0; i < info->port_count ; i++) {
2645 if (info->port_array[i] == NULL)
2649 dmastatus = dmastatus0;
2652 dmastatus = dmastatus1;
2655 shift = i & 1 ? 4 :0;
2657 if (status & BIT0 << shift)
2658 isr_rxrdy(info->port_array[i]);
2659 if (status & BIT1 << shift)
2660 isr_txrdy(info->port_array[i]);
2661 if (status & BIT2 << shift)
2662 isr_rxint(info->port_array[i]);
2663 if (status & BIT3 << shift)
2664 isr_txint(info->port_array[i]);
2666 if (dmastatus & BIT0 << shift)
2667 isr_rxdmaerror(info->port_array[i]);
2668 if (dmastatus & BIT1 << shift)
2669 isr_rxdmaok(info->port_array[i]);
2670 if (dmastatus & BIT2 << shift)
2671 isr_txdmaerror(info->port_array[i]);
2672 if (dmastatus & BIT3 << shift)
2673 isr_txdmaok(info->port_array[i]);
2676 if (timerstatus0 & (BIT5 | BIT4))
2677 isr_timer(info->port_array[0]);
2678 if (timerstatus0 & (BIT7 | BIT6))
2679 isr_timer(info->port_array[1]);
2680 if (timerstatus1 & (BIT5 | BIT4))
2681 isr_timer(info->port_array[2]);
2682 if (timerstatus1 & (BIT7 | BIT6))
2683 isr_timer(info->port_array[3]);
2686 for(i=0; i < info->port_count ; i++) {
2687 SLMP_INFO * port = info->port_array[i];
2689 /* Request bottom half processing if there's something
2690 * for it to do and the bh is not already running.
2692 * Note: startup adapter diags require interrupts.
2693 * do not request bottom half processing if the
2694 * device is not open in a normal mode.
2696 if ( port && (port->port.count || port->netcount) &&
2697 port->pending_bh && !port->bh_running &&
2698 !port->bh_requested ) {
2699 if ( debug_level >= DEBUG_LEVEL_ISR )
2700 printk("%s(%d):%s queueing bh task.\n",
2701 __FILE__,__LINE__,port->device_name);
2702 schedule_work(&port->task);
2703 port->bh_requested = true;
2707 spin_unlock(&info->lock);
2709 if ( debug_level >= DEBUG_LEVEL_ISR )
2710 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2711 __FILE__, __LINE__, info->irq_level);
2715 /* Initialize and start device.
2717 static int startup(SLMP_INFO * info)
2719 if ( debug_level >= DEBUG_LEVEL_INFO )
2720 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2722 if (info->port.flags & ASYNC_INITIALIZED)
2725 if (!info->tx_buf) {
2726 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2727 if (!info->tx_buf) {
2728 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2729 __FILE__,__LINE__,info->device_name);
2734 info->pending_bh = 0;
2736 memset(&info->icount, 0, sizeof(info->icount));
2738 /* program hardware for current parameters */
2741 change_params(info);
2743 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2746 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2748 info->port.flags |= ASYNC_INITIALIZED;
2753 /* Called by close() and hangup() to shutdown hardware
2755 static void shutdown(SLMP_INFO * info)
2757 unsigned long flags;
2759 if (!(info->port.flags & ASYNC_INITIALIZED))
2762 if (debug_level >= DEBUG_LEVEL_INFO)
2763 printk("%s(%d):%s synclinkmp_shutdown()\n",
2764 __FILE__,__LINE__, info->device_name );
2766 /* clear status wait queue because status changes */
2767 /* can't happen after shutting down the hardware */
2768 wake_up_interruptible(&info->status_event_wait_q);
2769 wake_up_interruptible(&info->event_wait_q);
2771 del_timer(&info->tx_timer);
2772 del_timer(&info->status_timer);
2774 kfree(info->tx_buf);
2775 info->tx_buf = NULL;
2777 spin_lock_irqsave(&info->lock,flags);
2781 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2782 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2786 spin_unlock_irqrestore(&info->lock,flags);
2789 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2791 info->port.flags &= ~ASYNC_INITIALIZED;
2794 static void program_hw(SLMP_INFO *info)
2796 unsigned long flags;
2798 spin_lock_irqsave(&info->lock,flags);
2803 info->tx_count = info->tx_put = info->tx_get = 0;
2805 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2812 info->dcd_chkcount = 0;
2813 info->cts_chkcount = 0;
2814 info->ri_chkcount = 0;
2815 info->dsr_chkcount = 0;
2817 info->ie1_value |= (CDCD|CCTS);
2818 write_reg(info, IE1, info->ie1_value);
2822 if (info->netcount || (info->port.tty && info->port.tty->termios->c_cflag & CREAD) )
2825 spin_unlock_irqrestore(&info->lock,flags);
2828 /* Reconfigure adapter based on new parameters
2830 static void change_params(SLMP_INFO *info)
2835 if (!info->port.tty || !info->port.tty->termios)
2838 if (debug_level >= DEBUG_LEVEL_INFO)
2839 printk("%s(%d):%s change_params()\n",
2840 __FILE__,__LINE__, info->device_name );
2842 cflag = info->port.tty->termios->c_cflag;
2844 /* if B0 rate (hangup) specified then negate DTR and RTS */
2845 /* otherwise assert DTR and RTS */
2847 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2849 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2851 /* byte size and parity */
2853 switch (cflag & CSIZE) {
2854 case CS5: info->params.data_bits = 5; break;
2855 case CS6: info->params.data_bits = 6; break;
2856 case CS7: info->params.data_bits = 7; break;
2857 case CS8: info->params.data_bits = 8; break;
2858 /* Never happens, but GCC is too dumb to figure it out */
2859 default: info->params.data_bits = 7; break;
2863 info->params.stop_bits = 2;
2865 info->params.stop_bits = 1;
2867 info->params.parity = ASYNC_PARITY_NONE;
2868 if (cflag & PARENB) {
2870 info->params.parity = ASYNC_PARITY_ODD;
2872 info->params.parity = ASYNC_PARITY_EVEN;
2875 info->params.parity = ASYNC_PARITY_SPACE;
2879 /* calculate number of jiffies to transmit a full
2880 * FIFO (32 bytes) at specified data rate
2882 bits_per_char = info->params.data_bits +
2883 info->params.stop_bits + 1;
2885 /* if port data rate is set to 460800 or less then
2886 * allow tty settings to override, otherwise keep the
2887 * current data rate.
2889 if (info->params.data_rate <= 460800) {
2890 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2893 if ( info->params.data_rate ) {
2894 info->timeout = (32*HZ*bits_per_char) /
2895 info->params.data_rate;
2897 info->timeout += HZ/50; /* Add .02 seconds of slop */
2899 if (cflag & CRTSCTS)
2900 info->port.flags |= ASYNC_CTS_FLOW;
2902 info->port.flags &= ~ASYNC_CTS_FLOW;
2905 info->port.flags &= ~ASYNC_CHECK_CD;
2907 info->port.flags |= ASYNC_CHECK_CD;
2909 /* process tty input control flags */
2911 info->read_status_mask2 = OVRN;
2912 if (I_INPCK(info->port.tty))
2913 info->read_status_mask2 |= PE | FRME;
2914 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2915 info->read_status_mask1 |= BRKD;
2916 if (I_IGNPAR(info->port.tty))
2917 info->ignore_status_mask2 |= PE | FRME;
2918 if (I_IGNBRK(info->port.tty)) {
2919 info->ignore_status_mask1 |= BRKD;
2920 /* If ignoring parity and break indicators, ignore
2921 * overruns too. (For real raw support).
2923 if (I_IGNPAR(info->port.tty))
2924 info->ignore_status_mask2 |= OVRN;
2930 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2934 if (debug_level >= DEBUG_LEVEL_INFO)
2935 printk("%s(%d):%s get_params()\n",
2936 __FILE__,__LINE__, info->device_name);
2939 memset(&info->icount, 0, sizeof(info->icount));
2941 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2949 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2952 if (debug_level >= DEBUG_LEVEL_INFO)
2953 printk("%s(%d):%s get_params()\n",
2954 __FILE__,__LINE__, info->device_name);
2956 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2958 if ( debug_level >= DEBUG_LEVEL_INFO )
2959 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2960 __FILE__,__LINE__,info->device_name);
2967 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2969 unsigned long flags;
2970 MGSL_PARAMS tmp_params;
2973 if (debug_level >= DEBUG_LEVEL_INFO)
2974 printk("%s(%d):%s set_params\n",
2975 __FILE__,__LINE__,info->device_name );
2976 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2978 if ( debug_level >= DEBUG_LEVEL_INFO )
2979 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2980 __FILE__,__LINE__,info->device_name);
2984 spin_lock_irqsave(&info->lock,flags);
2985 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2986 spin_unlock_irqrestore(&info->lock,flags);
2988 change_params(info);
2993 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2997 if (debug_level >= DEBUG_LEVEL_INFO)
2998 printk("%s(%d):%s get_txidle()=%d\n",
2999 __FILE__,__LINE__, info->device_name, info->idle_mode);
3001 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
3003 if ( debug_level >= DEBUG_LEVEL_INFO )
3004 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3005 __FILE__,__LINE__,info->device_name);
3012 static int set_txidle(SLMP_INFO * info, int idle_mode)
3014 unsigned long flags;
3016 if (debug_level >= DEBUG_LEVEL_INFO)
3017 printk("%s(%d):%s set_txidle(%d)\n",
3018 __FILE__,__LINE__,info->device_name, idle_mode );
3020 spin_lock_irqsave(&info->lock,flags);
3021 info->idle_mode = idle_mode;
3022 tx_set_idle( info );
3023 spin_unlock_irqrestore(&info->lock,flags);
3027 static int tx_enable(SLMP_INFO * info, int enable)
3029 unsigned long flags;
3031 if (debug_level >= DEBUG_LEVEL_INFO)
3032 printk("%s(%d):%s tx_enable(%d)\n",
3033 __FILE__,__LINE__,info->device_name, enable);
3035 spin_lock_irqsave(&info->lock,flags);
3037 if ( !info->tx_enabled ) {
3041 if ( info->tx_enabled )
3044 spin_unlock_irqrestore(&info->lock,flags);
3048 /* abort send HDLC frame
3050 static int tx_abort(SLMP_INFO * info)
3052 unsigned long flags;
3054 if (debug_level >= DEBUG_LEVEL_INFO)
3055 printk("%s(%d):%s tx_abort()\n",
3056 __FILE__,__LINE__,info->device_name);
3058 spin_lock_irqsave(&info->lock,flags);
3059 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3060 info->ie1_value &= ~UDRN;
3061 info->ie1_value |= IDLE;
3062 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
3063 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
3065 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
3066 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3068 write_reg(info, CMD, TXABORT);
3070 spin_unlock_irqrestore(&info->lock,flags);
3074 static int rx_enable(SLMP_INFO * info, int enable)
3076 unsigned long flags;
3078 if (debug_level >= DEBUG_LEVEL_INFO)
3079 printk("%s(%d):%s rx_enable(%d)\n",
3080 __FILE__,__LINE__,info->device_name,enable);
3082 spin_lock_irqsave(&info->lock,flags);
3084 if ( !info->rx_enabled )
3087 if ( info->rx_enabled )
3090 spin_unlock_irqrestore(&info->lock,flags);
3094 /* wait for specified event to occur
3096 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3098 unsigned long flags;
3101 struct mgsl_icount cprev, cnow;
3104 struct _input_signal_events oldsigs, newsigs;
3105 DECLARE_WAITQUEUE(wait, current);
3107 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3112 if (debug_level >= DEBUG_LEVEL_INFO)
3113 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3114 __FILE__,__LINE__,info->device_name,mask);
3116 spin_lock_irqsave(&info->lock,flags);
3118 /* return immediately if state matches requested events */
3120 s = info->serial_signals;
3123 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3124 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3125 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3126 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3128 spin_unlock_irqrestore(&info->lock,flags);
3132 /* save current irq counts */
3133 cprev = info->icount;
3134 oldsigs = info->input_signal_events;
3136 /* enable hunt and idle irqs if needed */
3137 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3138 unsigned char oldval = info->ie1_value;
3139 unsigned char newval = oldval +
3140 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3141 (mask & MgslEvent_IdleReceived ? IDLD:0);
3142 if ( oldval != newval ) {
3143 info->ie1_value = newval;
3144 write_reg(info, IE1, info->ie1_value);
3148 set_current_state(TASK_INTERRUPTIBLE);
3149 add_wait_queue(&info->event_wait_q, &wait);
3151 spin_unlock_irqrestore(&info->lock,flags);
3155 if (signal_pending(current)) {
3160 /* get current irq counts */
3161 spin_lock_irqsave(&info->lock,flags);
3162 cnow = info->icount;
3163 newsigs = info->input_signal_events;
3164 set_current_state(TASK_INTERRUPTIBLE);
3165 spin_unlock_irqrestore(&info->lock,flags);
3167 /* if no change, wait aborted for some reason */
3168 if (newsigs.dsr_up == oldsigs.dsr_up &&
3169 newsigs.dsr_down == oldsigs.dsr_down &&
3170 newsigs.dcd_up == oldsigs.dcd_up &&
3171 newsigs.dcd_down == oldsigs.dcd_down &&
3172 newsigs.cts_up == oldsigs.cts_up &&
3173 newsigs.cts_down == oldsigs.cts_down &&
3174 newsigs.ri_up == oldsigs.ri_up &&
3175 newsigs.ri_down == oldsigs.ri_down &&
3176 cnow.exithunt == cprev.exithunt &&
3177 cnow.rxidle == cprev.rxidle) {
3183 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3184 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3185 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3186 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3187 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3188 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3189 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3190 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3191 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3192 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3200 remove_wait_queue(&info->event_wait_q, &wait);
3201 set_current_state(TASK_RUNNING);
3204 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3205 spin_lock_irqsave(&info->lock,flags);
3206 if (!waitqueue_active(&info->event_wait_q)) {
3207 /* disable enable exit hunt mode/idle rcvd IRQs */
3208 info->ie1_value &= ~(FLGD|IDLD);
3209 write_reg(info, IE1, info->ie1_value);
3211 spin_unlock_irqrestore(&info->lock,flags);
3215 PUT_USER(rc, events, mask_ptr);
3220 static int modem_input_wait(SLMP_INFO *info,int arg)
3222 unsigned long flags;
3224 struct mgsl_icount cprev, cnow;
3225 DECLARE_WAITQUEUE(wait, current);
3227 /* save current irq counts */
3228 spin_lock_irqsave(&info->lock,flags);
3229 cprev = info->icount;
3230 add_wait_queue(&info->status_event_wait_q, &wait);
3231 set_current_state(TASK_INTERRUPTIBLE);
3232 spin_unlock_irqrestore(&info->lock,flags);
3236 if (signal_pending(current)) {
3241 /* get new irq counts */
3242 spin_lock_irqsave(&info->lock,flags);
3243 cnow = info->icount;
3244 set_current_state(TASK_INTERRUPTIBLE);
3245 spin_unlock_irqrestore(&info->lock,flags);
3247 /* if no change, wait aborted for some reason */
3248 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3249 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3254 /* check for change in caller specified modem input */
3255 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3256 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3257 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3258 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3265 remove_wait_queue(&info->status_event_wait_q, &wait);
3266 set_current_state(TASK_RUNNING);
3270 /* return the state of the serial control and status signals
3272 static int tiocmget(struct tty_struct *tty, struct file *file)
3274 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3275 unsigned int result;
3276 unsigned long flags;
3278 spin_lock_irqsave(&info->lock,flags);
3280 spin_unlock_irqrestore(&info->lock,flags);
3282 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3283 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3284 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3285 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3286 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3287 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3289 if (debug_level >= DEBUG_LEVEL_INFO)
3290 printk("%s(%d):%s tiocmget() value=%08X\n",
3291 __FILE__,__LINE__, info->device_name, result );
3295 /* set modem control signals (DTR/RTS)
3297 static int tiocmset(struct tty_struct *tty, struct file *file,
3298 unsigned int set, unsigned int clear)
3300 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3301 unsigned long flags;
3303 if (debug_level >= DEBUG_LEVEL_INFO)
3304 printk("%s(%d):%s tiocmset(%x,%x)\n",
3305 __FILE__,__LINE__,info->device_name, set, clear);
3307 if (set & TIOCM_RTS)
3308 info->serial_signals |= SerialSignal_RTS;
3309 if (set & TIOCM_DTR)
3310 info->serial_signals |= SerialSignal_DTR;
3311 if (clear & TIOCM_RTS)
3312 info->serial_signals &= ~SerialSignal_RTS;
3313 if (clear & TIOCM_DTR)
3314 info->serial_signals &= ~SerialSignal_DTR;
3316 spin_lock_irqsave(&info->lock,flags);
3318 spin_unlock_irqrestore(&info->lock,flags);
3325 /* Block the current process until the specified port is ready to open.
3327 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3330 DECLARE_WAITQUEUE(wait, current);
3332 bool do_clocal = false;
3333 bool extra_count = false;
3334 unsigned long flags;
3336 if (debug_level >= DEBUG_LEVEL_INFO)
3337 printk("%s(%d):%s block_til_ready()\n",
3338 __FILE__,__LINE__, tty->driver->name );
3340 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3341 /* nonblock mode is set or port is not enabled */
3342 /* just verify that callout device is not active */
3343 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3347 if (tty->termios->c_cflag & CLOCAL)
3350 /* Wait for carrier detect and the line to become
3351 * free (i.e., not in use by the callout). While we are in
3352 * this loop, info->port.count is dropped by one, so that
3353 * close() knows when to free things. We restore it upon
3354 * exit, either normal or abnormal.
3358 add_wait_queue(&info->port.open_wait, &wait);
3360 if (debug_level >= DEBUG_LEVEL_INFO)
3361 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3362 __FILE__,__LINE__, tty->driver->name, info->port.count );
3364 spin_lock_irqsave(&info->lock, flags);
3365 if (!tty_hung_up_p(filp)) {
3369 spin_unlock_irqrestore(&info->lock, flags);
3370 info->port.blocked_open++;
3373 if ((tty->termios->c_cflag & CBAUD)) {
3374 spin_lock_irqsave(&info->lock,flags);
3375 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3377 spin_unlock_irqrestore(&info->lock,flags);
3380 set_current_state(TASK_INTERRUPTIBLE);
3382 if (tty_hung_up_p(filp) || !(info->port.flags & ASYNC_INITIALIZED)){
3383 retval = (info->port.flags & ASYNC_HUP_NOTIFY) ?
3384 -EAGAIN : -ERESTARTSYS;
3388 spin_lock_irqsave(&info->lock,flags);
3390 spin_unlock_irqrestore(&info->lock,flags);
3392 if (!(info->port.flags & ASYNC_CLOSING) &&
3393 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3397 if (signal_pending(current)) {
3398 retval = -ERESTARTSYS;
3402 if (debug_level >= DEBUG_LEVEL_INFO)
3403 printk("%s(%d):%s block_til_ready() count=%d\n",
3404 __FILE__,__LINE__, tty->driver->name, info->port.count );
3409 set_current_state(TASK_RUNNING);
3410 remove_wait_queue(&info->port.open_wait, &wait);
3414 info->port.blocked_open--;
3416 if (debug_level >= DEBUG_LEVEL_INFO)
3417 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3418 __FILE__,__LINE__, tty->driver->name, info->port.count );
3421 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3426 static int alloc_dma_bufs(SLMP_INFO *info)
3428 unsigned short BuffersPerFrame;
3429 unsigned short BufferCount;
3431 // Force allocation to start at 64K boundary for each port.
3432 // This is necessary because *all* buffer descriptors for a port
3433 // *must* be in the same 64K block. All descriptors on a port
3434 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3435 // into the CBP register.
3436 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3438 /* Calculate the number of DMA buffers necessary to hold the */
3439 /* largest allowable frame size. Note: If the max frame size is */
3440 /* not an even multiple of the DMA buffer size then we need to */
3441 /* round the buffer count per frame up one. */
3443 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3444 if ( info->max_frame_size % SCABUFSIZE )
3447 /* calculate total number of data buffers (SCABUFSIZE) possible
3448 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3449 * for the descriptor list (BUFFERLISTSIZE).
3451 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3453 /* limit number of buffers to maximum amount of descriptors */
3454 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3455 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3457 /* use enough buffers to transmit one max size frame */
3458 info->tx_buf_count = BuffersPerFrame + 1;
3460 /* never use more than half the available buffers for transmit */
3461 if (info->tx_buf_count > (BufferCount/2))
3462 info->tx_buf_count = BufferCount/2;
3464 if (info->tx_buf_count > SCAMAXDESC)
3465 info->tx_buf_count = SCAMAXDESC;
3467 /* use remaining buffers for receive */
3468 info->rx_buf_count = BufferCount - info->tx_buf_count;
3470 if (info->rx_buf_count > SCAMAXDESC)
3471 info->rx_buf_count = SCAMAXDESC;
3473 if ( debug_level >= DEBUG_LEVEL_INFO )
3474 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3475 __FILE__,__LINE__, info->device_name,
3476 info->tx_buf_count,info->rx_buf_count);
3478 if ( alloc_buf_list( info ) < 0 ||
3479 alloc_frame_bufs(info,
3481 info->rx_buf_list_ex,
3482 info->rx_buf_count) < 0 ||
3483 alloc_frame_bufs(info,
3485 info->tx_buf_list_ex,
3486 info->tx_buf_count) < 0 ||
3487 alloc_tmp_rx_buf(info) < 0 ) {
3488 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3489 __FILE__,__LINE__, info->device_name);
3493 rx_reset_buffers( info );
3498 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3500 static int alloc_buf_list(SLMP_INFO *info)
3504 /* build list in adapter shared memory */
3505 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3506 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3507 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3509 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3511 /* Save virtual address pointers to the receive and */
3512 /* transmit buffer lists. (Receive 1st). These pointers will */
3513 /* be used by the processor to access the lists. */
3514 info->rx_buf_list = (SCADESC *)info->buffer_list;
3516 info->tx_buf_list = (SCADESC *)info->buffer_list;
3517 info->tx_buf_list += info->rx_buf_count;
3519 /* Build links for circular buffer entry lists (tx and rx)
3521 * Note: links are physical addresses read by the SCA device
3522 * to determine the next buffer entry to use.
3525 for ( i = 0; i < info->rx_buf_count; i++ ) {
3526 /* calculate and store physical address of this buffer entry */
3527 info->rx_buf_list_ex[i].phys_entry =
3528 info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3530 /* calculate and store physical address of */
3531 /* next entry in cirular list of entries */
3532 info->rx_buf_list[i].next = info->buffer_list_phys;
3533 if ( i < info->rx_buf_count - 1 )
3534 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3536 info->rx_buf_list[i].length = SCABUFSIZE;
3539 for ( i = 0; i < info->tx_buf_count; i++ ) {
3540 /* calculate and store physical address of this buffer entry */
3541 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3542 ((info->rx_buf_count + i) * sizeof(SCADESC));
3544 /* calculate and store physical address of */
3545 /* next entry in cirular list of entries */
3547 info->tx_buf_list[i].next = info->buffer_list_phys +
3548 info->rx_buf_count * sizeof(SCADESC);
3550 if ( i < info->tx_buf_count - 1 )
3551 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3557 /* Allocate the frame DMA buffers used by the specified buffer list.
3559 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3562 unsigned long phys_addr;
3564 for ( i = 0; i < count; i++ ) {
3565 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3566 phys_addr = info->port_array[0]->last_mem_alloc;
3567 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3569 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3570 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3576 static void free_dma_bufs(SLMP_INFO *info)
3578 info->buffer_list = NULL;
3579 info->rx_buf_list = NULL;
3580 info->tx_buf_list = NULL;
3583 /* allocate buffer large enough to hold max_frame_size.
3584 * This buffer is used to pass an assembled frame to the line discipline.
3586 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3588 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3589 if (info->tmp_rx_buf == NULL)
3594 static void free_tmp_rx_buf(SLMP_INFO *info)
3596 kfree(info->tmp_rx_buf);
3597 info->tmp_rx_buf = NULL;
3600 static int claim_resources(SLMP_INFO *info)
3602 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3603 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3604 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3605 info->init_error = DiagStatus_AddressConflict;
3609 info->shared_mem_requested = true;
3611 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3612 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3613 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3614 info->init_error = DiagStatus_AddressConflict;
3618 info->lcr_mem_requested = true;
3620 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3621 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3622 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3623 info->init_error = DiagStatus_AddressConflict;
3627 info->sca_base_requested = true;
3629 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3630 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3631 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3632 info->init_error = DiagStatus_AddressConflict;
3636 info->sca_statctrl_requested = true;
3638 info->memory_base = ioremap_nocache(info->phys_memory_base,
3640 if (!info->memory_base) {
3641 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3642 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3643 info->init_error = DiagStatus_CantAssignPciResources;
3647 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3648 if (!info->lcr_base) {
3649 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3650 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3651 info->init_error = DiagStatus_CantAssignPciResources;
3654 info->lcr_base += info->lcr_offset;
3656 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3657 if (!info->sca_base) {
3658 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3659 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3660 info->init_error = DiagStatus_CantAssignPciResources;
3663 info->sca_base += info->sca_offset;
3665 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3667 if (!info->statctrl_base) {
3668 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3669 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3670 info->init_error = DiagStatus_CantAssignPciResources;
3673 info->statctrl_base += info->statctrl_offset;
3675 if ( !memory_test(info) ) {
3676 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3677 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3678 info->init_error = DiagStatus_MemoryError;
3685 release_resources( info );
3689 static void release_resources(SLMP_INFO *info)
3691 if ( debug_level >= DEBUG_LEVEL_INFO )
3692 printk( "%s(%d):%s release_resources() entry\n",
3693 __FILE__,__LINE__,info->device_name );
3695 if ( info->irq_requested ) {
3696 free_irq(info->irq_level, info);
3697 info->irq_requested = false;
3700 if ( info->shared_mem_requested ) {
3701 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3702 info->shared_mem_requested = false;
3704 if ( info->lcr_mem_requested ) {
3705 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3706 info->lcr_mem_requested = false;
3708 if ( info->sca_base_requested ) {
3709 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3710 info->sca_base_requested = false;
3712 if ( info->sca_statctrl_requested ) {
3713 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3714 info->sca_statctrl_requested = false;
3717 if (info->memory_base){
3718 iounmap(info->memory_base);
3719 info->memory_base = NULL;
3722 if (info->sca_base) {
3723 iounmap(info->sca_base - info->sca_offset);
3724 info->sca_base=NULL;
3727 if (info->statctrl_base) {
3728 iounmap(info->statctrl_base - info->statctrl_offset);
3729 info->statctrl_base=NULL;
3732 if (info->lcr_base){
3733 iounmap(info->lcr_base - info->lcr_offset);
3734 info->lcr_base = NULL;
3737 if ( debug_level >= DEBUG_LEVEL_INFO )
3738 printk( "%s(%d):%s release_resources() exit\n",
3739 __FILE__,__LINE__,info->device_name );
3742 /* Add the specified device instance data structure to the
3743 * global linked list of devices and increment the device count.
3745 static void add_device(SLMP_INFO *info)
3747 info->next_device = NULL;
3748 info->line = synclinkmp_device_count;
3749 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3751 if (info->line < MAX_DEVICES) {
3752 if (maxframe[info->line])
3753 info->max_frame_size = maxframe[info->line];
3754 info->dosyncppp = dosyncppp[info->line];
3757 synclinkmp_device_count++;
3759 if ( !synclinkmp_device_list )
3760 synclinkmp_device_list = info;
3762 SLMP_INFO *current_dev = synclinkmp_device_list;
3763 while( current_dev->next_device )
3764 current_dev = current_dev->next_device;
3765 current_dev->next_device = info;
3768 if ( info->max_frame_size < 4096 )
3769 info->max_frame_size = 4096;
3770 else if ( info->max_frame_size > 65535 )
3771 info->max_frame_size = 65535;
3773 printk( "SyncLink MultiPort %s: "
3774 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3776 info->phys_sca_base,
3777 info->phys_memory_base,
3778 info->phys_statctrl_base,
3779 info->phys_lcr_base,
3781 info->max_frame_size );
3783 #if SYNCLINK_GENERIC_HDLC
3788 /* Allocate and initialize a device instance structure
3790 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3792 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3796 info = kzalloc(sizeof(SLMP_INFO),
3800 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3801 __FILE__,__LINE__, adapter_num, port_num);
3803 tty_port_init(&info->port);
3804 info->magic = MGSL_MAGIC;
3805 INIT_WORK(&info->task, bh_handler);
3806 info->max_frame_size = 4096;
3807 info->port.close_delay = 5*HZ/10;
3808 info->port.closing_wait = 30*HZ;
3809 init_waitqueue_head(&info->status_event_wait_q);
3810 init_waitqueue_head(&info->event_wait_q);
3811 spin_lock_init(&info->netlock);
3812 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3813 info->idle_mode = HDLC_TXIDLE_FLAGS;
3814 info->adapter_num = adapter_num;
3815 info->port_num = port_num;
3817 /* Copy configuration info to device instance data */
3818 info->irq_level = pdev->irq;
3819 info->phys_lcr_base = pci_resource_start(pdev,0);
3820 info->phys_sca_base = pci_resource_start(pdev,2);
3821 info->phys_memory_base = pci_resource_start(pdev,3);
3822 info->phys_statctrl_base = pci_resource_start(pdev,4);
3824 /* Because veremap only works on page boundaries we must map
3825 * a larger area than is actually implemented for the LCR
3826 * memory range. We map a full page starting at the page boundary.
3828 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3829 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3831 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3832 info->phys_sca_base &= ~(PAGE_SIZE-1);
3834 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3835 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3837 info->bus_type = MGSL_BUS_TYPE_PCI;
3838 info->irq_flags = IRQF_SHARED;
3840 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3841 setup_timer(&info->status_timer, status_timeout,
3842 (unsigned long)info);
3844 /* Store the PCI9050 misc control register value because a flaw
3845 * in the PCI9050 prevents LCR registers from being read if
3846 * BIOS assigns an LCR base address with bit 7 set.
3848 * Only the misc control register is accessed for which only
3849 * write access is needed, so set an initial value and change
3850 * bits to the device instance data as we write the value
3851 * to the actual misc control register.
3853 info->misc_ctrl_value = 0x087e4546;
3855 /* initial port state is unknown - if startup errors
3856 * occur, init_error will be set to indicate the
3857 * problem. Once the port is fully initialized,
3858 * this value will be set to 0 to indicate the
3859 * port is available.
3861 info->init_error = -1;
3867 static void device_init(int adapter_num, struct pci_dev *pdev)
3869 SLMP_INFO *port_array[SCA_MAX_PORTS];
3872 /* allocate device instances for up to SCA_MAX_PORTS devices */
3873 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3874 port_array[port] = alloc_dev(adapter_num,port,pdev);
3875 if( port_array[port] == NULL ) {
3876 for ( --port; port >= 0; --port )
3877 kfree(port_array[port]);
3882 /* give copy of port_array to all ports and add to device list */
3883 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3884 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3885 add_device( port_array[port] );
3886 spin_lock_init(&port_array[port]->lock);
3889 /* Allocate and claim adapter resources */
3890 if ( !claim_resources(port_array[0]) ) {
3892 alloc_dma_bufs(port_array[0]);
3894 /* copy resource information from first port to others */
3895 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3896 port_array[port]->lock = port_array[0]->lock;
3897 port_array[port]->irq_level = port_array[0]->irq_level;
3898 port_array[port]->memory_base = port_array[0]->memory_base;
3899 port_array[port]->sca_base = port_array[0]->sca_base;
3900 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3901 port_array[port]->lcr_base = port_array[0]->lcr_base;
3902 alloc_dma_bufs(port_array[port]);
3905 if ( request_irq(port_array[0]->irq_level,
3906 synclinkmp_interrupt,
3907 port_array[0]->irq_flags,
3908 port_array[0]->device_name,
3909 port_array[0]) < 0 ) {
3910 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3912 port_array[0]->device_name,
3913 port_array[0]->irq_level );
3916 port_array[0]->irq_requested = true;
3917 adapter_test(port_array[0]);
3922 static const struct tty_operations ops = {
3926 .put_char = put_char,
3927 .flush_chars = flush_chars,
3928 .write_room = write_room,
3929 .chars_in_buffer = chars_in_buffer,
3930 .flush_buffer = flush_buffer,
3932 .throttle = throttle,
3933 .unthrottle = unthrottle,
3934 .send_xchar = send_xchar,
3935 .break_ctl = set_break,
3936 .wait_until_sent = wait_until_sent,
3937 .read_proc = read_proc,
3938 .set_termios = set_termios,
3940 .start = tx_release,
3942 .tiocmget = tiocmget,
3943 .tiocmset = tiocmset,
3946 static void synclinkmp_cleanup(void)
3952 printk("Unloading %s %s\n", driver_name, driver_version);
3954 if (serial_driver) {
3955 if ((rc = tty_unregister_driver(serial_driver)))
3956 printk("%s(%d) failed to unregister tty driver err=%d\n",
3957 __FILE__,__LINE__,rc);
3958 put_tty_driver(serial_driver);
3962 info = synclinkmp_device_list;
3965 info = info->next_device;
3968 /* release devices */
3969 info = synclinkmp_device_list;
3971 #if SYNCLINK_GENERIC_HDLC
3974 free_dma_bufs(info);
3975 free_tmp_rx_buf(info);
3976 if ( info->port_num == 0 ) {
3978 write_reg(info, LPR, 1); /* set low power mode */
3979 release_resources(info);
3982 info = info->next_device;
3986 pci_unregister_driver(&synclinkmp_pci_driver);
3989 /* Driver initialization entry point.
3992 static int __init synclinkmp_init(void)
3996 if (break_on_load) {
3997 synclinkmp_get_text_ptr();
4001 printk("%s %s\n", driver_name, driver_version);
4003 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4004 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4008 serial_driver = alloc_tty_driver(128);
4009 if (!serial_driver) {
4014 /* Initialize the tty_driver structure */
4016 serial_driver->owner = THIS_MODULE;
4017 serial_driver->driver_name = "synclinkmp";
4018 serial_driver->name = "ttySLM";
4019 serial_driver->major = ttymajor;
4020 serial_driver->minor_start = 64;
4021 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4022 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4023 serial_driver->init_termios = tty_std_termios;
4024 serial_driver->init_termios.c_cflag =
4025 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4026 serial_driver->init_termios.c_ispeed = 9600;
4027 serial_driver->init_termios.c_ospeed = 9600;
4028 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4029 tty_set_operations(serial_driver, &ops);
4030 if ((rc = tty_register_driver(serial_driver)) < 0) {
4031 printk("%s(%d):Couldn't register serial driver\n",
4033 put_tty_driver(serial_driver);
4034 serial_driver = NULL;
4038 printk("%s %s, tty major#%d\n",
4039 driver_name, driver_version,
4040 serial_driver->major);
4045 synclinkmp_cleanup();
4049 static void __exit synclinkmp_exit(void)
4051 synclinkmp_cleanup();
4054 module_init(synclinkmp_init);
4055 module_exit(synclinkmp_exit);
4057 /* Set the port for internal loopback mode.
4058 * The TxCLK and RxCLK signals are generated from the BRG and
4059 * the TxD is looped back to the RxD internally.
4061 static void enable_loopback(SLMP_INFO *info, int enable)
4064 /* MD2 (Mode Register 2)
4065 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4067 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4069 /* degate external TxC clock source */
4070 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4071 write_control_reg(info);
4073 /* RXS/TXS (Rx/Tx clock source)
4074 * 07 Reserved, must be 0
4075 * 06..04 Clock Source, 100=BRG
4076 * 03..00 Clock Divisor, 0000=1
4078 write_reg(info, RXS, 0x40);
4079 write_reg(info, TXS, 0x40);
4082 /* MD2 (Mode Register 2)
4083 * 01..00 CNCT<1..0> Channel connection, 0=normal
4085 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4087 /* RXS/TXS (Rx/Tx clock source)
4088 * 07 Reserved, must be 0
4089 * 06..04 Clock Source, 000=RxC/TxC Pin
4090 * 03..00 Clock Divisor, 0000=1
4092 write_reg(info, RXS, 0x00);
4093 write_reg(info, TXS, 0x00);
4096 /* set LinkSpeed if available, otherwise default to 2Mbps */
4097 if (info->params.clock_speed)
4098 set_rate(info, info->params.clock_speed);
4100 set_rate(info, 3686400);
4103 /* Set the baud rate register to the desired speed
4105 * data_rate data rate of clock in bits per second
4106 * A data rate of 0 disables the AUX clock.
4108 static void set_rate( SLMP_INFO *info, u32 data_rate )
4111 unsigned char BRValue;
4114 /* fBRG = fCLK/(TMC * 2^BR)
4116 if (data_rate != 0) {
4117 Divisor = 14745600/data_rate;
4124 if (TMCValue != 1 && TMCValue != 2) {
4125 /* BRValue of 0 provides 50/50 duty cycle *only* when
4126 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4133 /* while TMCValue is too big for TMC register, divide
4134 * by 2 and increment BR exponent.
4136 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4139 write_reg(info, TXS,
4140 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4141 write_reg(info, RXS,
4142 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4143 write_reg(info, TMC, (unsigned char)TMCValue);
4146 write_reg(info, TXS,0);
4147 write_reg(info, RXS,0);
4148 write_reg(info, TMC, 0);
4154 static void rx_stop(SLMP_INFO *info)
4156 if (debug_level >= DEBUG_LEVEL_ISR)
4157 printk("%s(%d):%s rx_stop()\n",
4158 __FILE__,__LINE__, info->device_name );
4160 write_reg(info, CMD, RXRESET);
4162 info->ie0_value &= ~RXRDYE;
4163 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4165 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4166 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4167 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4169 info->rx_enabled = false;
4170 info->rx_overflow = false;
4173 /* enable the receiver
4175 static void rx_start(SLMP_INFO *info)
4179 if (debug_level >= DEBUG_LEVEL_ISR)
4180 printk("%s(%d):%s rx_start()\n",
4181 __FILE__,__LINE__, info->device_name );
4183 write_reg(info, CMD, RXRESET);
4185 if ( info->params.mode == MGSL_MODE_HDLC ) {
4186 /* HDLC, disabe IRQ on rxdata */
4187 info->ie0_value &= ~RXRDYE;
4188 write_reg(info, IE0, info->ie0_value);
4190 /* Reset all Rx DMA buffers and program rx dma */
4191 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4192 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4194 for (i = 0; i < info->rx_buf_count; i++) {
4195 info->rx_buf_list[i].status = 0xff;
4197 // throttle to 4 shared memory writes at a time to prevent
4198 // hogging local bus (keep latency time for DMA requests low).
4200 read_status_reg(info);
4202 info->current_rx_buf = 0;
4204 /* set current/1st descriptor address */
4205 write_reg16(info, RXDMA + CDA,
4206 info->rx_buf_list_ex[0].phys_entry);
4208 /* set new last rx descriptor address */
4209 write_reg16(info, RXDMA + EDA,
4210 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4212 /* set buffer length (shared by all rx dma data buffers) */
4213 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4215 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4216 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4218 /* async, enable IRQ on rxdata */
4219 info->ie0_value |= RXRDYE;
4220 write_reg(info, IE0, info->ie0_value);
4223 write_reg(info, CMD, RXENABLE);
4225 info->rx_overflow = false;
4226 info->rx_enabled = true;
4229 /* Enable the transmitter and send a transmit frame if
4230 * one is loaded in the DMA buffers.
4232 static void tx_start(SLMP_INFO *info)
4234 if (debug_level >= DEBUG_LEVEL_ISR)
4235 printk("%s(%d):%s tx_start() tx_count=%d\n",
4236 __FILE__,__LINE__, info->device_name,info->tx_count );
4238 if (!info->tx_enabled ) {
4239 write_reg(info, CMD, TXRESET);
4240 write_reg(info, CMD, TXENABLE);
4241 info->tx_enabled = true;
4244 if ( info->tx_count ) {
4246 /* If auto RTS enabled and RTS is inactive, then assert */
4247 /* RTS and set a flag indicating that the driver should */
4248 /* negate RTS when the transmission completes. */
4250 info->drop_rts_on_tx_done = false;
4252 if (info->params.mode != MGSL_MODE_ASYNC) {
4254 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4255 get_signals( info );
4256 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4257 info->serial_signals |= SerialSignal_RTS;
4258 set_signals( info );
4259 info->drop_rts_on_tx_done = true;
4263 write_reg16(info, TRC0,
4264 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4266 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4267 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4269 /* set TX CDA (current descriptor address) */
4270 write_reg16(info, TXDMA + CDA,
4271 info->tx_buf_list_ex[0].phys_entry);
4273 /* set TX EDA (last descriptor address) */
4274 write_reg16(info, TXDMA + EDA,
4275 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4277 /* enable underrun IRQ */
4278 info->ie1_value &= ~IDLE;
4279 info->ie1_value |= UDRN;
4280 write_reg(info, IE1, info->ie1_value);
4281 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4283 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4284 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4286 mod_timer(&info->tx_timer, jiffies +
4287 msecs_to_jiffies(5000));
4291 /* async, enable IRQ on txdata */
4292 info->ie0_value |= TXRDYE;
4293 write_reg(info, IE0, info->ie0_value);
4296 info->tx_active = true;
4300 /* stop the transmitter and DMA
4302 static void tx_stop( SLMP_INFO *info )
4304 if (debug_level >= DEBUG_LEVEL_ISR)
4305 printk("%s(%d):%s tx_stop()\n",
4306 __FILE__,__LINE__, info->device_name );
4308 del_timer(&info->tx_timer);
4310 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4311 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4313 write_reg(info, CMD, TXRESET);
4315 info->ie1_value &= ~(UDRN + IDLE);
4316 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4317 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4319 info->ie0_value &= ~TXRDYE;
4320 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4322 info->tx_enabled = false;
4323 info->tx_active = false;
4326 /* Fill the transmit FIFO until the FIFO is full or
4327 * there is no more data to load.
4329 static void tx_load_fifo(SLMP_INFO *info)
4333 /* do nothing is now tx data available and no XON/XOFF pending */
4335 if ( !info->tx_count && !info->x_char )
4338 /* load the Transmit FIFO until FIFOs full or all data sent */
4340 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4342 /* there is more space in the transmit FIFO and */
4343 /* there is more data in transmit buffer */
4345 if ( (info->tx_count > 1) && !info->x_char ) {
4347 TwoBytes[0] = info->tx_buf[info->tx_get++];
4348 if (info->tx_get >= info->max_frame_size)
4349 info->tx_get -= info->max_frame_size;
4350 TwoBytes[1] = info->tx_buf[info->tx_get++];
4351 if (info->tx_get >= info->max_frame_size)
4352 info->tx_get -= info->max_frame_size;
4354 write_reg16(info, TRB, *((u16 *)TwoBytes));
4356 info->tx_count -= 2;
4357 info->icount.tx += 2;
4359 /* only 1 byte left to transmit or 1 FIFO slot left */
4362 /* transmit pending high priority char */
4363 write_reg(info, TRB, info->x_char);
4366 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4367 if (info->tx_get >= info->max_frame_size)
4368 info->tx_get -= info->max_frame_size;
4376 /* Reset a port to a known state
4378 static void reset_port(SLMP_INFO *info)
4380 if (info->sca_base) {
4385 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4388 /* disable all port interrupts */
4389 info->ie0_value = 0;
4390 info->ie1_value = 0;
4391 info->ie2_value = 0;
4392 write_reg(info, IE0, info->ie0_value);
4393 write_reg(info, IE1, info->ie1_value);
4394 write_reg(info, IE2, info->ie2_value);
4396 write_reg(info, CMD, CHRESET);
4400 /* Reset all the ports to a known state.
4402 static void reset_adapter(SLMP_INFO *info)
4406 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4407 if (info->port_array[i])
4408 reset_port(info->port_array[i]);
4412 /* Program port for asynchronous communications.
4414 static void async_mode(SLMP_INFO *info)
4417 unsigned char RegValue;
4422 /* MD0, Mode Register 0
4424 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4425 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4426 * 03 Reserved, must be 0
4427 * 02 CRCCC, CRC Calculation, 0=disabled
4428 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4433 if (info->params.stop_bits != 1)
4435 write_reg(info, MD0, RegValue);
4437 /* MD1, Mode Register 1
4439 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4440 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4441 * 03..02 RXCHR<1..0>, rx char size
4442 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4447 switch (info->params.data_bits) {
4448 case 7: RegValue |= BIT4 + BIT2; break;
4449 case 6: RegValue |= BIT5 + BIT3; break;
4450 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4452 if (info->params.parity != ASYNC_PARITY_NONE) {
4454 if (info->params.parity == ASYNC_PARITY_ODD)
4457 write_reg(info, MD1, RegValue);
4459 /* MD2, Mode Register 2
4461 * 07..02 Reserved, must be 0
4462 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4467 if (info->params.loopback)
4468 RegValue |= (BIT1 + BIT0);
4469 write_reg(info, MD2, RegValue);
4471 /* RXS, Receive clock source
4473 * 07 Reserved, must be 0
4474 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4475 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4478 write_reg(info, RXS, RegValue);
4480 /* TXS, Transmit clock source
4482 * 07 Reserved, must be 0
4483 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4484 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4487 write_reg(info, TXS, RegValue);
4491 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4493 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4494 write_control_reg(info);
4498 /* RRC Receive Ready Control 0
4500 * 07..05 Reserved, must be 0
4501 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4503 write_reg(info, RRC, 0x00);
4505 /* TRC0 Transmit Ready Control 0
4507 * 07..05 Reserved, must be 0
4508 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4510 write_reg(info, TRC0, 0x10);
4512 /* TRC1 Transmit Ready Control 1
4514 * 07..05 Reserved, must be 0
4515 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4517 write_reg(info, TRC1, 0x1e);
4519 /* CTL, MSCI control register
4521 * 07..06 Reserved, set to 0
4522 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4523 * 04 IDLC, idle control, 0=mark 1=idle register
4524 * 03 BRK, break, 0=off 1 =on (async)
4525 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4526 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4527 * 00 RTS, RTS output control, 0=active 1=inactive
4532 if (!(info->serial_signals & SerialSignal_RTS))
4534 write_reg(info, CTL, RegValue);
4536 /* enable status interrupts */
4537 info->ie0_value |= TXINTE + RXINTE;
4538 write_reg(info, IE0, info->ie0_value);
4540 /* enable break detect interrupt */
4541 info->ie1_value = BRKD;
4542 write_reg(info, IE1, info->ie1_value);
4544 /* enable rx overrun interrupt */
4545 info->ie2_value = OVRN;
4546 write_reg(info, IE2, info->ie2_value);
4548 set_rate( info, info->params.data_rate * 16 );
4551 /* Program the SCA for HDLC communications.
4553 static void hdlc_mode(SLMP_INFO *info)
4555 unsigned char RegValue;
4558 // Can't use DPLL because SCA outputs recovered clock on RxC when
4559 // DPLL mode selected. This causes output contention with RxC receiver.
4560 // Use of DPLL would require external hardware to disable RxC receiver
4561 // when DPLL mode selected.
4562 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4564 /* disable DMA interrupts */
4565 write_reg(info, TXDMA + DIR, 0);
4566 write_reg(info, RXDMA + DIR, 0);
4568 /* MD0, Mode Register 0
4570 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4571 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4572 * 03 Reserved, must be 0
4573 * 02 CRCCC, CRC Calculation, 1=enabled
4574 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4575 * 00 CRC0, CRC initial value, 1 = all 1s
4580 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4582 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4584 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4585 RegValue |= BIT2 + BIT1;
4586 write_reg(info, MD0, RegValue);
4588 /* MD1, Mode Register 1
4590 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4591 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4592 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4593 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4598 write_reg(info, MD1, RegValue);
4600 /* MD2, Mode Register 2
4602 * 07 NRZFM, 0=NRZ, 1=FM
4603 * 06..05 CODE<1..0> Encoding, 00=NRZ
4604 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4605 * 02 Reserved, must be 0
4606 * 01..00 CNCT<1..0> Channel connection, 0=normal
4611 switch(info->params.encoding) {
4612 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4613 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4614 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4615 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4617 case HDLC_ENCODING_NRZB: /* not supported */
4618 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4619 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4622 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4625 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4631 write_reg(info, MD2, RegValue);
4634 /* RXS, Receive clock source
4636 * 07 Reserved, must be 0
4637 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4638 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4641 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4643 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4644 RegValue |= BIT6 + BIT5;
4645 write_reg(info, RXS, RegValue);
4647 /* TXS, Transmit clock source
4649 * 07 Reserved, must be 0
4650 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4651 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4654 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4656 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4657 RegValue |= BIT6 + BIT5;
4658 write_reg(info, TXS, RegValue);
4660 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4661 set_rate(info, info->params.clock_speed * DpllDivisor);
4663 set_rate(info, info->params.clock_speed);
4665 /* GPDATA (General Purpose I/O Data Register)
4667 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4669 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4670 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4672 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4673 write_control_reg(info);
4675 /* RRC Receive Ready Control 0
4677 * 07..05 Reserved, must be 0
4678 * 04..00 RRC<4..0> Rx FIFO trigger active
4680 write_reg(info, RRC, rx_active_fifo_level);
4682 /* TRC0 Transmit Ready Control 0
4684 * 07..05 Reserved, must be 0
4685 * 04..00 TRC<4..0> Tx FIFO trigger active
4687 write_reg(info, TRC0, tx_active_fifo_level);
4689 /* TRC1 Transmit Ready Control 1
4691 * 07..05 Reserved, must be 0
4692 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4694 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4696 /* DMR, DMA Mode Register
4698 * 07..05 Reserved, must be 0
4699 * 04 TMOD, Transfer Mode: 1=chained-block
4700 * 03 Reserved, must be 0
4701 * 02 NF, Number of Frames: 1=multi-frame
4702 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4703 * 00 Reserved, must be 0
4707 write_reg(info, TXDMA + DMR, 0x14);
4708 write_reg(info, RXDMA + DMR, 0x14);
4710 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4711 write_reg(info, RXDMA + CPB,
4712 (unsigned char)(info->buffer_list_phys >> 16));
4714 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4715 write_reg(info, TXDMA + CPB,
4716 (unsigned char)(info->buffer_list_phys >> 16));
4718 /* enable status interrupts. other code enables/disables
4719 * the individual sources for these two interrupt classes.
4721 info->ie0_value |= TXINTE + RXINTE;
4722 write_reg(info, IE0, info->ie0_value);
4724 /* CTL, MSCI control register
4726 * 07..06 Reserved, set to 0
4727 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4728 * 04 IDLC, idle control, 0=mark 1=idle register
4729 * 03 BRK, break, 0=off 1 =on (async)
4730 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4731 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4732 * 00 RTS, RTS output control, 0=active 1=inactive
4737 if (!(info->serial_signals & SerialSignal_RTS))
4739 write_reg(info, CTL, RegValue);
4741 /* preamble not supported ! */
4747 set_rate(info, info->params.clock_speed);
4749 if (info->params.loopback)
4750 enable_loopback(info,1);
4753 /* Set the transmit HDLC idle mode
4755 static void tx_set_idle(SLMP_INFO *info)
4757 unsigned char RegValue = 0xff;
4759 /* Map API idle mode to SCA register bits */
4760 switch(info->idle_mode) {
4761 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4762 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4763 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4764 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4765 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4766 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4767 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4770 write_reg(info, IDL, RegValue);
4773 /* Query the adapter for the state of the V24 status (input) signals.
4775 static void get_signals(SLMP_INFO *info)
4777 u16 status = read_reg(info, SR3);
4778 u16 gpstatus = read_status_reg(info);
4781 /* clear all serial signals except DTR and RTS */
4782 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4784 /* set serial signal bits to reflect MISR */
4786 if (!(status & BIT3))
4787 info->serial_signals |= SerialSignal_CTS;
4789 if ( !(status & BIT2))
4790 info->serial_signals |= SerialSignal_DCD;
4792 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4793 if (!(gpstatus & testbit))
4794 info->serial_signals |= SerialSignal_RI;
4796 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4797 if (!(gpstatus & testbit))
4798 info->serial_signals |= SerialSignal_DSR;
4801 /* Set the state of DTR and RTS based on contents of
4802 * serial_signals member of device context.
4804 static void set_signals(SLMP_INFO *info)
4806 unsigned char RegValue;
4809 RegValue = read_reg(info, CTL);
4810 if (info->serial_signals & SerialSignal_RTS)
4814 write_reg(info, CTL, RegValue);
4816 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4817 EnableBit = BIT1 << (info->port_num*2);
4818 if (info->serial_signals & SerialSignal_DTR)
4819 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4821 info->port_array[0]->ctrlreg_value |= EnableBit;
4822 write_control_reg(info);
4825 /*******************/
4826 /* DMA Buffer Code */
4827 /*******************/
4829 /* Set the count for all receive buffers to SCABUFSIZE
4830 * and set the current buffer to the first buffer. This effectively
4831 * makes all buffers free and discards any data in buffers.
4833 static void rx_reset_buffers(SLMP_INFO *info)
4835 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4838 /* Free the buffers used by a received frame
4840 * info pointer to device instance data
4841 * first index of 1st receive buffer of frame
4842 * last index of last receive buffer of frame
4844 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4849 /* reset current buffer for reuse */
4850 info->rx_buf_list[first].status = 0xff;
4852 if (first == last) {
4854 /* set new last rx descriptor address */
4855 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4859 if (first == info->rx_buf_count)
4863 /* set current buffer to next buffer after last buffer of frame */
4864 info->current_rx_buf = first;
4867 /* Return a received frame from the receive DMA buffers.
4868 * Only frames received without errors are returned.
4870 * Return Value: true if frame returned, otherwise false
4872 static bool rx_get_frame(SLMP_INFO *info)
4874 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4875 unsigned short status;
4876 unsigned int framesize = 0;
4877 bool ReturnCode = false;
4878 unsigned long flags;
4879 struct tty_struct *tty = info->port.tty;
4880 unsigned char addr_field = 0xff;
4882 SCADESC_EX *desc_ex;
4885 /* assume no frame returned, set zero length */
4890 * current_rx_buf points to the 1st buffer of the next available
4891 * receive frame. To find the last buffer of the frame look for
4892 * a non-zero status field in the buffer entries. (The status
4893 * field is set by the 16C32 after completing a receive frame.
4895 StartIndex = EndIndex = info->current_rx_buf;
4898 desc = &info->rx_buf_list[EndIndex];
4899 desc_ex = &info->rx_buf_list_ex[EndIndex];
4901 if (desc->status == 0xff)
4902 goto Cleanup; /* current desc still in use, no frames available */
4904 if (framesize == 0 && info->params.addr_filter != 0xff)
4905 addr_field = desc_ex->virt_addr[0];
4907 framesize += desc->length;
4909 /* Status != 0 means last buffer of frame */
4914 if (EndIndex == info->rx_buf_count)
4917 if (EndIndex == info->current_rx_buf) {
4918 /* all buffers have been 'used' but none mark */
4919 /* the end of a frame. Reset buffers and receiver. */
4920 if ( info->rx_enabled ){
4921 spin_lock_irqsave(&info->lock,flags);
4923 spin_unlock_irqrestore(&info->lock,flags);
4930 /* check status of receive frame */
4932 /* frame status is byte stored after frame data
4934 * 7 EOM (end of msg), 1 = last buffer of frame
4935 * 6 Short Frame, 1 = short frame
4936 * 5 Abort, 1 = frame aborted
4937 * 4 Residue, 1 = last byte is partial
4938 * 3 Overrun, 1 = overrun occurred during frame reception
4939 * 2 CRC, 1 = CRC error detected
4942 status = desc->status;
4944 /* ignore CRC bit if not using CRC (bit is undefined) */
4945 /* Note:CRC is not save to data buffer */
4946 if (info->params.crc_type == HDLC_CRC_NONE)
4949 if (framesize == 0 ||
4950 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4951 /* discard 0 byte frames, this seems to occur sometime
4952 * when remote is idling flags.
4954 rx_free_frame_buffers(info, StartIndex, EndIndex);
4961 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4962 /* received frame has errors,
4963 * update counts and mark frame size as 0
4966 info->icount.rxshort++;
4967 else if (status & BIT5)
4968 info->icount.rxabort++;
4969 else if (status & BIT3)
4970 info->icount.rxover++;
4972 info->icount.rxcrc++;
4975 #if SYNCLINK_GENERIC_HDLC
4977 info->netdev->stats.rx_errors++;
4978 info->netdev->stats.rx_frame_errors++;
4983 if ( debug_level >= DEBUG_LEVEL_BH )
4984 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4985 __FILE__,__LINE__,info->device_name,status,framesize);
4987 if ( debug_level >= DEBUG_LEVEL_DATA )
4988 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4989 min_t(int, framesize,SCABUFSIZE),0);
4992 if (framesize > info->max_frame_size)
4993 info->icount.rxlong++;
4995 /* copy dma buffer(s) to contiguous intermediate buffer */
4996 int copy_count = framesize;
4997 int index = StartIndex;
4998 unsigned char *ptmp = info->tmp_rx_buf;
4999 info->tmp_rx_buf_count = framesize;
5001 info->icount.rxok++;
5004 int partial_count = min(copy_count,SCABUFSIZE);
5006 info->rx_buf_list_ex[index].virt_addr,
5008 ptmp += partial_count;
5009 copy_count -= partial_count;
5011 if ( ++index == info->rx_buf_count )
5015 #if SYNCLINK_GENERIC_HDLC
5017 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5020 ldisc_receive_buf(tty,info->tmp_rx_buf,
5021 info->flag_buf, framesize);
5024 /* Free the buffers used by this frame. */
5025 rx_free_frame_buffers( info, StartIndex, EndIndex );
5030 if ( info->rx_enabled && info->rx_overflow ) {
5031 /* Receiver is enabled, but needs to restarted due to
5032 * rx buffer overflow. If buffers are empty, restart receiver.
5034 if (info->rx_buf_list[EndIndex].status == 0xff) {
5035 spin_lock_irqsave(&info->lock,flags);
5037 spin_unlock_irqrestore(&info->lock,flags);
5044 /* load the transmit DMA buffer with data
5046 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5048 unsigned short copy_count;
5051 SCADESC_EX *desc_ex;
5053 if ( debug_level >= DEBUG_LEVEL_DATA )
5054 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5056 /* Copy source buffer to one or more DMA buffers, starting with
5057 * the first transmit dma buffer.
5061 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5063 desc = &info->tx_buf_list[i];
5064 desc_ex = &info->tx_buf_list_ex[i];
5066 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5068 desc->length = copy_count;
5072 count -= copy_count;
5078 if (i >= info->tx_buf_count)
5082 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5083 info->last_tx_buf = ++i;
5086 static bool register_test(SLMP_INFO *info)
5088 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5089 static unsigned int count = ARRAY_SIZE(testval);
5092 unsigned long flags;
5094 spin_lock_irqsave(&info->lock,flags);
5097 /* assume failure */
5098 info->init_error = DiagStatus_AddressFailure;
5100 /* Write bit patterns to various registers but do it out of */
5101 /* sync, then read back and verify values. */
5103 for (i = 0 ; i < count ; i++) {
5104 write_reg(info, TMC, testval[i]);
5105 write_reg(info, IDL, testval[(i+1)%count]);
5106 write_reg(info, SA0, testval[(i+2)%count]);
5107 write_reg(info, SA1, testval[(i+3)%count]);
5109 if ( (read_reg(info, TMC) != testval[i]) ||
5110 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5111 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5112 (read_reg(info, SA1) != testval[(i+3)%count]) )
5120 spin_unlock_irqrestore(&info->lock,flags);
5125 static bool irq_test(SLMP_INFO *info)
5127 unsigned long timeout;
5128 unsigned long flags;
5130 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5132 spin_lock_irqsave(&info->lock,flags);
5135 /* assume failure */
5136 info->init_error = DiagStatus_IrqFailure;
5137 info->irq_occurred = false;
5139 /* setup timer0 on SCA0 to interrupt */
5141 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5142 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5144 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5145 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5148 /* TMCS, Timer Control/Status Register
5150 * 07 CMF, Compare match flag (read only) 1=match
5151 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5152 * 05 Reserved, must be 0
5153 * 04 TME, Timer Enable
5154 * 03..00 Reserved, must be 0
5158 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5160 spin_unlock_irqrestore(&info->lock,flags);
5163 while( timeout-- && !info->irq_occurred ) {
5164 msleep_interruptible(10);
5167 spin_lock_irqsave(&info->lock,flags);
5169 spin_unlock_irqrestore(&info->lock,flags);
5171 return info->irq_occurred;
5174 /* initialize individual SCA device (2 ports)
5176 static bool sca_init(SLMP_INFO *info)
5178 /* set wait controller to single mem partition (low), no wait states */
5179 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5180 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5181 write_reg(info, WCRL, 0); /* wait controller low range */
5182 write_reg(info, WCRM, 0); /* wait controller mid range */
5183 write_reg(info, WCRH, 0); /* wait controller high range */
5185 /* DPCR, DMA Priority Control
5187 * 07..05 Not used, must be 0
5188 * 04 BRC, bus release condition: 0=all transfers complete
5189 * 03 CCC, channel change condition: 0=every cycle
5190 * 02..00 PR<2..0>, priority 100=round robin
5194 write_reg(info, DPCR, dma_priority);
5196 /* DMA Master Enable, BIT7: 1=enable all channels */
5197 write_reg(info, DMER, 0x80);
5199 /* enable all interrupt classes */
5200 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5201 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5202 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5204 /* ITCR, interrupt control register
5205 * 07 IPC, interrupt priority, 0=MSCI->DMA
5206 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5207 * 04 VOS, Vector Output, 0=unmodified vector
5208 * 03..00 Reserved, must be 0
5210 write_reg(info, ITCR, 0);
5215 /* initialize adapter hardware
5217 static bool init_adapter(SLMP_INFO *info)
5221 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5222 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5225 info->misc_ctrl_value |= BIT30;
5226 *MiscCtrl = info->misc_ctrl_value;
5229 * Force at least 170ns delay before clearing
5230 * reset bit. Each read from LCR takes at least
5231 * 30ns so 10 times for 300ns to be safe.
5234 readval = *MiscCtrl;
5236 info->misc_ctrl_value &= ~BIT30;
5237 *MiscCtrl = info->misc_ctrl_value;
5239 /* init control reg (all DTRs off, all clksel=input) */
5240 info->ctrlreg_value = 0xaa;
5241 write_control_reg(info);
5244 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5245 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5247 switch(read_ahead_count)
5250 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5253 lcr1_brdr_value |= BIT5 + BIT4;
5256 lcr1_brdr_value |= BIT5 + BIT3;
5259 lcr1_brdr_value |= BIT5;
5263 *LCR1BRDR = lcr1_brdr_value;
5264 *MiscCtrl = misc_ctrl_value;
5267 sca_init(info->port_array[0]);
5268 sca_init(info->port_array[2]);
5273 /* Loopback an HDLC frame to test the hardware
5274 * interrupt and DMA functions.
5276 static bool loopback_test(SLMP_INFO *info)
5278 #define TESTFRAMESIZE 20
5280 unsigned long timeout;
5281 u16 count = TESTFRAMESIZE;
5282 unsigned char buf[TESTFRAMESIZE];
5284 unsigned long flags;
5286 struct tty_struct *oldtty = info->port.tty;
5287 u32 speed = info->params.clock_speed;
5289 info->params.clock_speed = 3686400;
5290 info->port.tty = NULL;
5292 /* assume failure */
5293 info->init_error = DiagStatus_DmaFailure;
5295 /* build and send transmit frame */
5296 for (count = 0; count < TESTFRAMESIZE;++count)
5297 buf[count] = (unsigned char)count;
5299 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5301 /* program hardware for HDLC and enabled receiver */
5302 spin_lock_irqsave(&info->lock,flags);
5304 enable_loopback(info,1);
5306 info->tx_count = count;
5307 tx_load_dma_buffer(info,buf,count);
5309 spin_unlock_irqrestore(&info->lock,flags);
5311 /* wait for receive complete */
5312 /* Set a timeout for waiting for interrupt. */
5313 for ( timeout = 100; timeout; --timeout ) {
5314 msleep_interruptible(10);
5316 if (rx_get_frame(info)) {
5322 /* verify received frame length and contents */
5324 ( info->tmp_rx_buf_count != count ||
5325 memcmp(buf, info->tmp_rx_buf,count))) {
5329 spin_lock_irqsave(&info->lock,flags);
5330 reset_adapter(info);
5331 spin_unlock_irqrestore(&info->lock,flags);
5333 info->params.clock_speed = speed;
5334 info->port.tty = oldtty;
5339 /* Perform diagnostics on hardware
5341 static int adapter_test( SLMP_INFO *info )
5343 unsigned long flags;
5344 if ( debug_level >= DEBUG_LEVEL_INFO )
5345 printk( "%s(%d):Testing device %s\n",
5346 __FILE__,__LINE__,info->device_name );
5348 spin_lock_irqsave(&info->lock,flags);
5350 spin_unlock_irqrestore(&info->lock,flags);
5352 info->port_array[0]->port_count = 0;
5354 if ( register_test(info->port_array[0]) &&
5355 register_test(info->port_array[1])) {
5357 info->port_array[0]->port_count = 2;
5359 if ( register_test(info->port_array[2]) &&
5360 register_test(info->port_array[3]) )
5361 info->port_array[0]->port_count += 2;
5364 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5365 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5369 if ( !irq_test(info->port_array[0]) ||
5370 !irq_test(info->port_array[1]) ||
5371 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5372 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5373 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5374 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5378 if (!loopback_test(info->port_array[0]) ||
5379 !loopback_test(info->port_array[1]) ||
5380 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5381 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5382 printk( "%s(%d):DMA test failure for device %s\n",
5383 __FILE__,__LINE__,info->device_name);
5387 if ( debug_level >= DEBUG_LEVEL_INFO )
5388 printk( "%s(%d):device %s passed diagnostics\n",
5389 __FILE__,__LINE__,info->device_name );
5391 info->port_array[0]->init_error = 0;
5392 info->port_array[1]->init_error = 0;
5393 if ( info->port_count > 2 ) {
5394 info->port_array[2]->init_error = 0;
5395 info->port_array[3]->init_error = 0;
5401 /* Test the shared memory on a PCI adapter.
5403 static bool memory_test(SLMP_INFO *info)
5405 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5406 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5407 unsigned long count = ARRAY_SIZE(testval);
5409 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5410 unsigned long * addr = (unsigned long *)info->memory_base;
5412 /* Test data lines with test pattern at one location. */
5414 for ( i = 0 ; i < count ; i++ ) {
5416 if ( *addr != testval[i] )
5420 /* Test address lines with incrementing pattern over */
5421 /* entire address range. */
5423 for ( i = 0 ; i < limit ; i++ ) {
5428 addr = (unsigned long *)info->memory_base;
5430 for ( i = 0 ; i < limit ; i++ ) {
5431 if ( *addr != i * 4 )
5436 memset( info->memory_base, 0, SCA_MEM_SIZE );
5440 /* Load data into PCI adapter shared memory.
5442 * The PCI9050 releases control of the local bus
5443 * after completing the current read or write operation.
5445 * While the PCI9050 write FIFO not empty, the
5446 * PCI9050 treats all of the writes as a single transaction
5447 * and does not release the bus. This causes DMA latency problems
5448 * at high speeds when copying large data blocks to the shared memory.
5450 * This function breaks a write into multiple transations by
5451 * interleaving a read which flushes the write FIFO and 'completes'
5452 * the write transation. This allows any pending DMA request to gain control
5453 * of the local bus in a timely fasion.
5455 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5457 /* A load interval of 16 allows for 4 32-bit writes at */
5458 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5460 unsigned short interval = count / sca_pci_load_interval;
5463 for ( i = 0 ; i < interval ; i++ )
5465 memcpy(dest, src, sca_pci_load_interval);
5466 read_status_reg(info);
5467 dest += sca_pci_load_interval;
5468 src += sca_pci_load_interval;
5471 memcpy(dest, src, count % sca_pci_load_interval);
5474 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5479 printk("%s tx data:\n",info->device_name);
5481 printk("%s rx data:\n",info->device_name);
5489 for(i=0;i<linecount;i++)
5490 printk("%02X ",(unsigned char)data[i]);
5493 for(i=0;i<linecount;i++) {
5494 if (data[i]>=040 && data[i]<=0176)
5495 printk("%c",data[i]);
5504 } /* end of trace_block() */
5506 /* called when HDLC frame times out
5507 * update stats and do tx completion processing
5509 static void tx_timeout(unsigned long context)
5511 SLMP_INFO *info = (SLMP_INFO*)context;
5512 unsigned long flags;
5514 if ( debug_level >= DEBUG_LEVEL_INFO )
5515 printk( "%s(%d):%s tx_timeout()\n",
5516 __FILE__,__LINE__,info->device_name);
5517 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5518 info->icount.txtimeout++;
5520 spin_lock_irqsave(&info->lock,flags);
5521 info->tx_active = false;
5522 info->tx_count = info->tx_put = info->tx_get = 0;
5524 spin_unlock_irqrestore(&info->lock,flags);
5526 #if SYNCLINK_GENERIC_HDLC
5528 hdlcdev_tx_done(info);
5534 /* called to periodically check the DSR/RI modem signal input status
5536 static void status_timeout(unsigned long context)
5539 SLMP_INFO *info = (SLMP_INFO*)context;
5540 unsigned long flags;
5541 unsigned char delta;
5544 spin_lock_irqsave(&info->lock,flags);
5546 spin_unlock_irqrestore(&info->lock,flags);
5548 /* check for DSR/RI state change */
5550 delta = info->old_signals ^ info->serial_signals;
5551 info->old_signals = info->serial_signals;
5553 if (delta & SerialSignal_DSR)
5554 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5556 if (delta & SerialSignal_RI)
5557 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5559 if (delta & SerialSignal_DCD)
5560 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5562 if (delta & SerialSignal_CTS)
5563 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5566 isr_io_pin(info,status);
5568 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5572 /* Register Access Routines -
5573 * All registers are memory mapped
5575 #define CALC_REGADDR() \
5576 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5577 if (info->port_num > 1) \
5578 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5579 if ( info->port_num & 1) { \
5581 RegAddr += 0x40; /* DMA access */ \
5582 else if (Addr > 0x1f && Addr < 0x60) \
5583 RegAddr += 0x20; /* MSCI access */ \
5587 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5592 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5598 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5601 return *((u16 *)RegAddr);
5604 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5607 *((u16 *)RegAddr) = Value;
5610 static unsigned char read_status_reg(SLMP_INFO * info)
5612 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5616 static void write_control_reg(SLMP_INFO * info)
5618 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5619 *RegAddr = info->port_array[0]->ctrlreg_value;
5623 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5624 const struct pci_device_id *ent)
5626 if (pci_enable_device(dev)) {
5627 printk("error enabling pci device %p\n", dev);
5630 device_init( ++synclinkmp_adapter_count, dev );
5634 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)