drivers/char/watchdog/pnx4008_wdt.c

   1 /*
   2  * drivers/char/watchdog/pnx4008_wdt.c
   3  *
   4  * Watchdog driver for PNX4008 board
   5  *
   6  * Authors: Dmitry Chigirev <source@mvista.com>,
   7  *          Vitaly Wool <vitalywool@gmail.com>
   8  * Based on sa1100 driver,
   9  * Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
  10  *
  11  * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
  12  * the terms of the GNU General Public License version 2. This program
  13  * is licensed "as is" without any warranty of any kind, whether express
  14  * or implied.
  15  */
  16
  17 #include <linux/config.h>
  18 #include <linux/module.h>
  19 #include <linux/moduleparam.h>
  20 #include <linux/types.h>
  21 #include <linux/kernel.h>
  22 #include <linux/fs.h>
  23 #include <linux/miscdevice.h>
  24 #include <linux/watchdog.h>
  25 #include <linux/init.h>
  26 #include <linux/bitops.h>
  27 #include <linux/ioport.h>
  28 #include <linux/device.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/clk.h>
  31
  32 #include <asm/hardware.h>
  33 #include <asm/uaccess.h>
  34 #include <asm/io.h>
  35
  36 #define MODULE_NAME "PNX4008-WDT: "
  37
  38 /* WatchDog Timer - Chapter 23 Page 207 */
  39
  40 #define DEFAULT_HEARTBEAT 19
  41 #define MAX_HEARTBEAT     60
  42
  43 /* Watchdog timer register set definition */
  44 #define WDTIM_INT(p)     ((p) + 0x0)
  45 #define WDTIM_CTRL(p)    ((p) + 0x4)
  46 #define WDTIM_COUNTER(p) ((p) + 0x8)
  47 #define WDTIM_MCTRL(p)   ((p) + 0xC)
  48 #define WDTIM_MATCH0(p)  ((p) + 0x10)
  49 #define WDTIM_EMR(p)     ((p) + 0x14)
  50 #define WDTIM_PULSE(p)   ((p) + 0x18)
  51 #define WDTIM_RES(p)     ((p) + 0x1C)
  52
  53 /* WDTIM_INT bit definitions */
  54 #define MATCH_INT      1
  55
  56 /* WDTIM_CTRL bit definitions */
  57 #define COUNT_ENAB     1
  58 #define RESET_COUNT    (1<<1)
  59 #define DEBUG_EN       (1<<2)
  60
  61 /* WDTIM_MCTRL bit definitions */
  62 #define MR0_INT        1
  63 #undef  RESET_COUNT0
  64 #define RESET_COUNT0   (1<<2)
  65 #define STOP_COUNT0    (1<<2)
  66 #define M_RES1         (1<<3)
  67 #define M_RES2         (1<<4)
  68 #define RESFRC1        (1<<5)
  69 #define RESFRC2        (1<<6)
  70
  71 /* WDTIM_EMR bit definitions */
  72 #define EXT_MATCH0      1
  73 #define MATCH_OUTPUT_HIGH (2<<4)        /*a MATCH_CTRL setting */
  74
  75 /* WDTIM_RES bit definitions */
  76 #define WDOG_RESET      1       /* read only */
  77
  78 #define WDOG_COUNTER_RATE 13000000      /*the counter clock is 13 MHz fixed */
  79
  80 static int nowayout = WATCHDOG_NOWAYOUT;
  81 static int heartbeat = DEFAULT_HEARTBEAT;
  82
  83 static unsigned long wdt_status;
  84 #define WDT_IN_USE        0
  85 #define WDT_OK_TO_CLOSE   1
  86 #define WDT_REGION_INITED 2
  87 #define WDT_DEVICE_INITED 3
  88
  89 static unsigned long boot_status;
  90
  91 static struct resource  *wdt_mem;
  92 static void __iomem     *wdt_base;
  93 struct clk              *wdt_clk;
  94
  95 static void wdt_enable(void)
  96 {
  97         if (wdt_clk)
  98                 clk_set_rate(wdt_clk, 1);
  99
 100         /* stop counter, initiate counter reset */
 101         __raw_writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
 102         /*wait for reset to complete. 100% guarantee event */
 103         while (__raw_readl(WDTIM_COUNTER(wdt_base)));
 104         /* internal and external reset, stop after that */
 105         __raw_writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0,
 106                 WDTIM_MCTRL(wdt_base));
 107         /* configure match output */
 108         __raw_writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
 109         /* clear interrupt, just in case */
 110         __raw_writel(MATCH_INT, WDTIM_INT(wdt_base));
 111         /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */
 112         __raw_writel(0xFFFF, WDTIM_PULSE(wdt_base));
 113         __raw_writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
 114         /*enable counter, stop when debugger active */
 115         __raw_writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base));
 116 }
 117
 118 static void wdt_disable(void)
 119 {
 120         __raw_writel(0, WDTIM_CTRL(wdt_base));  /*stop counter */
 121         if (wdt_clk)
 122                 clk_set_rate(wdt_clk, 0);
 123 }
 124
 125 static int pnx4008_wdt_open(struct inode *inode, struct file *file)
 126 {
 127         if (test_and_set_bit(WDT_IN_USE, &wdt_status))
 128                 return -EBUSY;
 129
 130         clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
 131
 132         wdt_enable();
 133
 134         return nonseekable_open(inode, file);
 135 }
 136
 137 static ssize_t
 138 pnx4008_wdt_write(struct file *file, const char *data, size_t len,
 139                   loff_t * ppos)
 140 {
 141         /*  Can't seek (pwrite) on this device  */
 142         if (ppos != &file->f_pos)
 143                 return -ESPIPE;
 144
 145         if (len) {
 146                 if (!nowayout) {
 147                         size_t i;
 148
 149                         clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
 150
 151                         for (i = 0; i != len; i++) {
 152                                 char c;
 153
 154                                 if (get_user(c, data + i))
 155                                         return -EFAULT;
 156                                 if (c == 'V')
 157                                         set_bit(WDT_OK_TO_CLOSE, &wdt_status);
 158                         }
 159                 }
 160                 wdt_enable();
 161         }
 162
 163         return len;
 164 }
 165
 166 static struct watchdog_info ident = {
 167         .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE |
 168             WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
 169         .identity = "PNX4008 Watchdog",
 170 };
 171
 172 static int
 173 pnx4008_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
 174                   unsigned long arg)
 175 {
 176         int ret = -ENOIOCTLCMD;
 177         int time;
 178
 179         switch (cmd) {
 180         case WDIOC_GETSUPPORT:
 181                 ret = copy_to_user((struct watchdog_info *)arg, &ident,
 182                                    sizeof(ident)) ? -EFAULT : 0;
 183                 break;
 184
 185         case WDIOC_GETSTATUS:
 186                 ret = put_user(0, (int *)arg);
 187                 break;
 188
 189         case WDIOC_GETBOOTSTATUS:
 190                 ret = put_user(boot_status, (int *)arg);
 191                 break;
 192
 193         case WDIOC_SETTIMEOUT:
 194                 ret = get_user(time, (int *)arg);
 195                 if (ret)
 196                         break;
 197
 198                 if (time <= 0 || time > MAX_HEARTBEAT) {
 199                         ret = -EINVAL;
 200                         break;
 201                 }
 202
 203                 heartbeat = time;
 204                 wdt_enable();
 205                 /* Fall through */
 206
 207         case WDIOC_GETTIMEOUT:
 208                 ret = put_user(heartbeat, (int *)arg);
 209                 break;
 210
 211         case WDIOC_KEEPALIVE:
 212                 wdt_enable();
 213                 ret = 0;
 214                 break;
 215         }
 216         return ret;
 217 }
 218
 219 static int pnx4008_wdt_release(struct inode *inode, struct file *file)
 220 {
 221         if (!test_bit(WDT_OK_TO_CLOSE, &wdt_status))
 222                 printk(KERN_WARNING "WATCHDOG: Device closed unexpectdly\n");
 223
 224         wdt_disable();
 225         clear_bit(WDT_IN_USE, &wdt_status);
 226         clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
 227
 228         return 0;
 229 }
 230
 231 static struct file_operations pnx4008_wdt_fops = {
 232         .owner = THIS_MODULE,
 233         .llseek = no_llseek,
 234         .write = pnx4008_wdt_write,
 235         .ioctl = pnx4008_wdt_ioctl,
 236         .open = pnx4008_wdt_open,
 237         .release = pnx4008_wdt_release,
 238 };
 239
 240 static struct miscdevice pnx4008_wdt_miscdev = {
 241         .minor = WATCHDOG_MINOR,
 242         .name = "watchdog",
 243         .fops = &pnx4008_wdt_fops,
 244 };
 245
 246 static int pnx4008_wdt_probe(struct platform_device *pdev)
 247 {
 248         int ret = 0, size;
 249         struct resource *res;
 250
 251         if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
 252                 heartbeat = DEFAULT_HEARTBEAT;
 253
 254         printk(KERN_INFO MODULE_NAME
 255                 "PNX4008 Watchdog Timer: heartbeat %d sec\n", heartbeat);
 256
 257         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 258         if (res == NULL) {
 259                 printk(KERN_INFO MODULE_NAME
 260                         "failed to get memory region resouce\n");
 261                 return -ENOENT;
 262         }
 263
 264         size = res->end - res->start + 1;
 265         wdt_mem = request_mem_region(res->start, size, pdev->name);
 266
 267         if (wdt_mem == NULL) {
 268                 printk(KERN_INFO MODULE_NAME "failed to get memory region\n");
 269                 return -ENOENT;
 270         }
 271         wdt_base = (void __iomem *)IO_ADDRESS(res->start);
 272
 273         wdt_clk = clk_get(&pdev->dev, "wdt_ck");
 274         if (!wdt_clk) {
 275                 release_resource(wdt_mem);
 276                 kfree(wdt_mem);
 277                 goto out;
 278         } else
 279                 clk_set_rate(wdt_clk, 1);
 280
 281         ret = misc_register(&pnx4008_wdt_miscdev);
 282         if (ret < 0) {
 283                 printk(KERN_ERR MODULE_NAME "cannot register misc device\n");
 284                 release_resource(wdt_mem);
 285                 kfree(wdt_mem);
 286                 clk_set_rate(wdt_clk, 0);
 287         } else {
 288                 boot_status = (__raw_readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
 289                     WDIOF_CARDRESET : 0;
 290                 wdt_disable();          /*disable for now */
 291                 set_bit(WDT_DEVICE_INITED, &wdt_status);
 292         }
 293
 294 out:
 295         return ret;
 296 }
 297
 298 static int pnx4008_wdt_remove(struct platform_device *pdev)
 299 {
 300         misc_deregister(&pnx4008_wdt_miscdev);
 301         if (wdt_clk) {
 302                 clk_set_rate(wdt_clk, 0);
 303                 clk_put(wdt_clk);
 304                 wdt_clk = NULL;
 305         }
 306         if (wdt_mem) {
 307                 release_resource(wdt_mem);
 308                 kfree(wdt_mem);
 309                 wdt_mem = NULL;
 310         }
 311         return 0;
 312 }
 313
 314 static struct platform_driver platform_wdt_driver = {
 315         .driver = {
 316                 .name = "watchdog",
 317         },
 318         .probe = pnx4008_wdt_probe,
 319         .remove = pnx4008_wdt_remove,
 320 };
 321
 322 static int __init pnx4008_wdt_init(void)
 323 {
 324         return platform_driver_register(&platform_wdt_driver);
 325 }
 326
 327 static void __exit pnx4008_wdt_exit(void)
 328 {
 329         return platform_driver_unregister(&platform_wdt_driver);
 330 }
 331
 332 module_init(pnx4008_wdt_init);
 333 module_exit(pnx4008_wdt_exit);
 334
 335 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
 336 MODULE_DESCRIPTION("PNX4008 Watchdog Driver");
 337
 338 module_param(heartbeat, int, 0);
 339 MODULE_PARM_DESC(heartbeat,
 340                  "Watchdog heartbeat period in seconds from 1 to "
 341                  __MODULE_STRING(MAX_HEARTBEAT) ", default "
 342                  __MODULE_STRING(DEFAULT_HEARTBEAT));
 343
 344 module_param(nowayout, int, 0);
 345 MODULE_PARM_DESC(nowayout,
 346                  "Set to 1 to keep watchdog running after device release");
 347
 348 MODULE_LICENSE("GPL");
 349 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);