drivers/clk/at91/clk-main.c

   1 /*
   2  *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  */
  10
  11 #include <linux/clk-provider.h>
  12 #include <linux/clkdev.h>
  13 #include <linux/clk/at91_pmc.h>
  14 #include <linux/delay.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/io.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <linux/mfd/syscon.h>
  22 #include <linux/regmap.h>
  23 #include <linux/sched.h>
  24 #include <linux/wait.h>
  25
  26 #include "pmc.h"
  27
  28 #define SLOW_CLOCK_FREQ         32768
  29 #define MAINF_DIV               16
  30 #define MAINFRDY_TIMEOUT        (((MAINF_DIV + 1) * USEC_PER_SEC) / \
  31                                  SLOW_CLOCK_FREQ)
  32 #define MAINF_LOOP_MIN_WAIT     (USEC_PER_SEC / SLOW_CLOCK_FREQ)
  33 #define MAINF_LOOP_MAX_WAIT     MAINFRDY_TIMEOUT
  34
  35 #define MOR_KEY_MASK            (0xff << 16)
  36
  37 struct clk_main_osc {
  38         struct clk_hw hw;
  39         struct regmap *regmap;
  40         unsigned int irq;
  41         wait_queue_head_t wait;
  42 };
  43
  44 #define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw)
  45
  46 struct clk_main_rc_osc {
  47         struct clk_hw hw;
  48         struct regmap *regmap;
  49         unsigned int irq;
  50         wait_queue_head_t wait;
  51         unsigned long frequency;
  52         unsigned long accuracy;
  53 };
  54
  55 #define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw)
  56
  57 struct clk_rm9200_main {
  58         struct clk_hw hw;
  59         struct regmap *regmap;
  60 };
  61
  62 #define to_clk_rm9200_main(hw) container_of(hw, struct clk_rm9200_main, hw)
  63
  64 struct clk_sam9x5_main {
  65         struct clk_hw hw;
  66         struct regmap *regmap;
  67         unsigned int irq;
  68         wait_queue_head_t wait;
  69         u8 parent;
  70 };
  71
  72 #define to_clk_sam9x5_main(hw) container_of(hw, struct clk_sam9x5_main, hw)
  73
  74 static irqreturn_t clk_main_osc_irq_handler(int irq, void *dev_id)
  75 {
  76         struct clk_main_osc *osc = dev_id;
  77
  78         wake_up(&osc->wait);
  79         disable_irq_nosync(osc->irq);
  80
  81         return IRQ_HANDLED;
  82 }
  83
  84 static inline bool clk_main_osc_ready(struct regmap *regmap)
  85 {
  86         unsigned int status;
  87
  88         regmap_read(regmap, AT91_PMC_SR, &status);
  89
  90         return status & AT91_PMC_MOSCS;
  91 }
  92
  93 static int clk_main_osc_prepare(struct clk_hw *hw)
  94 {
  95         struct clk_main_osc *osc = to_clk_main_osc(hw);
  96         struct regmap *regmap = osc->regmap;
  97         u32 tmp;
  98
  99         regmap_read(regmap, AT91_CKGR_MOR, &tmp);
 100         tmp &= ~MOR_KEY_MASK;
 101
 102         if (tmp & AT91_PMC_OSCBYPASS)
 103                 return 0;
 104
 105         if (!(tmp & AT91_PMC_MOSCEN)) {
 106                 tmp |= AT91_PMC_MOSCEN | AT91_PMC_KEY;
 107                 regmap_write(regmap, AT91_CKGR_MOR, tmp);
 108         }
 109
 110         while (!clk_main_osc_ready(regmap)) {
 111                 enable_irq(osc->irq);
 112                 wait_event(osc->wait,
 113                            clk_main_osc_ready(regmap));
 114         }
 115
 116         return 0;
 117 }
 118
 119 static void clk_main_osc_unprepare(struct clk_hw *hw)
 120 {
 121         struct clk_main_osc *osc = to_clk_main_osc(hw);
 122         struct regmap *regmap = osc->regmap;
 123         u32 tmp;
 124
 125         regmap_read(regmap, AT91_CKGR_MOR, &tmp);
 126         if (tmp & AT91_PMC_OSCBYPASS)
 127                 return;
 128
 129         if (!(tmp & AT91_PMC_MOSCEN))
 130                 return;
 131
 132         tmp &= ~(AT91_PMC_KEY | AT91_PMC_MOSCEN);
 133         regmap_write(regmap, AT91_CKGR_MOR, tmp | AT91_PMC_KEY);
 134 }
 135
 136 static int clk_main_osc_is_prepared(struct clk_hw *hw)
 137 {
 138         struct clk_main_osc *osc = to_clk_main_osc(hw);
 139         struct regmap *regmap = osc->regmap;
 140         u32 tmp, status;
 141
 142         regmap_read(regmap, AT91_CKGR_MOR, &tmp);
 143         if (tmp & AT91_PMC_OSCBYPASS)
 144                 return 1;
 145
 146         regmap_read(regmap, AT91_PMC_SR, &status);
 147
 148         return (status & AT91_PMC_MOSCS) && (tmp & AT91_PMC_MOSCEN);
 149 }
 150
 151 static const struct clk_ops main_osc_ops = {
 152         .prepare = clk_main_osc_prepare,
 153         .unprepare = clk_main_osc_unprepare,
 154         .is_prepared = clk_main_osc_is_prepared,
 155 };
 156
 157 static struct clk * __init
 158 at91_clk_register_main_osc(struct regmap *regmap,
 159                            unsigned int irq,
 160                            const char *name,
 161                            const char *parent_name,
 162                            bool bypass)
 163 {
 164         int ret;
 165         struct clk_main_osc *osc;
 166         struct clk *clk = NULL;
 167         struct clk_init_data init;
 168
 169         if (!irq || !name || !parent_name)
 170                 return ERR_PTR(-EINVAL);
 171
 172         osc = kzalloc(sizeof(*osc), GFP_KERNEL);
 173         if (!osc)
 174                 return ERR_PTR(-ENOMEM);
 175
 176         init.name = name;
 177         init.ops = &main_osc_ops;
 178         init.parent_names = &parent_name;
 179         init.num_parents = 1;
 180         init.flags = CLK_IGNORE_UNUSED;
 181
 182         osc->hw.init = &init;
 183         osc->regmap = regmap;
 184         osc->irq = irq;
 185
 186         init_waitqueue_head(&osc->wait);
 187         irq_set_status_flags(osc->irq, IRQ_NOAUTOEN);
 188         ret = request_irq(osc->irq, clk_main_osc_irq_handler,
 189                           IRQF_TRIGGER_HIGH, name, osc);
 190         if (ret) {
 191                 kfree(osc);
 192                 return ERR_PTR(ret);
 193         }
 194
 195         if (bypass)
 196                 regmap_update_bits(regmap,
 197                                    AT91_CKGR_MOR, MOR_KEY_MASK |
 198                                    AT91_PMC_MOSCEN,
 199                                    AT91_PMC_OSCBYPASS | AT91_PMC_KEY);
 200
 201         clk = clk_register(NULL, &osc->hw);
 202         if (IS_ERR(clk)) {
 203                 free_irq(irq, osc);
 204                 kfree(osc);
 205         }
 206
 207         return clk;
 208 }
 209
 210 static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)
 211 {
 212         struct clk *clk;
 213         unsigned int irq;
 214         const char *name = np->name;
 215         const char *parent_name;
 216         struct regmap *regmap;
 217         bool bypass;
 218
 219         of_property_read_string(np, "clock-output-names", &name);
 220         bypass = of_property_read_bool(np, "atmel,osc-bypass");
 221         parent_name = of_clk_get_parent_name(np, 0);
 222
 223         regmap = syscon_node_to_regmap(of_get_parent(np));
 224         if (IS_ERR(regmap))
 225                 return;
 226
 227         irq = irq_of_parse_and_map(np, 0);
 228         if (!irq)
 229                 return;
 230
 231         clk = at91_clk_register_main_osc(regmap, irq, name, parent_name, bypass);
 232         if (IS_ERR(clk))
 233                 return;
 234
 235         of_clk_add_provider(np, of_clk_src_simple_get, clk);
 236 }
 237 CLK_OF_DECLARE(at91rm9200_clk_main_osc, "atmel,at91rm9200-clk-main-osc",
 238                of_at91rm9200_clk_main_osc_setup);
 239
 240 static irqreturn_t clk_main_rc_osc_irq_handler(int irq, void *dev_id)
 241 {
 242         struct clk_main_rc_osc *osc = dev_id;
 243
 244         wake_up(&osc->wait);
 245         disable_irq_nosync(osc->irq);
 246
 247         return IRQ_HANDLED;
 248 }
 249
 250 static bool clk_main_rc_osc_ready(struct regmap *regmap)
 251 {
 252         unsigned int status;
 253
 254         regmap_read(regmap, AT91_PMC_SR, &status);
 255
 256         return status & AT91_PMC_MOSCRCS;
 257 }
 258
 259 static int clk_main_rc_osc_prepare(struct clk_hw *hw)
 260 {
 261         struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
 262         struct regmap *regmap = osc->regmap;
 263         unsigned int mor;
 264
 265         regmap_read(regmap, AT91_CKGR_MOR, &mor);
 266
 267         if (!(mor & AT91_PMC_MOSCRCEN))
 268                 regmap_update_bits(regmap, AT91_CKGR_MOR,
 269                                    MOR_KEY_MASK | AT91_PMC_MOSCRCEN,
 270                                    AT91_PMC_MOSCRCEN | AT91_PMC_KEY);
 271
 272         while (!clk_main_rc_osc_ready(regmap)) {
 273                 enable_irq(osc->irq);
 274                 wait_event(osc->wait,
 275                            clk_main_rc_osc_ready(regmap));
 276         }
 277
 278         return 0;
 279 }
 280
 281 static void clk_main_rc_osc_unprepare(struct clk_hw *hw)
 282 {
 283         struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
 284         struct regmap *regmap = osc->regmap;
 285         unsigned int mor;
 286
 287         regmap_read(regmap, AT91_CKGR_MOR, &mor);
 288
 289         if (!(mor & AT91_PMC_MOSCRCEN))
 290                 return;
 291
 292         regmap_update_bits(regmap, AT91_CKGR_MOR,
 293                            MOR_KEY_MASK | AT91_PMC_MOSCRCEN, AT91_PMC_KEY);
 294 }
 295
 296 static int clk_main_rc_osc_is_prepared(struct clk_hw *hw)
 297 {
 298         struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
 299         struct regmap *regmap = osc->regmap;
 300         unsigned int mor, status;
 301
 302         regmap_read(regmap, AT91_CKGR_MOR, &mor);
 303         regmap_read(regmap, AT91_PMC_SR, &status);
 304
 305         return (mor & AT91_PMC_MOSCRCEN) && (status & AT91_PMC_MOSCRCS);
 306 }
 307
 308 static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw,
 309                                                  unsigned long parent_rate)
 310 {
 311         struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
 312
 313         return osc->frequency;
 314 }
 315
 316 static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw,
 317                                                      unsigned long parent_acc)
 318 {
 319         struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
 320
 321         return osc->accuracy;
 322 }
 323
 324 static const struct clk_ops main_rc_osc_ops = {
 325         .prepare = clk_main_rc_osc_prepare,
 326         .unprepare = clk_main_rc_osc_unprepare,
 327         .is_prepared = clk_main_rc_osc_is_prepared,
 328         .recalc_rate = clk_main_rc_osc_recalc_rate,
 329         .recalc_accuracy = clk_main_rc_osc_recalc_accuracy,
 330 };
 331
 332 static struct clk * __init
 333 at91_clk_register_main_rc_osc(struct regmap *regmap,
 334                               unsigned int irq,
 335                               const char *name,
 336                               u32 frequency, u32 accuracy)
 337 {
 338         int ret;
 339         struct clk_main_rc_osc *osc;
 340         struct clk *clk = NULL;
 341         struct clk_init_data init;
 342
 343         if (!name || !frequency)
 344                 return ERR_PTR(-EINVAL);
 345
 346         osc = kzalloc(sizeof(*osc), GFP_KERNEL);
 347         if (!osc)
 348                 return ERR_PTR(-ENOMEM);
 349
 350         init.name = name;
 351         init.ops = &main_rc_osc_ops;
 352         init.parent_names = NULL;
 353         init.num_parents = 0;
 354         init.flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED;
 355
 356         osc->hw.init = &init;
 357         osc->regmap = regmap;
 358         osc->irq = irq;
 359         osc->frequency = frequency;
 360         osc->accuracy = accuracy;
 361
 362         init_waitqueue_head(&osc->wait);
 363         irq_set_status_flags(osc->irq, IRQ_NOAUTOEN);
 364         ret = request_irq(osc->irq, clk_main_rc_osc_irq_handler,
 365                           IRQF_TRIGGER_HIGH, name, osc);
 366         if (ret)
 367                 return ERR_PTR(ret);
 368
 369         clk = clk_register(NULL, &osc->hw);
 370         if (IS_ERR(clk)) {
 371                 free_irq(irq, osc);
 372                 kfree(osc);
 373         }
 374
 375         return clk;
 376 }
 377
 378 static void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np)
 379 {
 380         struct clk *clk;
 381         unsigned int irq;
 382         u32 frequency = 0;
 383         u32 accuracy = 0;
 384         const char *name = np->name;
 385         struct regmap *regmap;
 386
 387         of_property_read_string(np, "clock-output-names", &name);
 388         of_property_read_u32(np, "clock-frequency", &frequency);
 389         of_property_read_u32(np, "clock-accuracy", &accuracy);
 390
 391         irq = irq_of_parse_and_map(np, 0);
 392         if (!irq)
 393                 return;
 394
 395         regmap = syscon_node_to_regmap(of_get_parent(np));
 396         if (IS_ERR(regmap))
 397                 return;
 398
 399         clk = at91_clk_register_main_rc_osc(regmap, irq, name, frequency,
 400                                             accuracy);
 401         if (IS_ERR(clk))
 402                 return;
 403
 404         of_clk_add_provider(np, of_clk_src_simple_get, clk);
 405 }
 406 CLK_OF_DECLARE(at91sam9x5_clk_main_rc_osc, "atmel,at91sam9x5-clk-main-rc-osc",
 407                of_at91sam9x5_clk_main_rc_osc_setup);
 408
 409
 410 static int clk_main_probe_frequency(struct regmap *regmap)
 411 {
 412         unsigned long prep_time, timeout;
 413         unsigned int mcfr;
 414
 415         timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT);
 416         do {
 417                 prep_time = jiffies;
 418                 regmap_read(regmap, AT91_CKGR_MCFR, &mcfr);
 419                 if (mcfr & AT91_PMC_MAINRDY)
 420                         return 0;
 421                 usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
 422         } while (time_before(prep_time, timeout));
 423
 424         return -ETIMEDOUT;
 425 }
 426
 427 static unsigned long clk_main_recalc_rate(struct regmap *regmap,
 428                                           unsigned long parent_rate)
 429 {
 430         unsigned int mcfr;
 431
 432         if (parent_rate)
 433                 return parent_rate;
 434
 435         pr_warn("Main crystal frequency not set, using approximate value\n");
 436         regmap_read(regmap, AT91_CKGR_MCFR, &mcfr);
 437         if (!(mcfr & AT91_PMC_MAINRDY))
 438                 return 0;
 439
 440         return ((mcfr & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV;
 441 }
 442
 443 static int clk_rm9200_main_prepare(struct clk_hw *hw)
 444 {
 445         struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
 446
 447         return clk_main_probe_frequency(clkmain->regmap);
 448 }
 449
 450 static int clk_rm9200_main_is_prepared(struct clk_hw *hw)
 451 {
 452         struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
 453         unsigned int status;
 454
 455         regmap_read(clkmain->regmap, AT91_CKGR_MCFR, &status);
 456
 457         return status & AT91_PMC_MAINRDY ? 1 : 0;
 458 }
 459
 460 static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw,
 461                                                  unsigned long parent_rate)
 462 {
 463         struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
 464
 465         return clk_main_recalc_rate(clkmain->regmap, parent_rate);
 466 }
 467
 468 static const struct clk_ops rm9200_main_ops = {
 469         .prepare = clk_rm9200_main_prepare,
 470         .is_prepared = clk_rm9200_main_is_prepared,
 471         .recalc_rate = clk_rm9200_main_recalc_rate,
 472 };
 473
 474 static struct clk * __init
 475 at91_clk_register_rm9200_main(struct regmap *regmap,
 476                               const char *name,
 477                               const char *parent_name)
 478 {
 479         struct clk_rm9200_main *clkmain;
 480         struct clk *clk = NULL;
 481         struct clk_init_data init;
 482
 483         if (!name)
 484                 return ERR_PTR(-EINVAL);
 485
 486         if (!parent_name)
 487                 return ERR_PTR(-EINVAL);
 488
 489         clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
 490         if (!clkmain)
 491                 return ERR_PTR(-ENOMEM);
 492
 493         init.name = name;
 494         init.ops = &rm9200_main_ops;
 495         init.parent_names = &parent_name;
 496         init.num_parents = 1;
 497         init.flags = 0;
 498
 499         clkmain->hw.init = &init;
 500         clkmain->regmap = regmap;
 501
 502         clk = clk_register(NULL, &clkmain->hw);
 503         if (IS_ERR(clk))
 504                 kfree(clkmain);
 505
 506         return clk;
 507 }
 508
 509 static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
 510 {
 511         struct clk *clk;
 512         const char *parent_name;
 513         const char *name = np->name;
 514         struct regmap *regmap;
 515
 516         parent_name = of_clk_get_parent_name(np, 0);
 517         of_property_read_string(np, "clock-output-names", &name);
 518
 519         regmap = syscon_node_to_regmap(of_get_parent(np));
 520         if (IS_ERR(regmap))
 521                 return;
 522
 523         clk = at91_clk_register_rm9200_main(regmap, name, parent_name);
 524         if (IS_ERR(clk))
 525                 return;
 526
 527         of_clk_add_provider(np, of_clk_src_simple_get, clk);
 528 }
 529 CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
 530                of_at91rm9200_clk_main_setup);
 531
 532 static irqreturn_t clk_sam9x5_main_irq_handler(int irq, void *dev_id)
 533 {
 534         struct clk_sam9x5_main *clkmain = dev_id;
 535
 536         wake_up(&clkmain->wait);
 537         disable_irq_nosync(clkmain->irq);
 538
 539         return IRQ_HANDLED;
 540 }
 541
 542 static inline bool clk_sam9x5_main_ready(struct regmap *regmap)
 543 {
 544         unsigned int status;
 545
 546         regmap_read(regmap, AT91_PMC_SR, &status);
 547
 548         return status & AT91_PMC_MOSCSELS ? 1 : 0;
 549 }
 550
 551 static int clk_sam9x5_main_prepare(struct clk_hw *hw)
 552 {
 553         struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
 554         struct regmap *regmap = clkmain->regmap;
 555
 556         while (!clk_sam9x5_main_ready(regmap)) {
 557                 enable_irq(clkmain->irq);
 558                 wait_event(clkmain->wait,
 559                            clk_sam9x5_main_ready(regmap));
 560         }
 561
 562         return clk_main_probe_frequency(regmap);
 563 }
 564
 565 static int clk_sam9x5_main_is_prepared(struct clk_hw *hw)
 566 {
 567         struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
 568
 569         return clk_sam9x5_main_ready(clkmain->regmap);
 570 }
 571
 572 static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw,
 573                                                  unsigned long parent_rate)
 574 {
 575         struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
 576
 577         return clk_main_recalc_rate(clkmain->regmap, parent_rate);
 578 }
 579
 580 static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index)
 581 {
 582         struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
 583         struct regmap *regmap = clkmain->regmap;
 584         unsigned int tmp;
 585
 586         if (index > 1)
 587                 return -EINVAL;
 588
 589         regmap_read(regmap, AT91_CKGR_MOR, &tmp);
 590         tmp &= ~MOR_KEY_MASK;
 591
 592         if (index && !(tmp & AT91_PMC_MOSCSEL))
 593                 regmap_write(regmap, AT91_CKGR_MOR, tmp | AT91_PMC_MOSCSEL);
 594         else if (!index && (tmp & AT91_PMC_MOSCSEL))
 595                 regmap_write(regmap, AT91_CKGR_MOR, tmp & ~AT91_PMC_MOSCSEL);
 596
 597         while (!clk_sam9x5_main_ready(regmap)) {
 598                 enable_irq(clkmain->irq);
 599                 wait_event(clkmain->wait,
 600                            clk_sam9x5_main_ready(regmap));
 601         }
 602
 603         return 0;
 604 }
 605
 606 static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw)
 607 {
 608         struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
 609         unsigned int status;
 610
 611         regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
 612
 613         return status & AT91_PMC_MOSCEN ? 1 : 0;
 614 }
 615
 616 static const struct clk_ops sam9x5_main_ops = {
 617         .prepare = clk_sam9x5_main_prepare,
 618         .is_prepared = clk_sam9x5_main_is_prepared,
 619         .recalc_rate = clk_sam9x5_main_recalc_rate,
 620         .set_parent = clk_sam9x5_main_set_parent,
 621         .get_parent = clk_sam9x5_main_get_parent,
 622 };
 623
 624 static struct clk * __init
 625 at91_clk_register_sam9x5_main(struct regmap *regmap,
 626                               unsigned int irq,
 627                               const char *name,
 628                               const char **parent_names,
 629                               int num_parents)
 630 {
 631         int ret;
 632         struct clk_sam9x5_main *clkmain;
 633         struct clk *clk = NULL;
 634         struct clk_init_data init;
 635         unsigned int status;
 636
 637         if (!name)
 638                 return ERR_PTR(-EINVAL);
 639
 640         if (!parent_names || !num_parents)
 641                 return ERR_PTR(-EINVAL);
 642
 643         clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
 644         if (!clkmain)
 645                 return ERR_PTR(-ENOMEM);
 646
 647         init.name = name;
 648         init.ops = &sam9x5_main_ops;
 649         init.parent_names = parent_names;
 650         init.num_parents = num_parents;
 651         init.flags = CLK_SET_PARENT_GATE;
 652
 653         clkmain->hw.init = &init;
 654         clkmain->regmap = regmap;
 655         clkmain->irq = irq;
 656         regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
 657         clkmain->parent = status & AT91_PMC_MOSCEN ? 1 : 0;
 658         init_waitqueue_head(&clkmain->wait);
 659         irq_set_status_flags(clkmain->irq, IRQ_NOAUTOEN);
 660         ret = request_irq(clkmain->irq, clk_sam9x5_main_irq_handler,
 661                           IRQF_TRIGGER_HIGH, name, clkmain);
 662         if (ret)
 663                 return ERR_PTR(ret);
 664
 665         clk = clk_register(NULL, &clkmain->hw);
 666         if (IS_ERR(clk)) {
 667                 free_irq(clkmain->irq, clkmain);
 668                 kfree(clkmain);
 669         }
 670
 671         return clk;
 672 }
 673
 674 static void __init of_at91sam9x5_clk_main_setup(struct device_node *np)
 675 {
 676         struct clk *clk;
 677         const char *parent_names[2];
 678         int num_parents;
 679         unsigned int irq;
 680         const char *name = np->name;
 681         struct regmap *regmap;
 682
 683         num_parents = of_clk_get_parent_count(np);
 684         if (num_parents <= 0 || num_parents > 2)
 685                 return;
 686
 687         of_clk_parent_fill(np, parent_names, num_parents);
 688         regmap = syscon_node_to_regmap(of_get_parent(np));
 689         if (IS_ERR(regmap))
 690                 return;
 691
 692         of_property_read_string(np, "clock-output-names", &name);
 693
 694         irq = irq_of_parse_and_map(np, 0);
 695         if (!irq)
 696                 return;
 697
 698         clk = at91_clk_register_sam9x5_main(regmap, irq, name, parent_names,
 699                                             num_parents);
 700         if (IS_ERR(clk))
 701                 return;
 702
 703         of_clk_add_provider(np, of_clk_src_simple_get, clk);
 704 }
 705 CLK_OF_DECLARE(at91sam9x5_clk_main, "atmel,at91sam9x5-clk-main",
 706                of_at91sam9x5_clk_main_setup);