2 * Driver for TI Dual PLL CDCE925 clock synthesizer
4 * This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1
5 * and Y4/Y5 to PLL2. PLL frequency is set on a first-come-first-serve
6 * basis. Clients can directly request any frequency that the chip can
7 * deliver using the standard clk framework. In addition, the device can
8 * be configured and activated via the devicetree.
10 * Copyright (C) 2014, Topic Embedded Products
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/delay.h>
16 #include <linux/module.h>
17 #include <linux/i2c.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20 #include <linux/gcd.h>
22 /* The chip has 2 PLLs which can be routed through dividers to 5 outputs.
23 * Model this as 2 PLL clocks which are parents to the outputs.
25 #define NUMBER_OF_PLLS 2
26 #define NUMBER_OF_OUTPUTS 5
28 #define CDCE925_REG_GLOBAL1 0x01
29 #define CDCE925_REG_Y1SPIPDIVH 0x02
30 #define CDCE925_REG_PDIVL 0x03
31 #define CDCE925_REG_XCSEL 0x05
32 /* PLL parameters start at 0x10, steps of 0x10 */
33 #define CDCE925_OFFSET_PLL 0x10
34 /* Add CDCE925_OFFSET_PLL * (pll) to these registers before sending */
35 #define CDCE925_PLL_MUX_OUTPUTS 0x14
36 #define CDCE925_PLL_MULDIV 0x18
38 #define CDCE925_PLL_FREQUENCY_MIN 80000000ul
39 #define CDCE925_PLL_FREQUENCY_MAX 230000000ul
40 struct clk_cdce925_chip;
42 struct clk_cdce925_output {
44 struct clk_cdce925_chip *chip;
46 u16 pdiv; /* 1..127 for Y2-Y5; 1..1023 for Y1 */
48 #define to_clk_cdce925_output(_hw) \
49 container_of(_hw, struct clk_cdce925_output, hw)
51 struct clk_cdce925_pll {
53 struct clk_cdce925_chip *chip;
58 #define to_clk_cdce925_pll(_hw) container_of(_hw, struct clk_cdce925_pll, hw)
60 struct clk_cdce925_chip {
61 struct regmap *regmap;
62 struct i2c_client *i2c_client;
63 struct clk_cdce925_pll pll[NUMBER_OF_PLLS];
64 struct clk_cdce925_output clk[NUMBER_OF_OUTPUTS];
67 /* ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** */
69 static unsigned long cdce925_pll_calculate_rate(unsigned long parent_rate,
72 if ((!m || !n) || (m == n))
73 return parent_rate; /* In bypass mode runs at same frequency */
74 return mult_frac(parent_rate, (unsigned long)n, (unsigned long)m);
77 static unsigned long cdce925_pll_recalc_rate(struct clk_hw *hw,
78 unsigned long parent_rate)
80 /* Output frequency of PLL is Fout = (Fin/Pdiv)*(N/M) */
81 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
83 return cdce925_pll_calculate_rate(parent_rate, data->n, data->m);
86 static void cdce925_pll_find_rate(unsigned long rate,
87 unsigned long parent_rate, u16 *n, u16 *m)
93 if (rate <= parent_rate) {
94 /* Can always deliver parent_rate in bypass mode */
99 /* In PLL mode, need to apply min/max range */
100 if (rate < CDCE925_PLL_FREQUENCY_MIN)
101 rate = CDCE925_PLL_FREQUENCY_MIN;
102 else if (rate > CDCE925_PLL_FREQUENCY_MAX)
103 rate = CDCE925_PLL_FREQUENCY_MAX;
105 g = gcd(rate, parent_rate);
106 um = parent_rate / g;
108 /* When outside hw range, reduce to fit (rounding errors) */
109 while ((un > 4095) || (um > 511)) {
123 static long cdce925_pll_round_rate(struct clk_hw *hw, unsigned long rate,
124 unsigned long *parent_rate)
128 cdce925_pll_find_rate(rate, *parent_rate, &n, &m);
129 return (long)cdce925_pll_calculate_rate(*parent_rate, n, m);
132 static int cdce925_pll_set_rate(struct clk_hw *hw, unsigned long rate,
133 unsigned long parent_rate)
135 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
137 if (!rate || (rate == parent_rate)) {
138 data->m = 0; /* Bypass mode */
143 if ((rate < CDCE925_PLL_FREQUENCY_MIN) ||
144 (rate > CDCE925_PLL_FREQUENCY_MAX)) {
145 pr_debug("%s: rate %lu outside PLL range.\n", __func__, rate);
149 if (rate < parent_rate) {
150 pr_debug("%s: rate %lu less than parent rate %lu.\n", __func__,
155 cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m);
160 /* calculate p = max(0, 4 - int(log2 (n/m))) */
161 static u8 cdce925_pll_calc_p(u16 n, u16 m)
176 /* Returns VCO range bits for VCO1_0_RANGE */
177 static u8 cdce925_pll_calc_range_bits(struct clk_hw *hw, u16 n, u16 m)
179 struct clk *parent = clk_get_parent(hw->clk);
180 unsigned long rate = clk_get_rate(parent);
182 rate = mult_frac(rate, (unsigned long)n, (unsigned long)m);
183 if (rate >= 175000000)
185 if (rate >= 150000000)
187 if (rate >= 125000000)
192 /* I2C clock, hence everything must happen in (un)prepare because this
194 static int cdce925_pll_prepare(struct clk_hw *hw)
196 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
203 u8 pll[4]; /* Bits are spread out over 4 byte registers */
204 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL;
207 if ((!m || !n) || (m == n)) {
208 /* Set PLL mux to bypass mode, leave the rest as is */
209 regmap_update_bits(data->chip->regmap,
210 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80);
212 /* According to data sheet: */
213 /* p = max(0, 4 - int(log2 (n/m))) */
214 p = cdce925_pll_calc_p(n, m);
219 if ((q < 16) || (q > 63)) {
220 pr_debug("%s invalid q=%d\n", __func__, q);
225 pr_debug("%s invalid r=%d\n", __func__, r);
228 pr_debug("%s n=%d m=%d p=%d q=%d r=%d\n", __func__,
230 /* encode into register bits */
232 pll[1] = ((n & 0x0F) << 4) | ((r >> 5) & 0x0F);
233 pll[2] = ((r & 0x1F) << 3) | ((q >> 3) & 0x07);
234 pll[3] = ((q & 0x07) << 5) | (p << 2) |
235 cdce925_pll_calc_range_bits(hw, n, m);
236 /* Write to registers */
237 for (i = 0; i < ARRAY_SIZE(pll); ++i)
238 regmap_write(data->chip->regmap,
239 reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]);
241 regmap_update_bits(data->chip->regmap,
242 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00);
248 static void cdce925_pll_unprepare(struct clk_hw *hw)
250 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
251 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL;
253 regmap_update_bits(data->chip->regmap,
254 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80);
257 static const struct clk_ops cdce925_pll_ops = {
258 .prepare = cdce925_pll_prepare,
259 .unprepare = cdce925_pll_unprepare,
260 .recalc_rate = cdce925_pll_recalc_rate,
261 .round_rate = cdce925_pll_round_rate,
262 .set_rate = cdce925_pll_set_rate,
266 static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv)
268 switch (data->index) {
270 regmap_update_bits(data->chip->regmap,
271 CDCE925_REG_Y1SPIPDIVH,
272 0x03, (pdiv >> 8) & 0x03);
273 regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF);
276 regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv);
279 regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv);
282 regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv);
285 regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv);
290 static void cdce925_clk_activate(struct clk_cdce925_output *data)
292 switch (data->index) {
294 regmap_update_bits(data->chip->regmap,
295 CDCE925_REG_Y1SPIPDIVH, 0x0c, 0x0c);
299 regmap_update_bits(data->chip->regmap, 0x14, 0x03, 0x03);
303 regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03);
308 static int cdce925_clk_prepare(struct clk_hw *hw)
310 struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
312 cdce925_clk_set_pdiv(data, data->pdiv);
313 cdce925_clk_activate(data);
317 static void cdce925_clk_unprepare(struct clk_hw *hw)
319 struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
321 /* Disable clock by setting divider to "0" */
322 cdce925_clk_set_pdiv(data, 0);
325 static unsigned long cdce925_clk_recalc_rate(struct clk_hw *hw,
326 unsigned long parent_rate)
328 struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
331 return parent_rate / data->pdiv;
335 static u16 cdce925_calc_divider(unsigned long rate,
336 unsigned long parent_rate)
338 unsigned long divider;
342 if (rate >= parent_rate)
345 divider = DIV_ROUND_CLOSEST(parent_rate, rate);
352 static unsigned long cdce925_clk_best_parent_rate(
353 struct clk_hw *hw, unsigned long rate)
355 struct clk *pll = clk_get_parent(hw->clk);
356 struct clk *root = clk_get_parent(pll);
357 unsigned long root_rate = clk_get_rate(root);
358 unsigned long best_rate_error = rate;
364 if (root_rate % rate == 0)
365 return root_rate; /* Don't need the PLL, use bypass */
367 pdiv_min = (u16)max(1ul, DIV_ROUND_UP(CDCE925_PLL_FREQUENCY_MIN, rate));
368 pdiv_max = (u16)min(127ul, CDCE925_PLL_FREQUENCY_MAX / rate);
370 if (pdiv_min > pdiv_max)
371 return 0; /* No can do? */
373 pdiv_best = pdiv_min;
374 for (pdiv_now = pdiv_min; pdiv_now < pdiv_max; ++pdiv_now) {
375 unsigned long target_rate = rate * pdiv_now;
376 long pll_rate = clk_round_rate(pll, target_rate);
377 unsigned long actual_rate;
378 unsigned long rate_error;
382 actual_rate = pll_rate / pdiv_now;
383 rate_error = abs((long)actual_rate - (long)rate);
384 if (rate_error < best_rate_error) {
385 pdiv_best = pdiv_now;
386 best_rate_error = rate_error;
388 /* TODO: Consider PLL frequency based on smaller n/m values
389 * and pick the better one if the error is equal */
392 return rate * pdiv_best;
395 static long cdce925_clk_round_rate(struct clk_hw *hw, unsigned long rate,
396 unsigned long *parent_rate)
398 unsigned long l_parent_rate = *parent_rate;
399 u16 divider = cdce925_calc_divider(rate, l_parent_rate);
401 if (l_parent_rate / divider != rate) {
402 l_parent_rate = cdce925_clk_best_parent_rate(hw, rate);
403 divider = cdce925_calc_divider(rate, l_parent_rate);
404 *parent_rate = l_parent_rate;
408 return (long)(l_parent_rate / divider);
412 static int cdce925_clk_set_rate(struct clk_hw *hw, unsigned long rate,
413 unsigned long parent_rate)
415 struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
417 data->pdiv = cdce925_calc_divider(rate, parent_rate);
422 static const struct clk_ops cdce925_clk_ops = {
423 .prepare = cdce925_clk_prepare,
424 .unprepare = cdce925_clk_unprepare,
425 .recalc_rate = cdce925_clk_recalc_rate,
426 .round_rate = cdce925_clk_round_rate,
427 .set_rate = cdce925_clk_set_rate,
431 static u16 cdce925_y1_calc_divider(unsigned long rate,
432 unsigned long parent_rate)
434 unsigned long divider;
438 if (rate >= parent_rate)
441 divider = DIV_ROUND_CLOSEST(parent_rate, rate);
442 if (divider > 0x3FF) /* Y1 has 10-bit divider */
448 static long cdce925_clk_y1_round_rate(struct clk_hw *hw, unsigned long rate,
449 unsigned long *parent_rate)
451 unsigned long l_parent_rate = *parent_rate;
452 u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate);
455 return (long)(l_parent_rate / divider);
459 static int cdce925_clk_y1_set_rate(struct clk_hw *hw, unsigned long rate,
460 unsigned long parent_rate)
462 struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
464 data->pdiv = cdce925_y1_calc_divider(rate, parent_rate);
469 static const struct clk_ops cdce925_clk_y1_ops = {
470 .prepare = cdce925_clk_prepare,
471 .unprepare = cdce925_clk_unprepare,
472 .recalc_rate = cdce925_clk_recalc_rate,
473 .round_rate = cdce925_clk_y1_round_rate,
474 .set_rate = cdce925_clk_y1_set_rate,
478 static struct regmap_config cdce925_regmap_config = {
479 .name = "configuration0",
482 .cache_type = REGCACHE_RBTREE,
483 .max_register = 0x2F,
486 #define CDCE925_I2C_COMMAND_BLOCK_TRANSFER 0x00
487 #define CDCE925_I2C_COMMAND_BYTE_TRANSFER 0x80
489 static int cdce925_regmap_i2c_write(
490 void *context, const void *data, size_t count)
492 struct device *dev = context;
493 struct i2c_client *i2c = to_i2c_client(dev);
500 /* First byte is command code */
501 reg_data[0] = CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)data)[0];
502 reg_data[1] = ((u8 *)data)[1];
504 dev_dbg(&i2c->dev, "%s(%zu) %#x %#x\n", __func__, count,
505 reg_data[0], reg_data[1]);
507 ret = i2c_master_send(i2c, reg_data, count);
508 if (likely(ret == count))
516 static int cdce925_regmap_i2c_read(void *context,
517 const void *reg, size_t reg_size, void *val, size_t val_size)
519 struct device *dev = context;
520 struct i2c_client *i2c = to_i2c_client(dev);
521 struct i2c_msg xfer[2];
528 xfer[0].addr = i2c->addr;
530 xfer[0].buf = reg_data;
533 CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)reg)[0];
537 CDCE925_I2C_COMMAND_BLOCK_TRANSFER | ((u8 *)reg)[0];
538 reg_data[1] = val_size;
542 xfer[1].addr = i2c->addr;
543 xfer[1].flags = I2C_M_RD;
544 xfer[1].len = val_size;
547 ret = i2c_transfer(i2c->adapter, xfer, 2);
548 if (likely(ret == 2)) {
549 dev_dbg(&i2c->dev, "%s(%zu, %zu) %#x %#x\n", __func__,
550 reg_size, val_size, reg_data[0], *((u8 *)val));
558 static struct clk_hw *
559 of_clk_cdce925_get(struct of_phandle_args *clkspec, void *_data)
561 struct clk_cdce925_chip *data = _data;
562 unsigned int idx = clkspec->args[0];
564 if (idx >= ARRAY_SIZE(data->clk)) {
565 pr_err("%s: invalid index %u\n", __func__, idx);
566 return ERR_PTR(-EINVAL);
569 return &data->clk[idx].hw;
572 /* The CDCE925 uses a funky way to read/write registers. Bulk mode is
573 * just weird, so just use the single byte mode exclusively. */
574 static struct regmap_bus regmap_cdce925_bus = {
575 .write = cdce925_regmap_i2c_write,
576 .read = cdce925_regmap_i2c_read,
579 static int cdce925_probe(struct i2c_client *client,
580 const struct i2c_device_id *id)
582 struct clk_cdce925_chip *data;
583 struct device_node *node = client->dev.of_node;
584 const char *parent_name;
585 const char *pll_clk_name[NUMBER_OF_PLLS] = {NULL,};
586 struct clk_init_data init;
590 struct device_node *np_output;
593 dev_dbg(&client->dev, "%s\n", __func__);
594 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
598 data->i2c_client = client;
599 data->regmap = devm_regmap_init(&client->dev, ®map_cdce925_bus,
600 &client->dev, &cdce925_regmap_config);
601 if (IS_ERR(data->regmap)) {
602 dev_err(&client->dev, "failed to allocate register map\n");
603 return PTR_ERR(data->regmap);
605 i2c_set_clientdata(client, data);
607 parent_name = of_clk_get_parent_name(node, 0);
609 dev_err(&client->dev, "missing parent clock\n");
612 dev_dbg(&client->dev, "parent is: %s\n", parent_name);
614 if (of_property_read_u32(node, "xtal-load-pf", &value) == 0)
615 regmap_write(data->regmap,
616 CDCE925_REG_XCSEL, (value << 3) & 0xF8);
618 regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0);
620 /* Set input source for Y1 to be the XTAL */
621 regmap_update_bits(data->regmap, 0x02, BIT(7), 0);
623 init.ops = &cdce925_pll_ops;
625 init.parent_names = &parent_name;
626 init.num_parents = parent_name ? 1 : 0;
628 /* Register PLL clocks */
629 for (i = 0; i < NUMBER_OF_PLLS; ++i) {
630 pll_clk_name[i] = kasprintf(GFP_KERNEL, "%s.pll%d",
631 client->dev.of_node->name, i);
632 init.name = pll_clk_name[i];
633 data->pll[i].chip = data;
634 data->pll[i].hw.init = &init;
635 data->pll[i].index = i;
636 err = devm_clk_hw_register(&client->dev, &data->pll[i].hw);
638 dev_err(&client->dev, "Failed register PLL %d\n", i);
641 sprintf(child_name, "PLL%d", i+1);
642 np_output = of_get_child_by_name(node, child_name);
645 if (!of_property_read_u32(np_output,
646 "clock-frequency", &value)) {
647 err = clk_set_rate(data->pll[i].hw.clk, value);
649 dev_err(&client->dev,
650 "unable to set PLL frequency %ud\n",
653 if (!of_property_read_u32(np_output,
654 "spread-spectrum", &value)) {
655 u8 flag = of_property_read_bool(np_output,
656 "spread-spectrum-center") ? 0x80 : 0x00;
657 regmap_update_bits(data->regmap,
658 0x16 + (i*CDCE925_OFFSET_PLL),
660 regmap_update_bits(data->regmap,
661 0x12 + (i*CDCE925_OFFSET_PLL),
666 /* Register output clock Y1 */
667 init.ops = &cdce925_clk_y1_ops;
669 init.num_parents = 1;
670 init.parent_names = &parent_name; /* Mux Y1 to input */
671 init.name = kasprintf(GFP_KERNEL, "%s.Y1", client->dev.of_node->name);
672 data->clk[0].chip = data;
673 data->clk[0].hw.init = &init;
674 data->clk[0].index = 0;
675 data->clk[0].pdiv = 1;
676 err = devm_clk_hw_register(&client->dev, &data->clk[0].hw);
677 kfree(init.name); /* clock framework made a copy of the name */
679 dev_err(&client->dev, "clock registration Y1 failed\n");
683 /* Register output clocks Y2 .. Y5*/
684 init.ops = &cdce925_clk_ops;
685 init.flags = CLK_SET_RATE_PARENT;
686 init.num_parents = 1;
687 for (i = 1; i < NUMBER_OF_OUTPUTS; ++i) {
688 init.name = kasprintf(GFP_KERNEL, "%s.Y%d",
689 client->dev.of_node->name, i+1);
690 data->clk[i].chip = data;
691 data->clk[i].hw.init = &init;
692 data->clk[i].index = i;
693 data->clk[i].pdiv = 1;
697 /* Mux Y2/3 to PLL1 */
698 init.parent_names = &pll_clk_name[0];
702 /* Mux Y4/5 to PLL2 */
703 init.parent_names = &pll_clk_name[1];
706 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
707 kfree(init.name); /* clock framework made a copy of the name */
709 dev_err(&client->dev, "clock registration failed\n");
714 /* Register the output clocks */
715 err = of_clk_add_hw_provider(client->dev.of_node, of_clk_cdce925_get,
718 dev_err(&client->dev, "unable to add OF clock provider\n");
723 for (i = 0; i < NUMBER_OF_PLLS; ++i)
724 /* clock framework made a copy of the name */
725 kfree(pll_clk_name[i]);
730 static const struct i2c_device_id cdce925_id[] = {
734 MODULE_DEVICE_TABLE(i2c, cdce925_id);
736 static const struct of_device_id clk_cdce925_of_match[] = {
737 { .compatible = "ti,cdce925" },
740 MODULE_DEVICE_TABLE(of, clk_cdce925_of_match);
742 static struct i2c_driver cdce925_driver = {
745 .of_match_table = of_match_ptr(clk_cdce925_of_match),
747 .probe = cdce925_probe,
748 .id_table = cdce925_id,
750 module_i2c_driver(cdce925_driver);
752 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
753 MODULE_DESCRIPTION("cdce925 driver");
754 MODULE_LICENSE("GPL");