2 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
3 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * Gated clock implementation
12 #include <linux/clk-provider.h>
13 #include <linux/module.h>
14 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/string.h>
20 * DOC: basic gatable clock which can gate and ungate it's ouput
22 * Traits of this clock:
23 * prepare - clk_(un)prepare only ensures parent is (un)prepared
24 * enable - clk_enable and clk_disable are functional & control gating
25 * rate - inherits rate from parent. No clk_set_rate support
26 * parent - fixed parent. No clk_set_parent support
29 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
32 * It works on following logic:
34 * For enabling clock, enable = 1
35 * set2dis = 1 -> clear bit -> set = 0
36 * set2dis = 0 -> set bit -> set = 1
38 * For disabling clock, enable = 0
39 * set2dis = 1 -> set bit -> set = 1
40 * set2dis = 0 -> clear bit -> set = 0
42 * So, result is always: enable xor set2dis.
44 static void clk_gate_endisable(struct clk_hw *hw, int enable)
46 struct clk_gate *gate = to_clk_gate(hw);
47 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
48 unsigned long flags = 0;
54 spin_lock_irqsave(gate->lock, flags);
56 if (gate->flags & CLK_GATE_HIWORD_MASK) {
57 reg = BIT(gate->bit_idx + 16);
59 reg |= BIT(gate->bit_idx);
61 reg = readl(gate->reg);
64 reg |= BIT(gate->bit_idx);
66 reg &= ~BIT(gate->bit_idx);
69 writel(reg, gate->reg);
72 spin_unlock_irqrestore(gate->lock, flags);
75 static int clk_gate_enable(struct clk_hw *hw)
77 clk_gate_endisable(hw, 1);
82 static void clk_gate_disable(struct clk_hw *hw)
84 clk_gate_endisable(hw, 0);
87 static int clk_gate_is_enabled(struct clk_hw *hw)
90 struct clk_gate *gate = to_clk_gate(hw);
92 reg = readl(gate->reg);
94 /* if a set bit disables this clk, flip it before masking */
95 if (gate->flags & CLK_GATE_SET_TO_DISABLE)
96 reg ^= BIT(gate->bit_idx);
98 reg &= BIT(gate->bit_idx);
103 const struct clk_ops clk_gate_ops = {
104 .enable = clk_gate_enable,
105 .disable = clk_gate_disable,
106 .is_enabled = clk_gate_is_enabled,
108 EXPORT_SYMBOL_GPL(clk_gate_ops);
111 * clk_register_gate - register a gate clock with the clock framework
112 * @dev: device that is registering this clock
113 * @name: name of this clock
114 * @parent_name: name of this clock's parent
115 * @flags: framework-specific flags for this clock
116 * @reg: register address to control gating of this clock
117 * @bit_idx: which bit in the register controls gating of this clock
118 * @clk_gate_flags: gate-specific flags for this clock
119 * @lock: shared register lock for this clock
121 struct clk *clk_register_gate(struct device *dev, const char *name,
122 const char *parent_name, unsigned long flags,
123 void __iomem *reg, u8 bit_idx,
124 u8 clk_gate_flags, spinlock_t *lock)
126 struct clk_gate *gate;
128 struct clk_init_data init;
130 if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
132 pr_err("gate bit exceeds LOWORD field\n");
133 return ERR_PTR(-EINVAL);
137 /* allocate the gate */
138 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
140 pr_err("%s: could not allocate gated clk\n", __func__);
141 return ERR_PTR(-ENOMEM);
145 init.ops = &clk_gate_ops;
146 init.flags = flags | CLK_IS_BASIC;
147 init.parent_names = (parent_name ? &parent_name: NULL);
148 init.num_parents = (parent_name ? 1 : 0);
150 /* struct clk_gate assignments */
152 gate->bit_idx = bit_idx;
153 gate->flags = clk_gate_flags;
155 gate->hw.init = &init;
157 clk = clk_register(dev, &gate->hw);
164 EXPORT_SYMBOL_GPL(clk_register_gate);