2 * Nomadik clock implementation
3 * Copyright (C) 2013 ST-Ericsson AB
4 * License terms: GNU General Public License (GPL) version 2
5 * Author: Linus Walleij <linus.walleij@linaro.org>
8 #define pr_fmt(fmt) "Nomadik SRC clocks: " fmt
10 #include <linux/bitops.h>
11 #include <linux/clk.h>
12 #include <linux/clkdev.h>
13 #include <linux/err.h>
15 #include <linux/clk-provider.h>
17 #include <linux/of_address.h>
18 #include <linux/debugfs.h>
19 #include <linux/seq_file.h>
20 #include <linux/spinlock.h>
21 #include <linux/reboot.h>
24 * The Nomadik clock tree is described in the STN8815A12 DB V4.2
25 * reference manual for the chip, page 94 ff.
26 * Clock IDs are in the STn8815 Reference Manual table 3, page 27.
30 #define SRC_CR_T0_ENSEL BIT(15)
31 #define SRC_CR_T1_ENSEL BIT(17)
32 #define SRC_CR_T2_ENSEL BIT(19)
33 #define SRC_CR_T3_ENSEL BIT(21)
34 #define SRC_CR_T4_ENSEL BIT(23)
35 #define SRC_CR_T5_ENSEL BIT(25)
36 #define SRC_CR_T6_ENSEL BIT(27)
37 #define SRC_CR_T7_ENSEL BIT(29)
38 #define SRC_XTALCR 0x0CU
39 #define SRC_XTALCR_XTALTIMEN BIT(20)
40 #define SRC_XTALCR_SXTALDIS BIT(19)
41 #define SRC_XTALCR_MXTALSTAT BIT(2)
42 #define SRC_XTALCR_MXTALEN BIT(1)
43 #define SRC_XTALCR_MXTALOVER BIT(0)
44 #define SRC_PLLCR 0x10U
45 #define SRC_PLLCR_PLLTIMEN BIT(29)
46 #define SRC_PLLCR_PLL2EN BIT(28)
47 #define SRC_PLLCR_PLL1STAT BIT(2)
48 #define SRC_PLLCR_PLL1EN BIT(1)
49 #define SRC_PLLCR_PLL1OVER BIT(0)
50 #define SRC_PLLFR 0x14U
51 #define SRC_PCKEN0 0x24U
52 #define SRC_PCKDIS0 0x28U
53 #define SRC_PCKENSR0 0x2CU
54 #define SRC_PCKSR0 0x30U
55 #define SRC_PCKEN1 0x34U
56 #define SRC_PCKDIS1 0x38U
57 #define SRC_PCKENSR1 0x3CU
58 #define SRC_PCKSR1 0x40U
60 /* Lock protecting the SRC_CR register */
61 static DEFINE_SPINLOCK(src_lock);
62 /* Base address of the SRC */
63 static void __iomem *src_base;
66 * struct clk_pll1 - Nomadik PLL1 clock
67 * @hw: corresponding clock hardware entry
68 * @id: PLL instance: 1 or 2
76 * struct clk_src - Nomadik src clock
77 * @hw: corresponding clock hardware entry
79 * @group1: true if the clock is in group1, else it is in group0
80 * @clkbit: bit 0...31 corresponding to the clock in each clock register
89 #define to_pll(_hw) container_of(_hw, struct clk_pll, hw)
90 #define to_src(_hw) container_of(_hw, struct clk_src, hw)
92 static int pll_clk_enable(struct clk_hw *hw)
94 struct clk_pll *pll = to_pll(hw);
98 val = readl(src_base + SRC_PLLCR);
100 if (val & SRC_PLLCR_PLL1OVER) {
101 val |= SRC_PLLCR_PLL1EN;
102 writel(val, src_base + SRC_PLLCR);
104 } else if (pll->id == 2) {
105 val |= SRC_PLLCR_PLL2EN;
106 writel(val, src_base + SRC_PLLCR);
108 spin_unlock(&src_lock);
112 static void pll_clk_disable(struct clk_hw *hw)
114 struct clk_pll *pll = to_pll(hw);
117 spin_lock(&src_lock);
118 val = readl(src_base + SRC_PLLCR);
120 if (val & SRC_PLLCR_PLL1OVER) {
121 val &= ~SRC_PLLCR_PLL1EN;
122 writel(val, src_base + SRC_PLLCR);
124 } else if (pll->id == 2) {
125 val &= ~SRC_PLLCR_PLL2EN;
126 writel(val, src_base + SRC_PLLCR);
128 spin_unlock(&src_lock);
131 static int pll_clk_is_enabled(struct clk_hw *hw)
133 struct clk_pll *pll = to_pll(hw);
136 val = readl(src_base + SRC_PLLCR);
138 if (val & SRC_PLLCR_PLL1OVER)
139 return !!(val & SRC_PLLCR_PLL1EN);
140 } else if (pll->id == 2) {
141 return !!(val & SRC_PLLCR_PLL2EN);
146 static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
147 unsigned long parent_rate)
149 struct clk_pll *pll = to_pll(hw);
152 val = readl(src_base + SRC_PLLFR);
158 mul = (val >> 8) & 0x3FU;
161 return (parent_rate * mul) >> div;
167 mul = (val >> 24) & 0x3FU;
169 return (parent_rate * mul);
177 static const struct clk_ops pll_clk_ops = {
178 .enable = pll_clk_enable,
179 .disable = pll_clk_disable,
180 .is_enabled = pll_clk_is_enabled,
181 .recalc_rate = pll_clk_recalc_rate,
184 static struct clk * __init
185 pll_clk_register(struct device *dev, const char *name,
186 const char *parent_name, u32 id)
190 struct clk_init_data init;
192 if (id != 1 && id != 2) {
193 pr_err("%s: the Nomadik has only PLL 1 & 2\n", __func__);
194 return ERR_PTR(-EINVAL);
197 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
199 pr_err("%s: could not allocate PLL clk\n", __func__);
200 return ERR_PTR(-ENOMEM);
204 init.ops = &pll_clk_ops;
205 init.parent_names = (parent_name ? &parent_name : NULL);
206 init.num_parents = (parent_name ? 1 : 0);
207 pll->hw.init = &init;
210 pr_debug("register PLL1 clock \"%s\"\n", name);
212 clk = clk_register(dev, &pll->hw);
220 * The Nomadik SRC clocks are gated, but not in the sense that
221 * you read-modify-write a register. Instead there are separate
222 * clock enable and clock disable registers. Writing a '1' bit in
223 * the enable register for a certain clock ungates that clock without
224 * affecting the other clocks. The disable register works the opposite
228 static int src_clk_enable(struct clk_hw *hw)
230 struct clk_src *sclk = to_src(hw);
231 u32 enreg = sclk->group1 ? SRC_PCKEN1 : SRC_PCKEN0;
232 u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
234 writel(sclk->clkbit, src_base + enreg);
235 /* spin until enabled */
236 while (!(readl(src_base + sreg) & sclk->clkbit))
241 static void src_clk_disable(struct clk_hw *hw)
243 struct clk_src *sclk = to_src(hw);
244 u32 disreg = sclk->group1 ? SRC_PCKDIS1 : SRC_PCKDIS0;
245 u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
247 writel(sclk->clkbit, src_base + disreg);
248 /* spin until disabled */
249 while (readl(src_base + sreg) & sclk->clkbit)
253 static int src_clk_is_enabled(struct clk_hw *hw)
255 struct clk_src *sclk = to_src(hw);
256 u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
257 u32 val = readl(src_base + sreg);
259 return !!(val & sclk->clkbit);
263 src_clk_recalc_rate(struct clk_hw *hw,
264 unsigned long parent_rate)
269 static const struct clk_ops src_clk_ops = {
270 .enable = src_clk_enable,
271 .disable = src_clk_disable,
272 .is_enabled = src_clk_is_enabled,
273 .recalc_rate = src_clk_recalc_rate,
276 static struct clk * __init
277 src_clk_register(struct device *dev, const char *name,
278 const char *parent_name, u8 id)
281 struct clk_src *sclk;
282 struct clk_init_data init;
284 sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
286 pr_err("could not allocate SRC clock %s\n",
288 return ERR_PTR(-ENOMEM);
291 init.ops = &src_clk_ops;
292 /* Do not force-disable the static SDRAM controller */
294 init.flags = CLK_IGNORE_UNUSED;
297 init.parent_names = (parent_name ? &parent_name : NULL);
298 init.num_parents = (parent_name ? 1 : 0);
299 sclk->hw.init = &init;
301 sclk->group1 = (id > 31);
302 sclk->clkbit = BIT(id & 0x1f);
304 pr_debug("register clock \"%s\" ID: %d group: %d bits: %08x\n",
305 name, id, sclk->group1, sclk->clkbit);
307 clk = clk_register(dev, &sclk->hw);
314 #ifdef CONFIG_DEBUG_FS
316 static u32 src_pcksr0_boot;
317 static u32 src_pcksr1_boot;
319 static const char * const src_clk_names[] = {
386 static int nomadik_src_clk_show(struct seq_file *s, void *what)
389 u32 src_pcksr0 = readl(src_base + SRC_PCKSR0);
390 u32 src_pcksr1 = readl(src_base + SRC_PCKSR1);
391 u32 src_pckensr0 = readl(src_base + SRC_PCKENSR0);
392 u32 src_pckensr1 = readl(src_base + SRC_PCKENSR1);
394 seq_printf(s, "Clock: Boot: Now: Request: ASKED:\n");
395 for (i = 0; i < ARRAY_SIZE(src_clk_names); i++) {
396 u32 pcksrb = (i < 0x20) ? src_pcksr0_boot : src_pcksr1_boot;
397 u32 pcksr = (i < 0x20) ? src_pcksr0 : src_pcksr1;
398 u32 pckreq = (i < 0x20) ? src_pckensr0 : src_pckensr1;
399 u32 mask = BIT(i & 0x1f);
401 seq_printf(s, "%s %s %s %s\n",
403 (pcksrb & mask) ? "on " : "off",
404 (pcksr & mask) ? "on " : "off",
405 (pckreq & mask) ? "on " : "off");
410 static int nomadik_src_clk_open(struct inode *inode, struct file *file)
412 return single_open(file, nomadik_src_clk_show, NULL);
415 static const struct file_operations nomadik_src_clk_debugfs_ops = {
416 .open = nomadik_src_clk_open,
419 .release = single_release,
422 static int __init nomadik_src_clk_init_debugfs(void)
424 src_pcksr0_boot = readl(src_base + SRC_PCKSR0);
425 src_pcksr1_boot = readl(src_base + SRC_PCKSR1);
426 debugfs_create_file("nomadik-src-clk", S_IFREG | S_IRUGO,
427 NULL, NULL, &nomadik_src_clk_debugfs_ops);
431 module_init(nomadik_src_clk_init_debugfs);
435 static void __init of_nomadik_pll_setup(struct device_node *np)
437 struct clk *clk = ERR_PTR(-EINVAL);
438 const char *clk_name = np->name;
439 const char *parent_name;
442 if (of_property_read_u32(np, "pll-id", &pll_id)) {
443 pr_err("%s: PLL \"%s\" missing pll-id property\n",
447 parent_name = of_clk_get_parent_name(np, 0);
448 clk = pll_clk_register(NULL, clk_name, parent_name, pll_id);
450 of_clk_add_provider(np, of_clk_src_simple_get, clk);
453 static void __init of_nomadik_hclk_setup(struct device_node *np)
455 struct clk *clk = ERR_PTR(-EINVAL);
456 const char *clk_name = np->name;
457 const char *parent_name;
459 parent_name = of_clk_get_parent_name(np, 0);
461 * The HCLK divides PLL1 with 1 (passthru), 2, 3 or 4.
463 clk = clk_register_divider(NULL, clk_name, parent_name,
464 0, src_base + SRC_CR,
466 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
469 of_clk_add_provider(np, of_clk_src_simple_get, clk);
472 static void __init of_nomadik_src_clk_setup(struct device_node *np)
474 struct clk *clk = ERR_PTR(-EINVAL);
475 const char *clk_name = np->name;
476 const char *parent_name;
479 if (of_property_read_u32(np, "clock-id", &clk_id)) {
480 pr_err("%s: SRC clock \"%s\" missing clock-id property\n",
484 parent_name = of_clk_get_parent_name(np, 0);
485 clk = src_clk_register(NULL, clk_name, parent_name, clk_id);
487 of_clk_add_provider(np, of_clk_src_simple_get, clk);
490 static const struct of_device_id nomadik_src_match[] __initconst = {
491 { .compatible = "stericsson,nomadik-src" },
495 static const struct of_device_id nomadik_src_clk_match[] __initconst = {
497 .compatible = "fixed-clock",
498 .data = of_fixed_clk_setup,
501 .compatible = "fixed-factor-clock",
502 .data = of_fixed_factor_clk_setup,
505 .compatible = "st,nomadik-pll-clock",
506 .data = of_nomadik_pll_setup,
509 .compatible = "st,nomadik-hclk-clock",
510 .data = of_nomadik_hclk_setup,
513 .compatible = "st,nomadik-src-clock",
514 .data = of_nomadik_src_clk_setup,
519 static int nomadik_clk_reboot_handler(struct notifier_block *this,
525 /* The main chrystal need to be enabled for reboot to work */
526 val = readl(src_base + SRC_XTALCR);
527 val &= ~SRC_XTALCR_MXTALOVER;
528 val |= SRC_XTALCR_MXTALEN;
529 pr_crit("force-enabling MXTALO\n");
530 writel(val, src_base + SRC_XTALCR);
534 static struct notifier_block nomadik_clk_reboot_notifier = {
535 .notifier_call = nomadik_clk_reboot_handler,
538 void __init nomadik_clk_init(void)
540 struct device_node *np;
543 np = of_find_matching_node(NULL, nomadik_src_match);
545 pr_crit("no matching node for SRC, aborting clock init\n");
548 src_base = of_iomap(np, 0);
550 pr_err("%s: must have src parent node with REGS (%s)\n",
555 /* Set all timers to use the 2.4 MHz TIMCLK */
556 val = readl(src_base + SRC_CR);
557 val |= SRC_CR_T0_ENSEL;
558 val |= SRC_CR_T1_ENSEL;
559 val |= SRC_CR_T2_ENSEL;
560 val |= SRC_CR_T3_ENSEL;
561 val |= SRC_CR_T4_ENSEL;
562 val |= SRC_CR_T5_ENSEL;
563 val |= SRC_CR_T6_ENSEL;
564 val |= SRC_CR_T7_ENSEL;
565 writel(val, src_base + SRC_CR);
567 val = readl(src_base + SRC_XTALCR);
568 pr_info("SXTALO is %s\n",
569 (val & SRC_XTALCR_SXTALDIS) ? "disabled" : "enabled");
570 pr_info("MXTAL is %s\n",
571 (val & SRC_XTALCR_MXTALSTAT) ? "enabled" : "disabled");
572 if (of_property_read_bool(np, "disable-sxtalo")) {
573 /* The machine uses an external oscillator circuit */
574 val |= SRC_XTALCR_SXTALDIS;
575 pr_info("disabling SXTALO\n");
577 if (of_property_read_bool(np, "disable-mxtalo")) {
578 /* Disable this too: also run by external oscillator */
579 val |= SRC_XTALCR_MXTALOVER;
580 val &= ~SRC_XTALCR_MXTALEN;
581 pr_info("disabling MXTALO\n");
583 writel(val, src_base + SRC_XTALCR);
584 register_reboot_notifier(&nomadik_clk_reboot_notifier);
586 of_clk_init(nomadik_src_clk_match);