2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * clock driver for Freescale QorIQ SoCs.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/fsl/guts.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/of_address.h>
20 #include <linux/of_platform.h>
22 #include <linux/slab.h>
29 #define PLATFORM_PLL 0
33 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
37 struct clockgen_pll_div {
43 struct clockgen_pll_div div[4];
46 #define CLKSEL_VALID 1
47 #define CLKSEL_80PCT 2 /* Only allowed if PLL <= 80% of max cpu freq */
49 struct clockgen_sourceinfo {
50 u32 flags; /* CLKSEL_xxx */
51 int pll; /* CGx_PLLn */
52 int div; /* PLL_DIVn */
55 #define NUM_MUX_PARENTS 16
57 struct clockgen_muxinfo {
58 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS];
67 * cmux freq must be >= platform pll.
68 * If not set, cmux freq must be >= platform pll/2
70 #define CG_CMUX_GE_PLAT 1
72 #define CG_PLL_8BIT 2 /* PLLCnGSR[CFG] is 8 bits, not 6 */
73 #define CG_VER3 4 /* version 3 cg: reg layout different */
74 #define CG_LITTLE_ENDIAN 8
76 struct clockgen_chipinfo {
77 const char *compat, *guts_compat;
78 const struct clockgen_muxinfo *cmux_groups[2];
79 const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
80 void (*init_periph)(struct clockgen *cg);
81 int cmux_to_group[NUM_CMUX]; /* -1 terminates if fewer than NUM_CMUX */
82 u32 pll_mask; /* 1 << n bit set if PLL n is valid */
83 u32 flags; /* CG_xxx */
87 struct device_node *node;
89 struct clockgen_chipinfo info; /* mutable copy */
91 struct clockgen_pll pll[6];
92 struct clk *cmux[NUM_CMUX];
93 struct clk *hwaccel[NUM_HWACCEL];
95 struct ccsr_guts __iomem *guts;
98 static struct clockgen clockgen;
100 static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg)
102 if (cg->info.flags & CG_LITTLE_ENDIAN)
105 iowrite32be(val, reg);
108 static u32 cg_in(struct clockgen *cg, u32 __iomem *reg)
112 if (cg->info.flags & CG_LITTLE_ENDIAN)
115 val = ioread32be(reg);
120 static const struct clockgen_muxinfo p2041_cmux_grp1 = {
122 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
123 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
124 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
128 static const struct clockgen_muxinfo p2041_cmux_grp2 = {
130 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
131 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
132 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
136 static const struct clockgen_muxinfo p5020_cmux_grp1 = {
138 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
139 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
140 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
144 static const struct clockgen_muxinfo p5020_cmux_grp2 = {
146 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
147 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
148 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
152 static const struct clockgen_muxinfo p5040_cmux_grp1 = {
154 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
155 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
156 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
157 [5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
161 static const struct clockgen_muxinfo p5040_cmux_grp2 = {
163 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
164 [1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 },
165 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
166 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
170 static const struct clockgen_muxinfo p4080_cmux_grp1 = {
172 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
173 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
174 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
175 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
176 [8] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL3, PLL_DIV1 },
180 static const struct clockgen_muxinfo p4080_cmux_grp2 = {
182 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
183 [8] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
184 [9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
185 [12] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV1 },
186 [13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 },
190 static const struct clockgen_muxinfo t1023_cmux = {
192 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
193 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
197 static const struct clockgen_muxinfo t1040_cmux = {
199 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
200 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
201 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
202 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
207 static const struct clockgen_muxinfo clockgen2_cmux_cga = {
209 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
210 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
211 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
213 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
214 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
215 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
217 { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
218 { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
219 { CLKSEL_VALID, CGA_PLL3, PLL_DIV4 },
223 static const struct clockgen_muxinfo clockgen2_cmux_cga12 = {
225 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
226 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
227 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
229 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
230 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
231 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
235 static const struct clockgen_muxinfo clockgen2_cmux_cgb = {
237 { CLKSEL_VALID, CGB_PLL1, PLL_DIV1 },
238 { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
239 { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
241 { CLKSEL_VALID, CGB_PLL2, PLL_DIV1 },
242 { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
243 { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
247 static const struct clockgen_muxinfo ls1043a_hwa1 = {
251 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
252 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
255 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
256 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
260 static const struct clockgen_muxinfo ls1043a_hwa2 = {
263 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
265 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
269 static const struct clockgen_muxinfo ls1046a_hwa1 = {
273 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
274 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
275 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
276 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
277 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
278 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
282 static const struct clockgen_muxinfo ls1046a_hwa2 = {
285 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
286 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
287 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
290 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
294 static const struct clockgen_muxinfo ls1012a_cmux = {
296 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
298 [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
302 static const struct clockgen_muxinfo t1023_hwa1 = {
305 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
306 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
307 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
311 static const struct clockgen_muxinfo t1023_hwa2 = {
313 [6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
317 static const struct clockgen_muxinfo t2080_hwa1 = {
320 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
321 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
322 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
323 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
324 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
325 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
326 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
330 static const struct clockgen_muxinfo t2080_hwa2 = {
333 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
334 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
335 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
336 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
337 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
338 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
339 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
343 static const struct clockgen_muxinfo t4240_hwa1 = {
345 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
346 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
347 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
348 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
349 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
351 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
352 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
356 static const struct clockgen_muxinfo t4240_hwa4 = {
358 [2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
359 [3] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
360 [4] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
361 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
362 [6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
366 static const struct clockgen_muxinfo t4240_hwa5 = {
368 [2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
369 [3] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV3 },
370 [4] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
371 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
372 [6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
373 [7] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
377 #define RCWSR7_FM1_CLK_SEL 0x40000000
378 #define RCWSR7_FM2_CLK_SEL 0x20000000
379 #define RCWSR7_HWA_ASYNC_DIV 0x04000000
381 static void __init p2041_init_periph(struct clockgen *cg)
385 reg = ioread32be(&cg->guts->rcwsr[7]);
387 if (reg & RCWSR7_FM1_CLK_SEL)
388 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;
390 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
393 static void __init p4080_init_periph(struct clockgen *cg)
397 reg = ioread32be(&cg->guts->rcwsr[7]);
399 if (reg & RCWSR7_FM1_CLK_SEL)
400 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
402 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
404 if (reg & RCWSR7_FM2_CLK_SEL)
405 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
407 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
410 static void __init p5020_init_periph(struct clockgen *cg)
415 reg = ioread32be(&cg->guts->rcwsr[7]);
416 if (reg & RCWSR7_HWA_ASYNC_DIV)
419 if (reg & RCWSR7_FM1_CLK_SEL)
420 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk;
422 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
425 static void __init p5040_init_periph(struct clockgen *cg)
430 reg = ioread32be(&cg->guts->rcwsr[7]);
431 if (reg & RCWSR7_HWA_ASYNC_DIV)
434 if (reg & RCWSR7_FM1_CLK_SEL)
435 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk;
437 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
439 if (reg & RCWSR7_FM2_CLK_SEL)
440 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk;
442 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
445 static void __init t1023_init_periph(struct clockgen *cg)
447 cg->fman[0] = cg->hwaccel[1];
450 static void __init t1040_init_periph(struct clockgen *cg)
452 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;
455 static void __init t2080_init_periph(struct clockgen *cg)
457 cg->fman[0] = cg->hwaccel[0];
460 static void __init t4240_init_periph(struct clockgen *cg)
462 cg->fman[0] = cg->hwaccel[3];
463 cg->fman[1] = cg->hwaccel[4];
466 static const struct clockgen_chipinfo chipinfo[] = {
468 .compat = "fsl,b4420-clockgen",
469 .guts_compat = "fsl,b4860-device-config",
470 .init_periph = t2080_init_periph,
472 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
481 .flags = CG_PLL_8BIT,
484 .compat = "fsl,b4860-clockgen",
485 .guts_compat = "fsl,b4860-device-config",
486 .init_periph = t2080_init_periph,
488 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
497 .flags = CG_PLL_8BIT,
500 .compat = "fsl,ls1021a-clockgen",
510 .compat = "fsl,ls1043a-clockgen",
511 .init_periph = t2080_init_periph,
516 &ls1043a_hwa1, &ls1043a_hwa2
522 .flags = CG_PLL_8BIT,
525 .compat = "fsl,ls1046a-clockgen",
526 .init_periph = t2080_init_periph,
531 &ls1046a_hwa1, &ls1046a_hwa2
537 .flags = CG_PLL_8BIT,
540 .compat = "fsl,ls1012a-clockgen",
550 .compat = "fsl,ls2080a-clockgen",
552 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
558 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
561 .compat = "fsl,p2041-clockgen",
562 .guts_compat = "fsl,qoriq-device-config-1.0",
563 .init_periph = p2041_init_periph,
565 &p2041_cmux_grp1, &p2041_cmux_grp2
573 .compat = "fsl,p3041-clockgen",
574 .guts_compat = "fsl,qoriq-device-config-1.0",
575 .init_periph = p2041_init_periph,
577 &p2041_cmux_grp1, &p2041_cmux_grp2
585 .compat = "fsl,p4080-clockgen",
586 .guts_compat = "fsl,qoriq-device-config-1.0",
587 .init_periph = p4080_init_periph,
589 &p4080_cmux_grp1, &p4080_cmux_grp2
592 0, 0, 0, 0, 1, 1, 1, 1
597 .compat = "fsl,p5020-clockgen",
598 .guts_compat = "fsl,qoriq-device-config-1.0",
599 .init_periph = p5020_init_periph,
601 &p2041_cmux_grp1, &p2041_cmux_grp2
609 .compat = "fsl,p5040-clockgen",
610 .guts_compat = "fsl,p5040-device-config",
611 .init_periph = p5040_init_periph,
613 &p5040_cmux_grp1, &p5040_cmux_grp2
621 .compat = "fsl,t1023-clockgen",
622 .guts_compat = "fsl,t1023-device-config",
623 .init_periph = t1023_init_periph,
628 &t1023_hwa1, &t1023_hwa2
634 .flags = CG_PLL_8BIT,
637 .compat = "fsl,t1040-clockgen",
638 .guts_compat = "fsl,t1040-device-config",
639 .init_periph = t1040_init_periph,
647 .flags = CG_PLL_8BIT,
650 .compat = "fsl,t2080-clockgen",
651 .guts_compat = "fsl,t2080-device-config",
652 .init_periph = t2080_init_periph,
654 &clockgen2_cmux_cga12
657 &t2080_hwa1, &t2080_hwa2
663 .flags = CG_PLL_8BIT,
666 .compat = "fsl,t4240-clockgen",
667 .guts_compat = "fsl,t4240-device-config",
668 .init_periph = t4240_init_periph,
670 &clockgen2_cmux_cga, &clockgen2_cmux_cgb
673 &t4240_hwa1, NULL, NULL, &t4240_hwa4, &t4240_hwa5
679 .flags = CG_PLL_8BIT,
687 const struct clockgen_muxinfo *info;
689 u8 parent_to_clksel[NUM_MUX_PARENTS];
690 s8 clksel_to_parent[NUM_MUX_PARENTS];
694 #define to_mux_hwclock(p) container_of(p, struct mux_hwclock, hw)
695 #define CLKSEL_MASK 0x78000000
696 #define CLKSEL_SHIFT 27
698 static int mux_set_parent(struct clk_hw *hw, u8 idx)
700 struct mux_hwclock *hwc = to_mux_hwclock(hw);
703 if (idx >= hwc->num_parents)
706 clksel = hwc->parent_to_clksel[idx];
707 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg);
712 static u8 mux_get_parent(struct clk_hw *hw)
714 struct mux_hwclock *hwc = to_mux_hwclock(hw);
718 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
720 ret = hwc->clksel_to_parent[clksel];
722 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg);
729 static const struct clk_ops cmux_ops = {
730 .get_parent = mux_get_parent,
731 .set_parent = mux_set_parent,
735 * Don't allow setting for now, as the clock options haven't been
736 * sanitized for additional restrictions.
738 static const struct clk_ops hwaccel_ops = {
739 .get_parent = mux_get_parent,
742 static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg,
743 struct mux_hwclock *hwc,
748 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID))
751 pll = hwc->info->clksel[idx].pll;
752 div = hwc->info->clksel[idx].div;
754 return &cg->pll[pll].div[div];
757 static struct clk * __init create_mux_common(struct clockgen *cg,
758 struct mux_hwclock *hwc,
759 const struct clk_ops *ops,
760 unsigned long min_rate,
761 unsigned long max_rate,
762 unsigned long pct80_rate,
763 const char *fmt, int idx)
765 struct clk_init_data init = {};
767 const struct clockgen_pll_div *div;
768 const char *parent_names[NUM_MUX_PARENTS];
772 snprintf(name, sizeof(name), fmt, idx);
774 for (i = 0, j = 0; i < NUM_MUX_PARENTS; i++) {
777 hwc->clksel_to_parent[i] = -1;
779 div = get_pll_div(cg, hwc, i);
783 rate = clk_get_rate(div->clk);
785 if (hwc->info->clksel[i].flags & CLKSEL_80PCT &&
793 parent_names[j] = div->name;
794 hwc->parent_to_clksel[j] = i;
795 hwc->clksel_to_parent[i] = j;
801 init.parent_names = parent_names;
802 init.num_parents = hwc->num_parents = j;
804 hwc->hw.init = &init;
807 clk = clk_register(NULL, &hwc->hw);
809 pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
818 static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
820 struct mux_hwclock *hwc;
821 const struct clockgen_pll_div *div;
822 unsigned long plat_rate, min_rate;
823 u64 max_rate, pct80_rate;
826 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
830 if (cg->info.flags & CG_VER3)
831 hwc->reg = cg->regs + 0x70000 + 0x20 * idx;
833 hwc->reg = cg->regs + 0x20 * idx;
835 hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]];
838 * Find the rate for the default clksel, and treat it as the
839 * maximum rated core frequency. If this is an incorrect
840 * assumption, certain clock options (possibly including the
841 * default clksel) may be inappropriately excluded on certain
844 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
845 div = get_pll_div(cg, hwc, clksel);
851 max_rate = clk_get_rate(div->clk);
852 pct80_rate = max_rate * 8;
853 do_div(pct80_rate, 10);
855 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
857 if (cg->info.flags & CG_CMUX_GE_PLAT)
858 min_rate = plat_rate;
860 min_rate = plat_rate / 2;
862 return create_mux_common(cg, hwc, &cmux_ops, min_rate, max_rate,
863 pct80_rate, "cg-cmux%d", idx);
866 static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx)
868 struct mux_hwclock *hwc;
870 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
874 hwc->reg = cg->regs + 0x20 * idx + 0x10;
875 hwc->info = cg->info.hwaccel[idx];
877 return create_mux_common(cg, hwc, &hwaccel_ops, 0, ULONG_MAX, 0,
878 "cg-hwaccel%d", idx);
881 static void __init create_muxes(struct clockgen *cg)
885 for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) {
886 if (cg->info.cmux_to_group[i] < 0)
888 if (cg->info.cmux_to_group[i] >=
889 ARRAY_SIZE(cg->info.cmux_groups)) {
894 cg->cmux[i] = create_one_cmux(cg, i);
897 for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) {
898 if (!cg->info.hwaccel[i])
901 cg->hwaccel[i] = create_one_hwaccel(cg, i);
905 static void __init clockgen_init(struct device_node *np);
907 /* Legacy nodes may get probed before the parent clockgen node */
908 static void __init legacy_init_clockgen(struct device_node *np)
911 clockgen_init(of_get_parent(np));
915 static void __init core_mux_init(struct device_node *np)
921 legacy_init_clockgen(np);
923 if (of_address_to_resource(np, 0, &res))
926 idx = (res.start & 0xf0) >> 5;
927 clk = clockgen.cmux[idx];
929 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
931 pr_err("%s: Couldn't register clk provider for node %s: %d\n",
932 __func__, np->name, rc);
937 static struct clk __init
938 *sysclk_from_fixed(struct device_node *node, const char *name)
942 if (of_property_read_u32(node, "clock-frequency", &rate))
943 return ERR_PTR(-ENODEV);
945 return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
948 static struct clk *sysclk_from_parent(const char *name)
951 const char *parent_name;
953 clk = of_clk_get(clockgen.node, 0);
957 /* Register the input clock under the desired name. */
958 parent_name = __clk_get_name(clk);
959 clk = clk_register_fixed_factor(NULL, name, parent_name,
962 pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
968 static struct clk * __init create_sysclk(const char *name)
970 struct device_node *sysclk;
973 clk = sysclk_from_fixed(clockgen.node, name);
977 clk = sysclk_from_parent(name);
981 sysclk = of_get_child_by_name(clockgen.node, "sysclk");
983 clk = sysclk_from_fixed(sysclk, name);
988 pr_err("%s: No input clock\n", __func__);
993 static void __init sysclk_init(struct device_node *node)
997 legacy_init_clockgen(node);
999 clk = clockgen.sysclk;
1001 of_clk_add_provider(node, of_clk_src_simple_get, clk);
1004 #define PLL_KILL BIT(31)
1006 static void __init create_one_pll(struct clockgen *cg, int idx)
1010 struct clockgen_pll *pll = &cg->pll[idx];
1013 if (!(cg->info.pll_mask & (1 << idx)))
1016 if (cg->info.flags & CG_VER3) {
1019 reg = cg->regs + 0x60080;
1022 reg = cg->regs + 0x80;
1025 reg = cg->regs + 0xa0;
1028 reg = cg->regs + 0x10080;
1031 reg = cg->regs + 0x100a0;
1034 WARN_ONCE(1, "index %d\n", idx);
1038 if (idx == PLATFORM_PLL)
1039 reg = cg->regs + 0xc00;
1041 reg = cg->regs + 0x800 + 0x20 * (idx - 1);
1044 /* Get the multiple of PLL */
1045 mult = cg_in(cg, reg);
1047 /* Check if this PLL is disabled */
1048 if (mult & PLL_KILL) {
1049 pr_debug("%s(): pll %p disabled\n", __func__, reg);
1053 if ((cg->info.flags & CG_VER3) ||
1054 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL))
1055 mult = (mult & GENMASK(8, 1)) >> 1;
1057 mult = (mult & GENMASK(6, 1)) >> 1;
1059 for (i = 0; i < ARRAY_SIZE(pll->div); i++) {
1062 snprintf(pll->div[i].name, sizeof(pll->div[i].name),
1063 "cg-pll%d-div%d", idx, i + 1);
1065 clk = clk_register_fixed_factor(NULL,
1066 pll->div[i].name, "cg-sysclk", 0, mult, i + 1);
1068 pr_err("%s: %s: register failed %ld\n",
1069 __func__, pll->div[i].name, PTR_ERR(clk));
1073 pll->div[i].clk = clk;
1077 static void __init create_plls(struct clockgen *cg)
1081 for (i = 0; i < ARRAY_SIZE(cg->pll); i++)
1082 create_one_pll(cg, i);
1085 static void __init legacy_pll_init(struct device_node *np, int idx)
1087 struct clockgen_pll *pll;
1088 struct clk_onecell_data *onecell_data;
1089 struct clk **subclks;
1092 legacy_init_clockgen(np);
1094 pll = &clockgen.pll[idx];
1095 count = of_property_count_strings(np, "clock-output-names");
1097 BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4);
1098 subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL);
1102 onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL);
1107 subclks[0] = pll->div[0].clk;
1108 subclks[1] = pll->div[1].clk;
1109 subclks[2] = pll->div[3].clk;
1111 subclks[0] = pll->div[0].clk;
1112 subclks[1] = pll->div[1].clk;
1113 subclks[2] = pll->div[2].clk;
1114 subclks[3] = pll->div[3].clk;
1117 onecell_data->clks = subclks;
1118 onecell_data->clk_num = count;
1120 rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
1122 pr_err("%s: Couldn't register clk provider for node %s: %d\n",
1123 __func__, np->name, rc);
1129 kfree(onecell_data);
1135 static void __init pltfrm_pll_init(struct device_node *np)
1137 legacy_pll_init(np, PLATFORM_PLL);
1141 static void __init core_pll_init(struct device_node *np)
1143 struct resource res;
1146 if (of_address_to_resource(np, 0, &res))
1149 if ((res.start & 0xfff) == 0xc00) {
1151 * ls1021a devtree labels the platform PLL
1152 * with the core PLL compatible
1154 pltfrm_pll_init(np);
1156 idx = (res.start & 0xf0) >> 5;
1157 legacy_pll_init(np, CGA_PLL1 + idx);
1161 static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data)
1163 struct clockgen *cg = data;
1165 struct clockgen_pll *pll;
1168 if (clkspec->args_count < 2) {
1169 pr_err("%s: insufficient phandle args\n", __func__);
1170 return ERR_PTR(-EINVAL);
1173 type = clkspec->args[0];
1174 idx = clkspec->args[1];
1183 if (idx >= ARRAY_SIZE(cg->cmux))
1185 clk = cg->cmux[idx];
1188 if (idx >= ARRAY_SIZE(cg->hwaccel))
1190 clk = cg->hwaccel[idx];
1193 if (idx >= ARRAY_SIZE(cg->fman))
1195 clk = cg->fman[idx];
1198 pll = &cg->pll[PLATFORM_PLL];
1199 if (idx >= ARRAY_SIZE(pll->div))
1201 clk = pll->div[idx].clk;
1208 return ERR_PTR(-ENOENT);
1212 pr_err("%s: Bad phandle args %u %u\n", __func__, type, idx);
1213 return ERR_PTR(-EINVAL);
1217 #include <asm/mpc85xx.h>
1219 static const u32 a4510_svrs[] __initconst = {
1220 (SVR_P2040 << 8) | 0x10, /* P2040 1.0 */
1221 (SVR_P2040 << 8) | 0x11, /* P2040 1.1 */
1222 (SVR_P2041 << 8) | 0x10, /* P2041 1.0 */
1223 (SVR_P2041 << 8) | 0x11, /* P2041 1.1 */
1224 (SVR_P3041 << 8) | 0x10, /* P3041 1.0 */
1225 (SVR_P3041 << 8) | 0x11, /* P3041 1.1 */
1226 (SVR_P4040 << 8) | 0x20, /* P4040 2.0 */
1227 (SVR_P4080 << 8) | 0x20, /* P4080 2.0 */
1228 (SVR_P5010 << 8) | 0x10, /* P5010 1.0 */
1229 (SVR_P5010 << 8) | 0x20, /* P5010 2.0 */
1230 (SVR_P5020 << 8) | 0x10, /* P5020 1.0 */
1231 (SVR_P5021 << 8) | 0x10, /* P5021 1.0 */
1232 (SVR_P5040 << 8) | 0x10, /* P5040 1.0 */
1235 #define SVR_SECURITY 0x80000 /* The Security (E) bit */
1237 static bool __init has_erratum_a4510(void)
1239 u32 svr = mfspr(SPRN_SVR);
1242 svr &= ~SVR_SECURITY;
1244 for (i = 0; i < ARRAY_SIZE(a4510_svrs); i++) {
1245 if (svr == a4510_svrs[i])
1252 static bool __init has_erratum_a4510(void)
1258 static void __init clockgen_init(struct device_node *np)
1261 bool is_old_ls1021a = false;
1263 /* May have already been called by a legacy probe */
1268 clockgen.regs = of_iomap(np, 0);
1269 if (!clockgen.regs &&
1270 of_device_is_compatible(of_root, "fsl,ls1021a")) {
1271 /* Compatibility hack for old, broken device trees */
1272 clockgen.regs = ioremap(0x1ee1000, 0x1000);
1273 is_old_ls1021a = true;
1275 if (!clockgen.regs) {
1276 pr_err("%s(): %s: of_iomap() failed\n", __func__, np->name);
1280 for (i = 0; i < ARRAY_SIZE(chipinfo); i++) {
1281 if (of_device_is_compatible(np, chipinfo[i].compat))
1283 if (is_old_ls1021a &&
1284 !strcmp(chipinfo[i].compat, "fsl,ls1021a-clockgen"))
1288 if (i == ARRAY_SIZE(chipinfo)) {
1289 pr_err("%s: unknown clockgen node %s\n", __func__,
1293 clockgen.info = chipinfo[i];
1295 if (clockgen.info.guts_compat) {
1296 struct device_node *guts;
1298 guts = of_find_compatible_node(NULL, NULL,
1299 clockgen.info.guts_compat);
1301 clockgen.guts = of_iomap(guts, 0);
1302 if (!clockgen.guts) {
1303 pr_err("%s: Couldn't map %s regs\n", __func__,
1310 if (has_erratum_a4510())
1311 clockgen.info.flags |= CG_CMUX_GE_PLAT;
1313 clockgen.sysclk = create_sysclk("cg-sysclk");
1314 create_plls(&clockgen);
1315 create_muxes(&clockgen);
1317 if (clockgen.info.init_periph)
1318 clockgen.info.init_periph(&clockgen);
1320 ret = of_clk_add_provider(np, clockgen_clk_get, &clockgen);
1322 pr_err("%s: Couldn't register clk provider for node %s: %d\n",
1323 __func__, np->name, ret);
1328 iounmap(clockgen.regs);
1329 clockgen.regs = NULL;
1332 CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
1333 CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
1334 CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
1335 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
1336 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
1337 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
1338 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
1341 CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
1342 CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
1343 CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
1344 CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init);
1345 CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init);
1346 CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init);
1347 CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init);
1348 CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init);