2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * clock driver for Freescale QorIQ SoCs.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/clk-provider.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/of_platform.h>
20 #include <linux/slab.h>
25 unsigned int clk_per_pll;
29 #define PLL_KILL BIT(31)
30 #define CLKSEL_SHIFT 27
31 #define CLKSEL_ADJUST BIT(0)
32 #define to_cmux_clk(p) container_of(p, struct cmux_clk, hw)
34 static int cmux_set_parent(struct clk_hw *hw, u8 idx)
36 struct cmux_clk *clk = to_cmux_clk(hw);
39 clksel = ((idx / clk->clk_per_pll) << 2) + idx % clk->clk_per_pll;
40 if (clk->flags & CLKSEL_ADJUST)
42 clksel = (clksel & 0xf) << CLKSEL_SHIFT;
43 iowrite32be(clksel, clk->reg);
48 static u8 cmux_get_parent(struct clk_hw *hw)
50 struct cmux_clk *clk = to_cmux_clk(hw);
53 clksel = ioread32be(clk->reg);
54 clksel = (clksel >> CLKSEL_SHIFT) & 0xf;
55 if (clk->flags & CLKSEL_ADJUST)
57 clksel = (clksel >> 2) * clk->clk_per_pll + clksel % 4;
62 static const struct clk_ops cmux_ops = {
63 .get_parent = cmux_get_parent,
64 .set_parent = cmux_set_parent,
67 static void __init core_mux_init(struct device_node *np)
70 struct clk_init_data init;
71 struct cmux_clk *cmux_clk;
72 struct device_node *node;
76 const char **parent_names;
77 struct of_phandle_args clkspec;
79 rc = of_property_read_u32(np, "reg", &offset);
81 pr_err("%s: could not get reg property\n", np->name);
85 /* get the input clock source count */
86 count = of_property_count_strings(np, "clock-names");
88 pr_err("%s: get clock count error\n", np->name);
91 parent_names = kcalloc(count, sizeof(char *), GFP_KERNEL);
95 for (i = 0; i < count; i++)
96 parent_names[i] = of_clk_get_parent_name(np, i);
98 cmux_clk = kzalloc(sizeof(*cmux_clk), GFP_KERNEL);
102 cmux_clk->reg = of_iomap(np, 0);
103 if (!cmux_clk->reg) {
104 pr_err("%s: could not map register\n", __func__);
108 rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", 0,
111 pr_err("%s: parse clock node error\n", __func__);
115 cmux_clk->clk_per_pll = of_property_count_strings(clkspec.np,
116 "clock-output-names");
117 of_node_put(clkspec.np);
119 node = of_find_compatible_node(NULL, NULL, "fsl,p4080-clockgen");
120 if (node && (offset >= 0x80))
121 cmux_clk->flags = CLKSEL_ADJUST;
123 rc = of_property_read_string_index(np, "clock-output-names",
126 pr_err("%s: read clock names error\n", np->name);
130 init.name = clk_name;
131 init.ops = &cmux_ops;
132 init.parent_names = parent_names;
133 init.num_parents = count;
135 cmux_clk->hw.init = &init;
137 clk = clk_register(NULL, &cmux_clk->hw);
139 pr_err("%s: could not register clock\n", clk_name);
143 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
145 pr_err("Could not register clock provider for node:%s\n",
154 /* free *_names because they are reallocated when registered */
158 static void __init core_pll_init(struct device_node *np)
162 const char *clk_name, *parent_name;
163 struct clk_onecell_data *onecell_data;
164 struct clk **subclks;
167 base = of_iomap(np, 0);
169 pr_err("iomap error\n");
173 /* get the multiple of PLL */
174 mult = ioread32be(base);
176 /* check if this PLL is disabled */
177 if (mult & PLL_KILL) {
178 pr_debug("PLL:%s is disabled\n", np->name);
181 mult = (mult >> 1) & 0x3f;
183 parent_name = of_clk_get_parent_name(np, 0);
185 pr_err("PLL: %s must have a parent\n", np->name);
189 count = of_property_count_strings(np, "clock-output-names");
190 if (count < 0 || count > 4) {
191 pr_err("%s: clock is not supported\n", np->name);
195 subclks = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
199 onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL);
203 for (i = 0; i < count; i++) {
204 rc = of_property_read_string_index(np, "clock-output-names",
207 pr_err("%s: could not get clock names\n", np->name);
212 * when count == 4, there are 4 output clocks:
213 * /1, /2, /3, /4 respectively
214 * when count < 4, there are at least 2 output clocks:
215 * /1, /2, (/4, if count == 3) respectively.
218 subclks[i] = clk_register_fixed_factor(NULL, clk_name,
219 parent_name, 0, mult, 1 + i);
222 subclks[i] = clk_register_fixed_factor(NULL, clk_name,
223 parent_name, 0, mult, 1 << i);
225 if (IS_ERR(subclks[i])) {
226 pr_err("%s: could not register clock\n", clk_name);
231 onecell_data->clks = subclks;
232 onecell_data->clk_num = count;
234 rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
236 pr_err("Could not register clk provider for node:%s\n",
251 static void __init sysclk_init(struct device_node *node)
254 const char *clk_name = node->name;
255 struct device_node *np = of_get_parent(node);
259 pr_err("could not get parent node\n");
263 if (of_property_read_u32(np, "clock-frequency", &rate)) {
268 of_property_read_string(np, "clock-output-names", &clk_name);
270 clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, rate);
272 of_clk_add_provider(np, of_clk_src_simple_get, clk);
275 static void __init pltfrm_pll_init(struct device_node *np)
279 const char *parent_name, *clk_name;
281 struct clk_onecell_data *cod;
283 base = of_iomap(np, 0);
285 pr_err("%s(): %s: of_iomap() failed\n", __func__, np->name);
289 /* Get the multiple of PLL */
290 mult = ioread32be(base);
294 /* Check if this PLL is disabled */
295 if (mult & PLL_KILL) {
296 pr_debug("%s(): %s: Disabled\n", __func__, np->name);
299 mult = (mult & GENMASK(6, 1)) >> 1;
301 parent_name = of_clk_get_parent_name(np, 0);
303 pr_err("%s(): %s: of_clk_get_parent_name() failed\n",
308 i = of_property_count_strings(np, "clock-output-names");
310 pr_err("%s(): %s: of_property_count_strings(clock-output-names) = %d\n",
311 __func__, np->name, i);
315 cod = kmalloc(sizeof(*cod) + i * sizeof(struct clk *), GFP_KERNEL);
318 cod->clks = (struct clk **)(cod + 1);
321 for (i = 0; i < cod->clk_num; i++) {
322 _errno = of_property_read_string_index(np, "clock-output-names",
325 pr_err("%s(): %s: of_property_read_string_index(clock-output-names) = %d\n",
326 __func__, np->name, _errno);
327 goto return_clk_unregister;
330 cod->clks[i] = clk_register_fixed_factor(NULL, clk_name,
331 parent_name, 0, mult, 1 + i);
332 if (IS_ERR(cod->clks[i])) {
333 pr_err("%s(): %s: clk_register_fixed_factor(%s) = %ld\n",
335 clk_name, PTR_ERR(cod->clks[i]));
336 goto return_clk_unregister;
340 _errno = of_clk_add_provider(np, of_clk_src_onecell_get, cod);
342 pr_err("%s(): %s: of_clk_add_provider() = %d\n",
343 __func__, np->name, _errno);
344 goto return_clk_unregister;
349 return_clk_unregister:
351 clk_unregister(cod->clks[i]);
355 CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
356 CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
357 CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
358 CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init);
359 CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init);
360 CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init);
361 CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init);
362 CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init);