drivers/clk/clk-stm32f4.c

   1 /*
   2  * Author: Daniel Thompson <daniel.thompson@linaro.org>
   3  *
   4  * Inspired by clk-asm9260.c .
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/clk-provider.h>
  20 #include <linux/err.h>
  21 #include <linux/io.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/ioport.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28 #include <linux/regmap.h>
  29 #include <linux/mfd/syscon.h>
  30
  31 /*
  32  * Include list of clocks wich are not derived from system clock (SYSCLOCK)
  33  * The index of these clocks is the secondary index of DT bindings
  34  *
  35  */
  36 #include <dt-bindings/clock/stm32fx-clock.h>
  37
  38 #define STM32F4_RCC_CR                  0x00
  39 #define STM32F4_RCC_PLLCFGR             0x04
  40 #define STM32F4_RCC_CFGR                0x08
  41 #define STM32F4_RCC_AHB1ENR             0x30
  42 #define STM32F4_RCC_AHB2ENR             0x34
  43 #define STM32F4_RCC_AHB3ENR             0x38
  44 #define STM32F4_RCC_APB1ENR             0x40
  45 #define STM32F4_RCC_APB2ENR             0x44
  46 #define STM32F4_RCC_BDCR                0x70
  47 #define STM32F4_RCC_CSR                 0x74
  48 #define STM32F4_RCC_PLLI2SCFGR          0x84
  49 #define STM32F4_RCC_PLLSAICFGR          0x88
  50 #define STM32F4_RCC_DCKCFGR             0x8c
  51 #define STM32F7_RCC_DCKCFGR2            0x90
  52
  53 #define NONE -1
  54 #define NO_IDX  NONE
  55 #define NO_MUX  NONE
  56 #define NO_GATE NONE
  57
  58 struct stm32f4_gate_data {
  59         u8      offset;
  60         u8      bit_idx;
  61         const char *name;
  62         const char *parent_name;
  63         unsigned long flags;
  64 };
  65
  66 static const struct stm32f4_gate_data stm32f429_gates[] __initconst = {
  67         { STM32F4_RCC_AHB1ENR,  0,      "gpioa",        "ahb_div" },
  68         { STM32F4_RCC_AHB1ENR,  1,      "gpiob",        "ahb_div" },
  69         { STM32F4_RCC_AHB1ENR,  2,      "gpioc",        "ahb_div" },
  70         { STM32F4_RCC_AHB1ENR,  3,      "gpiod",        "ahb_div" },
  71         { STM32F4_RCC_AHB1ENR,  4,      "gpioe",        "ahb_div" },
  72         { STM32F4_RCC_AHB1ENR,  5,      "gpiof",        "ahb_div" },
  73         { STM32F4_RCC_AHB1ENR,  6,      "gpiog",        "ahb_div" },
  74         { STM32F4_RCC_AHB1ENR,  7,      "gpioh",        "ahb_div" },
  75         { STM32F4_RCC_AHB1ENR,  8,      "gpioi",        "ahb_div" },
  76         { STM32F4_RCC_AHB1ENR,  9,      "gpioj",        "ahb_div" },
  77         { STM32F4_RCC_AHB1ENR, 10,      "gpiok",        "ahb_div" },
  78         { STM32F4_RCC_AHB1ENR, 12,      "crc",          "ahb_div" },
  79         { STM32F4_RCC_AHB1ENR, 18,      "bkpsra",       "ahb_div" },
  80         { STM32F4_RCC_AHB1ENR, 20,      "ccmdatam",     "ahb_div" },
  81         { STM32F4_RCC_AHB1ENR, 21,      "dma1",         "ahb_div" },
  82         { STM32F4_RCC_AHB1ENR, 22,      "dma2",         "ahb_div" },
  83         { STM32F4_RCC_AHB1ENR, 23,      "dma2d",        "ahb_div" },
  84         { STM32F4_RCC_AHB1ENR, 25,      "ethmac",       "ahb_div" },
  85         { STM32F4_RCC_AHB1ENR, 26,      "ethmactx",     "ahb_div" },
  86         { STM32F4_RCC_AHB1ENR, 27,      "ethmacrx",     "ahb_div" },
  87         { STM32F4_RCC_AHB1ENR, 28,      "ethmacptp",    "ahb_div" },
  88         { STM32F4_RCC_AHB1ENR, 29,      "otghs",        "ahb_div" },
  89         { STM32F4_RCC_AHB1ENR, 30,      "otghsulpi",    "ahb_div" },
  90
  91         { STM32F4_RCC_AHB2ENR,  0,      "dcmi",         "ahb_div" },
  92         { STM32F4_RCC_AHB2ENR,  4,      "cryp",         "ahb_div" },
  93         { STM32F4_RCC_AHB2ENR,  5,      "hash",         "ahb_div" },
  94         { STM32F4_RCC_AHB2ENR,  6,      "rng",          "pll48" },
  95         { STM32F4_RCC_AHB2ENR,  7,      "otgfs",        "pll48" },
  96
  97         { STM32F4_RCC_AHB3ENR,  0,      "fmc",          "ahb_div",
  98                 CLK_IGNORE_UNUSED },
  99
 100         { STM32F4_RCC_APB1ENR,  0,      "tim2",         "apb1_mul" },
 101         { STM32F4_RCC_APB1ENR,  1,      "tim3",         "apb1_mul" },
 102         { STM32F4_RCC_APB1ENR,  2,      "tim4",         "apb1_mul" },
 103         { STM32F4_RCC_APB1ENR,  3,      "tim5",         "apb1_mul" },
 104         { STM32F4_RCC_APB1ENR,  4,      "tim6",         "apb1_mul" },
 105         { STM32F4_RCC_APB1ENR,  5,      "tim7",         "apb1_mul" },
 106         { STM32F4_RCC_APB1ENR,  6,      "tim12",        "apb1_mul" },
 107         { STM32F4_RCC_APB1ENR,  7,      "tim13",        "apb1_mul" },
 108         { STM32F4_RCC_APB1ENR,  8,      "tim14",        "apb1_mul" },
 109         { STM32F4_RCC_APB1ENR, 11,      "wwdg",         "apb1_div" },
 110         { STM32F4_RCC_APB1ENR, 14,      "spi2",         "apb1_div" },
 111         { STM32F4_RCC_APB1ENR, 15,      "spi3",         "apb1_div" },
 112         { STM32F4_RCC_APB1ENR, 17,      "uart2",        "apb1_div" },
 113         { STM32F4_RCC_APB1ENR, 18,      "uart3",        "apb1_div" },
 114         { STM32F4_RCC_APB1ENR, 19,      "uart4",        "apb1_div" },
 115         { STM32F4_RCC_APB1ENR, 20,      "uart5",        "apb1_div" },
 116         { STM32F4_RCC_APB1ENR, 21,      "i2c1",         "apb1_div" },
 117         { STM32F4_RCC_APB1ENR, 22,      "i2c2",         "apb1_div" },
 118         { STM32F4_RCC_APB1ENR, 23,      "i2c3",         "apb1_div" },
 119         { STM32F4_RCC_APB1ENR, 25,      "can1",         "apb1_div" },
 120         { STM32F4_RCC_APB1ENR, 26,      "can2",         "apb1_div" },
 121         { STM32F4_RCC_APB1ENR, 28,      "pwr",          "apb1_div" },
 122         { STM32F4_RCC_APB1ENR, 29,      "dac",          "apb1_div" },
 123         { STM32F4_RCC_APB1ENR, 30,      "uart7",        "apb1_div" },
 124         { STM32F4_RCC_APB1ENR, 31,      "uart8",        "apb1_div" },
 125
 126         { STM32F4_RCC_APB2ENR,  0,      "tim1",         "apb2_mul" },
 127         { STM32F4_RCC_APB2ENR,  1,      "tim8",         "apb2_mul" },
 128         { STM32F4_RCC_APB2ENR,  4,      "usart1",       "apb2_div" },
 129         { STM32F4_RCC_APB2ENR,  5,      "usart6",       "apb2_div" },
 130         { STM32F4_RCC_APB2ENR,  8,      "adc1",         "apb2_div" },
 131         { STM32F4_RCC_APB2ENR,  9,      "adc2",         "apb2_div" },
 132         { STM32F4_RCC_APB2ENR, 10,      "adc3",         "apb2_div" },
 133         { STM32F4_RCC_APB2ENR, 11,      "sdio",         "pll48" },
 134         { STM32F4_RCC_APB2ENR, 12,      "spi1",         "apb2_div" },
 135         { STM32F4_RCC_APB2ENR, 13,      "spi4",         "apb2_div" },
 136         { STM32F4_RCC_APB2ENR, 14,      "syscfg",       "apb2_div" },
 137         { STM32F4_RCC_APB2ENR, 16,      "tim9",         "apb2_mul" },
 138         { STM32F4_RCC_APB2ENR, 17,      "tim10",        "apb2_mul" },
 139         { STM32F4_RCC_APB2ENR, 18,      "tim11",        "apb2_mul" },
 140         { STM32F4_RCC_APB2ENR, 20,      "spi5",         "apb2_div" },
 141         { STM32F4_RCC_APB2ENR, 21,      "spi6",         "apb2_div" },
 142         { STM32F4_RCC_APB2ENR, 22,      "sai1",         "apb2_div" },
 143         { STM32F4_RCC_APB2ENR, 26,      "ltdc",         "apb2_div" },
 144 };
 145
 146 static const struct stm32f4_gate_data stm32f469_gates[] __initconst = {
 147         { STM32F4_RCC_AHB1ENR,  0,      "gpioa",        "ahb_div" },
 148         { STM32F4_RCC_AHB1ENR,  1,      "gpiob",        "ahb_div" },
 149         { STM32F4_RCC_AHB1ENR,  2,      "gpioc",        "ahb_div" },
 150         { STM32F4_RCC_AHB1ENR,  3,      "gpiod",        "ahb_div" },
 151         { STM32F4_RCC_AHB1ENR,  4,      "gpioe",        "ahb_div" },
 152         { STM32F4_RCC_AHB1ENR,  5,      "gpiof",        "ahb_div" },
 153         { STM32F4_RCC_AHB1ENR,  6,      "gpiog",        "ahb_div" },
 154         { STM32F4_RCC_AHB1ENR,  7,      "gpioh",        "ahb_div" },
 155         { STM32F4_RCC_AHB1ENR,  8,      "gpioi",        "ahb_div" },
 156         { STM32F4_RCC_AHB1ENR,  9,      "gpioj",        "ahb_div" },
 157         { STM32F4_RCC_AHB1ENR, 10,      "gpiok",        "ahb_div" },
 158         { STM32F4_RCC_AHB1ENR, 12,      "crc",          "ahb_div" },
 159         { STM32F4_RCC_AHB1ENR, 18,      "bkpsra",       "ahb_div" },
 160         { STM32F4_RCC_AHB1ENR, 20,      "ccmdatam",     "ahb_div" },
 161         { STM32F4_RCC_AHB1ENR, 21,      "dma1",         "ahb_div" },
 162         { STM32F4_RCC_AHB1ENR, 22,      "dma2",         "ahb_div" },
 163         { STM32F4_RCC_AHB1ENR, 23,      "dma2d",        "ahb_div" },
 164         { STM32F4_RCC_AHB1ENR, 25,      "ethmac",       "ahb_div" },
 165         { STM32F4_RCC_AHB1ENR, 26,      "ethmactx",     "ahb_div" },
 166         { STM32F4_RCC_AHB1ENR, 27,      "ethmacrx",     "ahb_div" },
 167         { STM32F4_RCC_AHB1ENR, 28,      "ethmacptp",    "ahb_div" },
 168         { STM32F4_RCC_AHB1ENR, 29,      "otghs",        "ahb_div" },
 169         { STM32F4_RCC_AHB1ENR, 30,      "otghsulpi",    "ahb_div" },
 170
 171         { STM32F4_RCC_AHB2ENR,  0,      "dcmi",         "ahb_div" },
 172         { STM32F4_RCC_AHB2ENR,  4,      "cryp",         "ahb_div" },
 173         { STM32F4_RCC_AHB2ENR,  5,      "hash",         "ahb_div" },
 174         { STM32F4_RCC_AHB2ENR,  6,      "rng",          "pll48" },
 175         { STM32F4_RCC_AHB2ENR,  7,      "otgfs",        "pll48" },
 176
 177         { STM32F4_RCC_AHB3ENR,  0,      "fmc",          "ahb_div",
 178                 CLK_IGNORE_UNUSED },
 179         { STM32F4_RCC_AHB3ENR,  1,      "qspi",         "ahb_div",
 180                 CLK_IGNORE_UNUSED },
 181
 182         { STM32F4_RCC_APB1ENR,  0,      "tim2",         "apb1_mul" },
 183         { STM32F4_RCC_APB1ENR,  1,      "tim3",         "apb1_mul" },
 184         { STM32F4_RCC_APB1ENR,  2,      "tim4",         "apb1_mul" },
 185         { STM32F4_RCC_APB1ENR,  3,      "tim5",         "apb1_mul" },
 186         { STM32F4_RCC_APB1ENR,  4,      "tim6",         "apb1_mul" },
 187         { STM32F4_RCC_APB1ENR,  5,      "tim7",         "apb1_mul" },
 188         { STM32F4_RCC_APB1ENR,  6,      "tim12",        "apb1_mul" },
 189         { STM32F4_RCC_APB1ENR,  7,      "tim13",        "apb1_mul" },
 190         { STM32F4_RCC_APB1ENR,  8,      "tim14",        "apb1_mul" },
 191         { STM32F4_RCC_APB1ENR, 11,      "wwdg",         "apb1_div" },
 192         { STM32F4_RCC_APB1ENR, 14,      "spi2",         "apb1_div" },
 193         { STM32F4_RCC_APB1ENR, 15,      "spi3",         "apb1_div" },
 194         { STM32F4_RCC_APB1ENR, 17,      "uart2",        "apb1_div" },
 195         { STM32F4_RCC_APB1ENR, 18,      "uart3",        "apb1_div" },
 196         { STM32F4_RCC_APB1ENR, 19,      "uart4",        "apb1_div" },
 197         { STM32F4_RCC_APB1ENR, 20,      "uart5",        "apb1_div" },
 198         { STM32F4_RCC_APB1ENR, 21,      "i2c1",         "apb1_div" },
 199         { STM32F4_RCC_APB1ENR, 22,      "i2c2",         "apb1_div" },
 200         { STM32F4_RCC_APB1ENR, 23,      "i2c3",         "apb1_div" },
 201         { STM32F4_RCC_APB1ENR, 25,      "can1",         "apb1_div" },
 202         { STM32F4_RCC_APB1ENR, 26,      "can2",         "apb1_div" },
 203         { STM32F4_RCC_APB1ENR, 28,      "pwr",          "apb1_div" },
 204         { STM32F4_RCC_APB1ENR, 29,      "dac",          "apb1_div" },
 205         { STM32F4_RCC_APB1ENR, 30,      "uart7",        "apb1_div" },
 206         { STM32F4_RCC_APB1ENR, 31,      "uart8",        "apb1_div" },
 207
 208         { STM32F4_RCC_APB2ENR,  0,      "tim1",         "apb2_mul" },
 209         { STM32F4_RCC_APB2ENR,  1,      "tim8",         "apb2_mul" },
 210         { STM32F4_RCC_APB2ENR,  4,      "usart1",       "apb2_div" },
 211         { STM32F4_RCC_APB2ENR,  5,      "usart6",       "apb2_div" },
 212         { STM32F4_RCC_APB2ENR,  8,      "adc1",         "apb2_div" },
 213         { STM32F4_RCC_APB2ENR,  9,      "adc2",         "apb2_div" },
 214         { STM32F4_RCC_APB2ENR, 10,      "adc3",         "apb2_div" },
 215         { STM32F4_RCC_APB2ENR, 11,      "sdio",         "sdmux" },
 216         { STM32F4_RCC_APB2ENR, 12,      "spi1",         "apb2_div" },
 217         { STM32F4_RCC_APB2ENR, 13,      "spi4",         "apb2_div" },
 218         { STM32F4_RCC_APB2ENR, 14,      "syscfg",       "apb2_div" },
 219         { STM32F4_RCC_APB2ENR, 16,      "tim9",         "apb2_mul" },
 220         { STM32F4_RCC_APB2ENR, 17,      "tim10",        "apb2_mul" },
 221         { STM32F4_RCC_APB2ENR, 18,      "tim11",        "apb2_mul" },
 222         { STM32F4_RCC_APB2ENR, 20,      "spi5",         "apb2_div" },
 223         { STM32F4_RCC_APB2ENR, 21,      "spi6",         "apb2_div" },
 224         { STM32F4_RCC_APB2ENR, 22,      "sai1",         "apb2_div" },
 225         { STM32F4_RCC_APB2ENR, 26,      "ltdc",         "apb2_div" },
 226 };
 227
 228 static const struct stm32f4_gate_data stm32f746_gates[] __initconst = {
 229         { STM32F4_RCC_AHB1ENR,  0,      "gpioa",        "ahb_div" },
 230         { STM32F4_RCC_AHB1ENR,  1,      "gpiob",        "ahb_div" },
 231         { STM32F4_RCC_AHB1ENR,  2,      "gpioc",        "ahb_div" },
 232         { STM32F4_RCC_AHB1ENR,  3,      "gpiod",        "ahb_div" },
 233         { STM32F4_RCC_AHB1ENR,  4,      "gpioe",        "ahb_div" },
 234         { STM32F4_RCC_AHB1ENR,  5,      "gpiof",        "ahb_div" },
 235         { STM32F4_RCC_AHB1ENR,  6,      "gpiog",        "ahb_div" },
 236         { STM32F4_RCC_AHB1ENR,  7,      "gpioh",        "ahb_div" },
 237         { STM32F4_RCC_AHB1ENR,  8,      "gpioi",        "ahb_div" },
 238         { STM32F4_RCC_AHB1ENR,  9,      "gpioj",        "ahb_div" },
 239         { STM32F4_RCC_AHB1ENR, 10,      "gpiok",        "ahb_div" },
 240         { STM32F4_RCC_AHB1ENR, 12,      "crc",          "ahb_div" },
 241         { STM32F4_RCC_AHB1ENR, 18,      "bkpsra",       "ahb_div" },
 242         { STM32F4_RCC_AHB1ENR, 20,      "dtcmram",      "ahb_div" },
 243         { STM32F4_RCC_AHB1ENR, 21,      "dma1",         "ahb_div" },
 244         { STM32F4_RCC_AHB1ENR, 22,      "dma2",         "ahb_div" },
 245         { STM32F4_RCC_AHB1ENR, 23,      "dma2d",        "ahb_div" },
 246         { STM32F4_RCC_AHB1ENR, 25,      "ethmac",       "ahb_div" },
 247         { STM32F4_RCC_AHB1ENR, 26,      "ethmactx",     "ahb_div" },
 248         { STM32F4_RCC_AHB1ENR, 27,      "ethmacrx",     "ahb_div" },
 249         { STM32F4_RCC_AHB1ENR, 28,      "ethmacptp",    "ahb_div" },
 250         { STM32F4_RCC_AHB1ENR, 29,      "otghs",        "ahb_div" },
 251         { STM32F4_RCC_AHB1ENR, 30,      "otghsulpi",    "ahb_div" },
 252
 253         { STM32F4_RCC_AHB2ENR,  0,      "dcmi",         "ahb_div" },
 254         { STM32F4_RCC_AHB2ENR,  4,      "cryp",         "ahb_div" },
 255         { STM32F4_RCC_AHB2ENR,  5,      "hash",         "ahb_div" },
 256         { STM32F4_RCC_AHB2ENR,  6,      "rng",          "pll48"   },
 257         { STM32F4_RCC_AHB2ENR,  7,      "otgfs",        "pll48"   },
 258
 259         { STM32F4_RCC_AHB3ENR,  0,      "fmc",          "ahb_div",
 260                 CLK_IGNORE_UNUSED },
 261         { STM32F4_RCC_AHB3ENR,  1,      "qspi",         "ahb_div",
 262                 CLK_IGNORE_UNUSED },
 263
 264         { STM32F4_RCC_APB1ENR,  0,      "tim2",         "apb1_mul" },
 265         { STM32F4_RCC_APB1ENR,  1,      "tim3",         "apb1_mul" },
 266         { STM32F4_RCC_APB1ENR,  2,      "tim4",         "apb1_mul" },
 267         { STM32F4_RCC_APB1ENR,  3,      "tim5",         "apb1_mul" },
 268         { STM32F4_RCC_APB1ENR,  4,      "tim6",         "apb1_mul" },
 269         { STM32F4_RCC_APB1ENR,  5,      "tim7",         "apb1_mul" },
 270         { STM32F4_RCC_APB1ENR,  6,      "tim12",        "apb1_mul" },
 271         { STM32F4_RCC_APB1ENR,  7,      "tim13",        "apb1_mul" },
 272         { STM32F4_RCC_APB1ENR,  8,      "tim14",        "apb1_mul" },
 273         { STM32F4_RCC_APB1ENR, 11,      "wwdg",         "apb1_div" },
 274         { STM32F4_RCC_APB1ENR, 14,      "spi2",         "apb1_div" },
 275         { STM32F4_RCC_APB1ENR, 15,      "spi3",         "apb1_div" },
 276         { STM32F4_RCC_APB1ENR, 16,      "spdifrx",      "apb1_div" },
 277         { STM32F4_RCC_APB1ENR, 25,      "can1",         "apb1_div" },
 278         { STM32F4_RCC_APB1ENR, 26,      "can2",         "apb1_div" },
 279         { STM32F4_RCC_APB1ENR, 27,      "cec",          "apb1_div" },
 280         { STM32F4_RCC_APB1ENR, 28,      "pwr",          "apb1_div" },
 281         { STM32F4_RCC_APB1ENR, 29,      "dac",          "apb1_div" },
 282
 283         { STM32F4_RCC_APB2ENR,  0,      "tim1",         "apb2_mul" },
 284         { STM32F4_RCC_APB2ENR,  1,      "tim8",         "apb2_mul" },
 285         { STM32F4_RCC_APB2ENR,  8,      "adc1",         "apb2_div" },
 286         { STM32F4_RCC_APB2ENR,  9,      "adc2",         "apb2_div" },
 287         { STM32F4_RCC_APB2ENR, 10,      "adc3",         "apb2_div" },
 288         { STM32F4_RCC_APB2ENR, 11,      "sdmmc",        "sdmux"    },
 289         { STM32F4_RCC_APB2ENR, 12,      "spi1",         "apb2_div" },
 290         { STM32F4_RCC_APB2ENR, 13,      "spi4",         "apb2_div" },
 291         { STM32F4_RCC_APB2ENR, 14,      "syscfg",       "apb2_div" },
 292         { STM32F4_RCC_APB2ENR, 16,      "tim9",         "apb2_mul" },
 293         { STM32F4_RCC_APB2ENR, 17,      "tim10",        "apb2_mul" },
 294         { STM32F4_RCC_APB2ENR, 18,      "tim11",        "apb2_mul" },
 295         { STM32F4_RCC_APB2ENR, 20,      "spi5",         "apb2_div" },
 296         { STM32F4_RCC_APB2ENR, 21,      "spi6",         "apb2_div" },
 297         { STM32F4_RCC_APB2ENR, 22,      "sai1",         "apb2_div" },
 298         { STM32F4_RCC_APB2ENR, 23,      "sai2",         "apb2_div" },
 299         { STM32F4_RCC_APB2ENR, 26,      "ltdc",         "apb2_div" },
 300 };
 301
 302 /*
 303  * This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx
 304  * have gate bits associated with them. Its combined hweight is 71.
 305  */
 306 #define MAX_GATE_MAP 3
 307
 308 static const u64 stm32f42xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
 309                                                        0x0000000000000001ull,
 310                                                        0x04777f33f6fec9ffull };
 311
 312 static const u64 stm32f46xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
 313                                                        0x0000000000000003ull,
 314                                                        0x0c777f33f6fec9ffull };
 315
 316 static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
 317                                                       0x0000000000000003ull,
 318                                                       0x04f77f033e01c9ffull };
 319
 320 static const u64 *stm32f4_gate_map;
 321
 322 static struct clk_hw **clks;
 323
 324 static DEFINE_SPINLOCK(stm32f4_clk_lock);
 325 static void __iomem *base;
 326
 327 static struct regmap *pdrm;
 328
 329 static int stm32fx_end_primary_clk;
 330
 331 /*
 332  * "Multiplier" device for APBx clocks.
 333  *
 334  * The APBx dividers are power-of-two dividers and, if *not* running in 1:1
 335  * mode, they also tap out the one of the low order state bits to run the
 336  * timers. ST datasheets represent this feature as a (conditional) clock
 337  * multiplier.
 338  */
 339 struct clk_apb_mul {
 340         struct clk_hw hw;
 341         u8 bit_idx;
 342 };
 343
 344 #define to_clk_apb_mul(_hw) container_of(_hw, struct clk_apb_mul, hw)
 345
 346 static unsigned long clk_apb_mul_recalc_rate(struct clk_hw *hw,
 347                                              unsigned long parent_rate)
 348 {
 349         struct clk_apb_mul *am = to_clk_apb_mul(hw);
 350
 351         if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
 352                 return parent_rate * 2;
 353
 354         return parent_rate;
 355 }
 356
 357 static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate,
 358                                    unsigned long *prate)
 359 {
 360         struct clk_apb_mul *am = to_clk_apb_mul(hw);
 361         unsigned long mult = 1;
 362
 363         if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
 364                 mult = 2;
 365
 366         if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
 367                 unsigned long best_parent = rate / mult;
 368
 369                 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
 370         }
 371
 372         return *prate * mult;
 373 }
 374
 375 static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate,
 376                                 unsigned long parent_rate)
 377 {
 378         /*
 379          * We must report success but we can do so unconditionally because
 380          * clk_apb_mul_round_rate returns values that ensure this call is a
 381          * nop.
 382          */
 383
 384         return 0;
 385 }
 386
 387 static const struct clk_ops clk_apb_mul_factor_ops = {
 388         .round_rate = clk_apb_mul_round_rate,
 389         .set_rate = clk_apb_mul_set_rate,
 390         .recalc_rate = clk_apb_mul_recalc_rate,
 391 };
 392
 393 static struct clk *clk_register_apb_mul(struct device *dev, const char *name,
 394                                         const char *parent_name,
 395                                         unsigned long flags, u8 bit_idx)
 396 {
 397         struct clk_apb_mul *am;
 398         struct clk_init_data init;
 399         struct clk *clk;
 400
 401         am = kzalloc(sizeof(*am), GFP_KERNEL);
 402         if (!am)
 403                 return ERR_PTR(-ENOMEM);
 404
 405         am->bit_idx = bit_idx;
 406         am->hw.init = &init;
 407
 408         init.name = name;
 409         init.ops = &clk_apb_mul_factor_ops;
 410         init.flags = flags;
 411         init.parent_names = &parent_name;
 412         init.num_parents = 1;
 413
 414         clk = clk_register(dev, &am->hw);
 415
 416         if (IS_ERR(clk))
 417                 kfree(am);
 418
 419         return clk;
 420 }
 421
 422 enum {
 423         PLL,
 424         PLL_I2S,
 425         PLL_SAI,
 426 };
 427
 428 static const struct clk_div_table pll_divp_table[] = {
 429         { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, { 0 }
 430 };
 431
 432 static const struct clk_div_table pll_divr_table[] = {
 433         { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 }
 434 };
 435
 436 struct stm32f4_pll {
 437         spinlock_t *lock;
 438         struct  clk_gate gate;
 439         u8 offset;
 440         u8 bit_rdy_idx;
 441         u8 status;
 442         u8 n_start;
 443 };
 444
 445 #define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate)
 446
 447 struct stm32f4_pll_post_div_data {
 448         int idx;
 449         u8 pll_num;
 450         const char *name;
 451         const char *parent;
 452         u8 flag;
 453         u8 offset;
 454         u8 shift;
 455         u8 width;
 456         u8 flag_div;
 457         const struct clk_div_table *div_table;
 458 };
 459
 460 struct stm32f4_vco_data {
 461         const char *vco_name;
 462         u8 offset;
 463         u8 bit_idx;
 464         u8 bit_rdy_idx;
 465 };
 466
 467 static const struct stm32f4_vco_data  vco_data[] = {
 468         { "vco",     STM32F4_RCC_PLLCFGR,    24, 25 },
 469         { "vco-i2s", STM32F4_RCC_PLLI2SCFGR, 26, 27 },
 470         { "vco-sai", STM32F4_RCC_PLLSAICFGR, 28, 29 },
 471 };
 472
 473
 474 static const struct clk_div_table post_divr_table[] = {
 475         { 0, 2 }, { 1, 4 }, { 2, 8 }, { 3, 16 }, { 0 }
 476 };
 477
 478 #define MAX_POST_DIV 3
 479 static const struct stm32f4_pll_post_div_data  post_div_data[MAX_POST_DIV] = {
 480         { CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q",
 481                 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL},
 482
 483         { CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q",
 484                 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL },
 485
 486         { NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
 487                 STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table },
 488 };
 489
 490 struct stm32f4_div_data {
 491         u8 shift;
 492         u8 width;
 493         u8 flag_div;
 494         const struct clk_div_table *div_table;
 495 };
 496
 497 #define MAX_PLL_DIV 3
 498 static const struct stm32f4_div_data  div_data[MAX_PLL_DIV] = {
 499         { 16, 2, 0,                     pll_divp_table  },
 500         { 24, 4, CLK_DIVIDER_ONE_BASED, NULL            },
 501         { 28, 3, 0,                     pll_divr_table  },
 502 };
 503
 504 struct stm32f4_pll_data {
 505         u8 pll_num;
 506         u8 n_start;
 507         const char *div_name[MAX_PLL_DIV];
 508 };
 509
 510 static const struct stm32f4_pll_data stm32f429_pll[MAX_PLL_DIV] = {
 511         { PLL,     192, { "pll", "pll48",    NULL       } },
 512         { PLL_I2S, 192, { NULL,  "plli2s-q", "plli2s-r" } },
 513         { PLL_SAI,  49, { NULL,  "pllsai-q", "pllsai-r" } },
 514 };
 515
 516 static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
 517         { PLL,     50, { "pll",      "pll-q",    NULL       } },
 518         { PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
 519         { PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
 520 };
 521
 522 static int stm32f4_pll_is_enabled(struct clk_hw *hw)
 523 {
 524         return clk_gate_ops.is_enabled(hw);
 525 }
 526
 527 static int stm32f4_pll_enable(struct clk_hw *hw)
 528 {
 529         struct clk_gate *gate = to_clk_gate(hw);
 530         struct stm32f4_pll *pll = to_stm32f4_pll(gate);
 531         int ret = 0;
 532         unsigned long reg;
 533
 534         ret = clk_gate_ops.enable(hw);
 535
 536         ret = readl_relaxed_poll_timeout_atomic(base + STM32F4_RCC_CR, reg,
 537                         reg & (1 << pll->bit_rdy_idx), 0, 10000);
 538
 539         return ret;
 540 }
 541
 542 static void stm32f4_pll_disable(struct clk_hw *hw)
 543 {
 544         clk_gate_ops.disable(hw);
 545 }
 546
 547 static unsigned long stm32f4_pll_recalc(struct clk_hw *hw,
 548                 unsigned long parent_rate)
 549 {
 550         struct clk_gate *gate = to_clk_gate(hw);
 551         struct stm32f4_pll *pll = to_stm32f4_pll(gate);
 552         unsigned long n;
 553
 554         n = (readl(base + pll->offset) >> 6) & 0x1ff;
 555
 556         return parent_rate * n;
 557 }
 558
 559 static long stm32f4_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 560                 unsigned long *prate)
 561 {
 562         struct clk_gate *gate = to_clk_gate(hw);
 563         struct stm32f4_pll *pll = to_stm32f4_pll(gate);
 564         unsigned long n;
 565
 566         n = rate / *prate;
 567
 568         if (n < pll->n_start)
 569                 n = pll->n_start;
 570         else if (n > 432)
 571                 n = 432;
 572
 573         return *prate * n;
 574 }
 575
 576 static int stm32f4_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 577                                 unsigned long parent_rate)
 578 {
 579         struct clk_gate *gate = to_clk_gate(hw);
 580         struct stm32f4_pll *pll = to_stm32f4_pll(gate);
 581
 582         unsigned long n;
 583         unsigned long val;
 584         int pll_state;
 585
 586         pll_state = stm32f4_pll_is_enabled(hw);
 587
 588         if (pll_state)
 589                 stm32f4_pll_disable(hw);
 590
 591         n = rate  / parent_rate;
 592
 593         val = readl(base + pll->offset) & ~(0x1ff << 6);
 594
 595         writel(val | ((n & 0x1ff) <<  6), base + pll->offset);
 596
 597         if (pll_state)
 598                 stm32f4_pll_enable(hw);
 599
 600         return 0;
 601 }
 602
 603 static const struct clk_ops stm32f4_pll_gate_ops = {
 604         .enable         = stm32f4_pll_enable,
 605         .disable        = stm32f4_pll_disable,
 606         .is_enabled     = stm32f4_pll_is_enabled,
 607         .recalc_rate    = stm32f4_pll_recalc,
 608         .round_rate     = stm32f4_pll_round_rate,
 609         .set_rate       = stm32f4_pll_set_rate,
 610 };
 611
 612 struct stm32f4_pll_div {
 613         struct clk_divider div;
 614         struct clk_hw *hw_pll;
 615 };
 616
 617 #define to_pll_div_clk(_div) container_of(_div, struct stm32f4_pll_div, div)
 618
 619 static unsigned long stm32f4_pll_div_recalc_rate(struct clk_hw *hw,
 620                 unsigned long parent_rate)
 621 {
 622         return clk_divider_ops.recalc_rate(hw, parent_rate);
 623 }
 624
 625 static long stm32f4_pll_div_round_rate(struct clk_hw *hw, unsigned long rate,
 626                                 unsigned long *prate)
 627 {
 628         return clk_divider_ops.round_rate(hw, rate, prate);
 629 }
 630
 631 static int stm32f4_pll_div_set_rate(struct clk_hw *hw, unsigned long rate,
 632                                 unsigned long parent_rate)
 633 {
 634         int pll_state, ret;
 635
 636         struct clk_divider *div = to_clk_divider(hw);
 637         struct stm32f4_pll_div *pll_div = to_pll_div_clk(div);
 638
 639         pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll);
 640
 641         if (pll_state)
 642                 stm32f4_pll_disable(pll_div->hw_pll);
 643
 644         ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
 645
 646         if (pll_state)
 647                 stm32f4_pll_enable(pll_div->hw_pll);
 648
 649         return ret;
 650 }
 651
 652 static const struct clk_ops stm32f4_pll_div_ops = {
 653         .recalc_rate = stm32f4_pll_div_recalc_rate,
 654         .round_rate = stm32f4_pll_div_round_rate,
 655         .set_rate = stm32f4_pll_div_set_rate,
 656 };
 657
 658 static struct clk_hw *clk_register_pll_div(const char *name,
 659                 const char *parent_name, unsigned long flags,
 660                 void __iomem *reg, u8 shift, u8 width,
 661                 u8 clk_divider_flags, const struct clk_div_table *table,
 662                 struct clk_hw *pll_hw, spinlock_t *lock)
 663 {
 664         struct stm32f4_pll_div *pll_div;
 665         struct clk_hw *hw;
 666         struct clk_init_data init;
 667         int ret;
 668
 669         /* allocate the divider */
 670         pll_div = kzalloc(sizeof(*pll_div), GFP_KERNEL);
 671         if (!pll_div)
 672                 return ERR_PTR(-ENOMEM);
 673
 674         init.name = name;
 675         init.ops = &stm32f4_pll_div_ops;
 676         init.flags = flags;
 677         init.parent_names = (parent_name ? &parent_name : NULL);
 678         init.num_parents = (parent_name ? 1 : 0);
 679
 680         /* struct clk_divider assignments */
 681         pll_div->div.reg = reg;
 682         pll_div->div.shift = shift;
 683         pll_div->div.width = width;
 684         pll_div->div.flags = clk_divider_flags;
 685         pll_div->div.lock = lock;
 686         pll_div->div.table = table;
 687         pll_div->div.hw.init = &init;
 688
 689         pll_div->hw_pll = pll_hw;
 690
 691         /* register the clock */
 692         hw = &pll_div->div.hw;
 693         ret = clk_hw_register(NULL, hw);
 694         if (ret) {
 695                 kfree(pll_div);
 696                 hw = ERR_PTR(ret);
 697         }
 698
 699         return hw;
 700 }
 701
 702 static struct clk_hw *stm32f4_rcc_register_pll(const char *pllsrc,
 703                 const struct stm32f4_pll_data *data,  spinlock_t *lock)
 704 {
 705         struct stm32f4_pll *pll;
 706         struct clk_init_data init = { NULL };
 707         void __iomem *reg;
 708         struct clk_hw *pll_hw;
 709         int ret;
 710         int i;
 711         const struct stm32f4_vco_data *vco;
 712
 713
 714         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 715         if (!pll)
 716                 return ERR_PTR(-ENOMEM);
 717
 718         vco = &vco_data[data->pll_num];
 719
 720         init.name = vco->vco_name;
 721         init.ops = &stm32f4_pll_gate_ops;
 722         init.flags = CLK_SET_RATE_GATE;
 723         init.parent_names = &pllsrc;
 724         init.num_parents = 1;
 725
 726         pll->gate.lock = lock;
 727         pll->gate.reg = base + STM32F4_RCC_CR;
 728         pll->gate.bit_idx = vco->bit_idx;
 729         pll->gate.hw.init = &init;
 730
 731         pll->offset = vco->offset;
 732         pll->n_start = data->n_start;
 733         pll->bit_rdy_idx = vco->bit_rdy_idx;
 734         pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1;
 735
 736         reg = base + pll->offset;
 737
 738         pll_hw = &pll->gate.hw;
 739         ret = clk_hw_register(NULL, pll_hw);
 740         if (ret) {
 741                 kfree(pll);
 742                 return ERR_PTR(ret);
 743         }
 744
 745         for (i = 0; i < MAX_PLL_DIV; i++)
 746                 if (data->div_name[i])
 747                         clk_register_pll_div(data->div_name[i],
 748                                         vco->vco_name,
 749                                         0,
 750                                         reg,
 751                                         div_data[i].shift,
 752                                         div_data[i].width,
 753                                         div_data[i].flag_div,
 754                                         div_data[i].div_table,
 755                                         pll_hw,
 756                                         lock);
 757         return pll_hw;
 758 }
 759
 760 /*
 761  * Converts the primary and secondary indices (as they appear in DT) to an
 762  * offset into our struct clock array.
 763  */
 764 static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
 765 {
 766         u64 table[MAX_GATE_MAP];
 767
 768         if (primary == 1) {
 769                 if (WARN_ON(secondary >= stm32fx_end_primary_clk))
 770                         return -EINVAL;
 771                 return secondary;
 772         }
 773
 774         memcpy(table, stm32f4_gate_map, sizeof(table));
 775
 776         /* only bits set in table can be used as indices */
 777         if (WARN_ON(secondary >= BITS_PER_BYTE * sizeof(table) ||
 778                     0 == (table[BIT_ULL_WORD(secondary)] &
 779                           BIT_ULL_MASK(secondary))))
 780                 return -EINVAL;
 781
 782         /* mask out bits above our current index */
 783         table[BIT_ULL_WORD(secondary)] &=
 784             GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0);
 785
 786         return stm32fx_end_primary_clk - 1 + hweight64(table[0]) +
 787                (BIT_ULL_WORD(secondary) >= 1 ? hweight64(table[1]) : 0) +
 788                (BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0);
 789 }
 790
 791 static struct clk_hw *
 792 stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data)
 793 {
 794         int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]);
 795
 796         if (i < 0)
 797                 return ERR_PTR(-EINVAL);
 798
 799         return clks[i];
 800 }
 801
 802 #define to_rgclk(_rgate) container_of(_rgate, struct stm32_rgate, gate)
 803
 804 static inline void disable_power_domain_write_protection(void)
 805 {
 806         if (pdrm)
 807                 regmap_update_bits(pdrm, 0x00, (1 << 8), (1 << 8));
 808 }
 809
 810 static inline void enable_power_domain_write_protection(void)
 811 {
 812         if (pdrm)
 813                 regmap_update_bits(pdrm, 0x00, (1 << 8), (0 << 8));
 814 }
 815
 816 static inline void sofware_reset_backup_domain(void)
 817 {
 818         unsigned long val;
 819
 820         val = readl(base + STM32F4_RCC_BDCR);
 821         writel(val | BIT(16), base + STM32F4_RCC_BDCR);
 822         writel(val & ~BIT(16), base + STM32F4_RCC_BDCR);
 823 }
 824
 825 struct stm32_rgate {
 826         struct  clk_gate gate;
 827         u8      bit_rdy_idx;
 828 };
 829
 830 #define RTC_TIMEOUT 1000000
 831
 832 static int rgclk_enable(struct clk_hw *hw)
 833 {
 834         struct clk_gate *gate = to_clk_gate(hw);
 835         struct stm32_rgate *rgate = to_rgclk(gate);
 836         u32 reg;
 837         int ret;
 838
 839         disable_power_domain_write_protection();
 840
 841         clk_gate_ops.enable(hw);
 842
 843         ret = readl_relaxed_poll_timeout_atomic(gate->reg, reg,
 844                         reg & rgate->bit_rdy_idx, 1000, RTC_TIMEOUT);
 845
 846         enable_power_domain_write_protection();
 847         return ret;
 848 }
 849
 850 static void rgclk_disable(struct clk_hw *hw)
 851 {
 852         clk_gate_ops.disable(hw);
 853 }
 854
 855 static int rgclk_is_enabled(struct clk_hw *hw)
 856 {
 857         return clk_gate_ops.is_enabled(hw);
 858 }
 859
 860 static const struct clk_ops rgclk_ops = {
 861         .enable = rgclk_enable,
 862         .disable = rgclk_disable,
 863         .is_enabled = rgclk_is_enabled,
 864 };
 865
 866 static struct clk_hw *clk_register_rgate(struct device *dev, const char *name,
 867                 const char *parent_name, unsigned long flags,
 868                 void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx,
 869                 u8 clk_gate_flags, spinlock_t *lock)
 870 {
 871         struct stm32_rgate *rgate;
 872         struct clk_init_data init = { NULL };
 873         struct clk_hw *hw;
 874         int ret;
 875
 876         rgate = kzalloc(sizeof(*rgate), GFP_KERNEL);
 877         if (!rgate)
 878                 return ERR_PTR(-ENOMEM);
 879
 880         init.name = name;
 881         init.ops = &rgclk_ops;
 882         init.flags = flags;
 883         init.parent_names = &parent_name;
 884         init.num_parents = 1;
 885
 886         rgate->bit_rdy_idx = bit_rdy_idx;
 887
 888         rgate->gate.lock = lock;
 889         rgate->gate.reg = reg;
 890         rgate->gate.bit_idx = bit_idx;
 891         rgate->gate.hw.init = &init;
 892
 893         hw = &rgate->gate.hw;
 894         ret = clk_hw_register(dev, hw);
 895         if (ret) {
 896                 kfree(rgate);
 897                 hw = ERR_PTR(ret);
 898         }
 899
 900         return hw;
 901 }
 902
 903 static int cclk_gate_enable(struct clk_hw *hw)
 904 {
 905         int ret;
 906
 907         disable_power_domain_write_protection();
 908
 909         ret = clk_gate_ops.enable(hw);
 910
 911         enable_power_domain_write_protection();
 912
 913         return ret;
 914 }
 915
 916 static void cclk_gate_disable(struct clk_hw *hw)
 917 {
 918         disable_power_domain_write_protection();
 919
 920         clk_gate_ops.disable(hw);
 921
 922         enable_power_domain_write_protection();
 923 }
 924
 925 static int cclk_gate_is_enabled(struct clk_hw *hw)
 926 {
 927         return clk_gate_ops.is_enabled(hw);
 928 }
 929
 930 static const struct clk_ops cclk_gate_ops = {
 931         .enable         = cclk_gate_enable,
 932         .disable        = cclk_gate_disable,
 933         .is_enabled     = cclk_gate_is_enabled,
 934 };
 935
 936 static u8 cclk_mux_get_parent(struct clk_hw *hw)
 937 {
 938         return clk_mux_ops.get_parent(hw);
 939 }
 940
 941 static int cclk_mux_set_parent(struct clk_hw *hw, u8 index)
 942 {
 943         int ret;
 944
 945         disable_power_domain_write_protection();
 946
 947         sofware_reset_backup_domain();
 948
 949         ret = clk_mux_ops.set_parent(hw, index);
 950
 951         enable_power_domain_write_protection();
 952
 953         return ret;
 954 }
 955
 956 static const struct clk_ops cclk_mux_ops = {
 957         .get_parent = cclk_mux_get_parent,
 958         .set_parent = cclk_mux_set_parent,
 959 };
 960
 961 static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
 962                 const char * const *parent_names, int num_parents,
 963                 void __iomem *reg, u8 bit_idx, u8 shift, unsigned long flags,
 964                 spinlock_t *lock)
 965 {
 966         struct clk_hw *hw;
 967         struct clk_gate *gate;
 968         struct clk_mux *mux;
 969
 970         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 971         if (!gate) {
 972                 hw = ERR_PTR(-EINVAL);
 973                 goto fail;
 974         }
 975
 976         mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 977         if (!mux) {
 978                 kfree(gate);
 979                 hw = ERR_PTR(-EINVAL);
 980                 goto fail;
 981         }
 982
 983         gate->reg = reg;
 984         gate->bit_idx = bit_idx;
 985         gate->flags = 0;
 986         gate->lock = lock;
 987
 988         mux->reg = reg;
 989         mux->shift = shift;
 990         mux->mask = 3;
 991         mux->flags = 0;
 992
 993         hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
 994                         &mux->hw, &cclk_mux_ops,
 995                         NULL, NULL,
 996                         &gate->hw, &cclk_gate_ops,
 997                         flags);
 998
 999         if (IS_ERR(hw)) {
1000                 kfree(gate);
1001                 kfree(mux);
1002         }
1003
1004 fail:
1005         return hw;
1006 }
1007
1008 static const char *sys_parents[] __initdata =   { "hsi", NULL, "pll" };
1009
1010 static const struct clk_div_table ahb_div_table[] = {
1011         { 0x0,   1 }, { 0x1,   1 }, { 0x2,   1 }, { 0x3,   1 },
1012         { 0x4,   1 }, { 0x5,   1 }, { 0x6,   1 }, { 0x7,   1 },
1013         { 0x8,   2 }, { 0x9,   4 }, { 0xa,   8 }, { 0xb,  16 },
1014         { 0xc,  64 }, { 0xd, 128 }, { 0xe, 256 }, { 0xf, 512 },
1015         { 0 },
1016 };
1017
1018 static const struct clk_div_table apb_div_table[] = {
1019         { 0,  1 }, { 0,  1 }, { 0,  1 }, { 0,  1 },
1020         { 4,  2 }, { 5,  4 }, { 6,  8 }, { 7, 16 },
1021         { 0 },
1022 };
1023
1024 static const char *rtc_parents[4] = {
1025         "no-clock", "lse", "lsi", "hse-rtc"
1026 };
1027
1028 static const char *lcd_parent[1] = { "pllsai-r-div" };
1029
1030 static const char *i2s_parents[2] = { "plli2s-r", NULL };
1031
1032 static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL,
1033         "no-clock" };
1034
1035 static const char *pll48_parents[2] = { "pll-q", "pllsai-p" };
1036
1037 static const char *sdmux_parents[2] = { "pll48", "sys" };
1038
1039 static const char *hdmi_parents[2] = { "lse", "hsi_div488" };
1040
1041 static const char *spdif_parent[1] = { "plli2s-p" };
1042
1043 static const char *lptim_parent[4] = { "apb1_mul", "lsi", "hsi", "lse" };
1044
1045 static const char *uart_parents1[4] = { "apb2_div", "sys", "hsi", "lse" };
1046 static const char *uart_parents2[4] = { "apb1_div", "sys", "hsi", "lse" };
1047
1048 static const char *i2c_parents[4] = { "apb1_div", "sys", "hsi", "no-clock" };
1049
1050 struct stm32_aux_clk {
1051         int idx;
1052         const char *name;
1053         const char * const *parent_names;
1054         int num_parents;
1055         int offset_mux;
1056         u8 shift;
1057         u8 mask;
1058         int offset_gate;
1059         u8 bit_idx;
1060         unsigned long flags;
1061 };
1062
1063 struct stm32f4_clk_data {
1064         const struct stm32f4_gate_data *gates_data;
1065         const u64 *gates_map;
1066         int gates_num;
1067         const struct stm32f4_pll_data *pll_data;
1068         const struct stm32_aux_clk *aux_clk;
1069         int aux_clk_num;
1070         int end_primary;
1071 };
1072
1073 static const struct stm32_aux_clk stm32f429_aux_clk[] = {
1074         {
1075                 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1076                 NO_MUX, 0, 0,
1077                 STM32F4_RCC_APB2ENR, 26,
1078                 CLK_SET_RATE_PARENT
1079         },
1080         {
1081                 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1082                 STM32F4_RCC_CFGR, 23, 1,
1083                 NO_GATE, 0,
1084                 CLK_SET_RATE_PARENT
1085         },
1086         {
1087                 CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
1088                 STM32F4_RCC_DCKCFGR, 20, 3,
1089                 STM32F4_RCC_APB2ENR, 22,
1090                 CLK_SET_RATE_PARENT
1091         },
1092         {
1093                 CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1094                 STM32F4_RCC_DCKCFGR, 22, 3,
1095                 STM32F4_RCC_APB2ENR, 22,
1096                 CLK_SET_RATE_PARENT
1097         },
1098 };
1099
1100 static const struct stm32_aux_clk stm32f469_aux_clk[] = {
1101         {
1102                 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1103                 NO_MUX, 0, 0,
1104                 STM32F4_RCC_APB2ENR, 26,
1105                 CLK_SET_RATE_PARENT
1106         },
1107         {
1108                 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1109                 STM32F4_RCC_CFGR, 23, 1,
1110                 NO_GATE, 0,
1111                 CLK_SET_RATE_PARENT
1112         },
1113         {
1114                 CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
1115                 STM32F4_RCC_DCKCFGR, 20, 3,
1116                 STM32F4_RCC_APB2ENR, 22,
1117                 CLK_SET_RATE_PARENT
1118         },
1119         {
1120                 CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1121                 STM32F4_RCC_DCKCFGR, 22, 3,
1122                 STM32F4_RCC_APB2ENR, 22,
1123                 CLK_SET_RATE_PARENT
1124         },
1125         {
1126                 NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
1127                 STM32F4_RCC_DCKCFGR, 27, 1,
1128                 NO_GATE, 0,
1129                 0
1130         },
1131         {
1132                 NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1133                 STM32F4_RCC_DCKCFGR, 28, 1,
1134                 NO_GATE, 0,
1135                 0
1136         },
1137 };
1138
1139 static const struct stm32_aux_clk stm32f746_aux_clk[] = {
1140         {
1141                 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1142                 NO_MUX, 0, 0,
1143                 STM32F4_RCC_APB2ENR, 26,
1144                 CLK_SET_RATE_PARENT
1145         },
1146         {
1147                 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1148                 STM32F4_RCC_CFGR, 23, 1,
1149                 NO_GATE, 0,
1150                 CLK_SET_RATE_PARENT
1151         },
1152         {
1153                 CLK_SAI1, "sai1_clk", sai_parents, ARRAY_SIZE(sai_parents),
1154                 STM32F4_RCC_DCKCFGR, 20, 3,
1155                 STM32F4_RCC_APB2ENR, 22,
1156                 CLK_SET_RATE_PARENT
1157         },
1158         {
1159                 CLK_SAI2, "sai2_clk", sai_parents, ARRAY_SIZE(sai_parents),
1160                 STM32F4_RCC_DCKCFGR, 22, 3,
1161                 STM32F4_RCC_APB2ENR, 23,
1162                 CLK_SET_RATE_PARENT
1163         },
1164         {
1165                 NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
1166                 STM32F7_RCC_DCKCFGR2, 27, 1,
1167                 NO_GATE, 0,
1168                 0
1169         },
1170         {
1171                 NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1172                 STM32F7_RCC_DCKCFGR2, 28, 1,
1173                 NO_GATE, 0,
1174                 0
1175         },
1176         {
1177                 CLK_HDMI_CEC, "hdmi-cec",
1178                 hdmi_parents, ARRAY_SIZE(hdmi_parents),
1179                 STM32F7_RCC_DCKCFGR2, 26, 1,
1180                 NO_GATE, 0,
1181                 0
1182         },
1183         {
1184                 CLK_SPDIF, "spdif-rx",
1185                 spdif_parent, ARRAY_SIZE(spdif_parent),
1186                 STM32F7_RCC_DCKCFGR2, 22, 3,
1187                 STM32F4_RCC_APB2ENR, 23,
1188                 CLK_SET_RATE_PARENT
1189         },
1190         {
1191                 CLK_USART1, "usart1",
1192                 uart_parents1, ARRAY_SIZE(uart_parents1),
1193                 STM32F7_RCC_DCKCFGR2, 0, 3,
1194                 STM32F4_RCC_APB2ENR, 4,
1195                 CLK_SET_RATE_PARENT,
1196         },
1197         {
1198                 CLK_USART2, "usart2",
1199                 uart_parents2, ARRAY_SIZE(uart_parents1),
1200                 STM32F7_RCC_DCKCFGR2, 2, 3,
1201                 STM32F4_RCC_APB1ENR, 17,
1202                 CLK_SET_RATE_PARENT,
1203         },
1204         {
1205                 CLK_USART3, "usart3",
1206                 uart_parents2, ARRAY_SIZE(uart_parents1),
1207                 STM32F7_RCC_DCKCFGR2, 4, 3,
1208                 STM32F4_RCC_APB1ENR, 18,
1209                 CLK_SET_RATE_PARENT,
1210         },
1211         {
1212                 CLK_UART4, "uart4",
1213                 uart_parents2, ARRAY_SIZE(uart_parents1),
1214                 STM32F7_RCC_DCKCFGR2, 6, 3,
1215                 STM32F4_RCC_APB1ENR, 19,
1216                 CLK_SET_RATE_PARENT,
1217         },
1218         {
1219                 CLK_UART5, "uart5",
1220                 uart_parents2, ARRAY_SIZE(uart_parents1),
1221                 STM32F7_RCC_DCKCFGR2, 8, 3,
1222                 STM32F4_RCC_APB1ENR, 20,
1223                 CLK_SET_RATE_PARENT,
1224         },
1225         {
1226                 CLK_USART6, "usart6",
1227                 uart_parents1, ARRAY_SIZE(uart_parents1),
1228                 STM32F7_RCC_DCKCFGR2, 10, 3,
1229                 STM32F4_RCC_APB2ENR, 5,
1230                 CLK_SET_RATE_PARENT,
1231         },
1232
1233         {
1234                 CLK_UART7, "uart7",
1235                 uart_parents2, ARRAY_SIZE(uart_parents1),
1236                 STM32F7_RCC_DCKCFGR2, 12, 3,
1237                 STM32F4_RCC_APB1ENR, 30,
1238                 CLK_SET_RATE_PARENT,
1239         },
1240         {
1241                 CLK_UART8, "uart8",
1242                 uart_parents2, ARRAY_SIZE(uart_parents1),
1243                 STM32F7_RCC_DCKCFGR2, 14, 3,
1244                 STM32F4_RCC_APB1ENR, 31,
1245                 CLK_SET_RATE_PARENT,
1246         },
1247         {
1248                 CLK_I2C1, "i2c1",
1249                 i2c_parents, ARRAY_SIZE(i2c_parents),
1250                 STM32F7_RCC_DCKCFGR2, 16, 3,
1251                 STM32F4_RCC_APB1ENR, 21,
1252                 CLK_SET_RATE_PARENT,
1253         },
1254         {
1255                 CLK_I2C2, "i2c2",
1256                 i2c_parents, ARRAY_SIZE(i2c_parents),
1257                 STM32F7_RCC_DCKCFGR2, 18, 3,
1258                 STM32F4_RCC_APB1ENR, 22,
1259                 CLK_SET_RATE_PARENT,
1260         },
1261         {
1262                 CLK_I2C3, "i2c3",
1263                 i2c_parents, ARRAY_SIZE(i2c_parents),
1264                 STM32F7_RCC_DCKCFGR2, 20, 3,
1265                 STM32F4_RCC_APB1ENR, 23,
1266                 CLK_SET_RATE_PARENT,
1267         },
1268         {
1269                 CLK_I2C4, "i2c4",
1270                 i2c_parents, ARRAY_SIZE(i2c_parents),
1271                 STM32F7_RCC_DCKCFGR2, 22, 3,
1272                 STM32F4_RCC_APB1ENR, 24,
1273                 CLK_SET_RATE_PARENT,
1274         },
1275
1276         {
1277                 CLK_LPTIMER, "lptim1",
1278                 lptim_parent, ARRAY_SIZE(lptim_parent),
1279                 STM32F7_RCC_DCKCFGR2, 24, 3,
1280                 STM32F4_RCC_APB1ENR, 9,
1281                 CLK_SET_RATE_PARENT
1282         },
1283 };
1284
1285 static const struct stm32f4_clk_data stm32f429_clk_data = {
1286         .end_primary    = END_PRIMARY_CLK,
1287         .gates_data     = stm32f429_gates,
1288         .gates_map      = stm32f42xx_gate_map,
1289         .gates_num      = ARRAY_SIZE(stm32f429_gates),
1290         .pll_data       = stm32f429_pll,
1291         .aux_clk        = stm32f429_aux_clk,
1292         .aux_clk_num    = ARRAY_SIZE(stm32f429_aux_clk),
1293 };
1294
1295 static const struct stm32f4_clk_data stm32f469_clk_data = {
1296         .end_primary    = END_PRIMARY_CLK,
1297         .gates_data     = stm32f469_gates,
1298         .gates_map      = stm32f46xx_gate_map,
1299         .gates_num      = ARRAY_SIZE(stm32f469_gates),
1300         .pll_data       = stm32f469_pll,
1301         .aux_clk        = stm32f469_aux_clk,
1302         .aux_clk_num    = ARRAY_SIZE(stm32f469_aux_clk),
1303 };
1304
1305 static const struct stm32f4_clk_data stm32f746_clk_data = {
1306         .end_primary    = END_PRIMARY_CLK_F7,
1307         .gates_data     = stm32f746_gates,
1308         .gates_map      = stm32f746_gate_map,
1309         .gates_num      = ARRAY_SIZE(stm32f746_gates),
1310         .pll_data       = stm32f469_pll,
1311         .aux_clk        = stm32f746_aux_clk,
1312         .aux_clk_num    = ARRAY_SIZE(stm32f746_aux_clk),
1313 };
1314
1315 static const struct of_device_id stm32f4_of_match[] = {
1316         {
1317                 .compatible = "st,stm32f42xx-rcc",
1318                 .data = &stm32f429_clk_data
1319         },
1320         {
1321                 .compatible = "st,stm32f469-rcc",
1322                 .data = &stm32f469_clk_data
1323         },
1324         {
1325                 .compatible = "st,stm32f746-rcc",
1326                 .data = &stm32f746_clk_data
1327         },
1328         {}
1329 };
1330
1331 static struct clk_hw *stm32_register_aux_clk(const char *name,
1332                 const char * const *parent_names, int num_parents,
1333                 int offset_mux, u8 shift, u8 mask,
1334                 int offset_gate, u8 bit_idx,
1335                 unsigned long flags, spinlock_t *lock)
1336 {
1337         struct clk_hw *hw;
1338         struct clk_gate *gate = NULL;
1339         struct clk_mux *mux = NULL;
1340         struct clk_hw *mux_hw = NULL, *gate_hw = NULL;
1341         const struct clk_ops *mux_ops = NULL, *gate_ops = NULL;
1342
1343         if (offset_gate != NO_GATE) {
1344                 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1345                 if (!gate) {
1346                         hw = ERR_PTR(-EINVAL);
1347                         goto fail;
1348                 }
1349
1350                 gate->reg = base + offset_gate;
1351                 gate->bit_idx = bit_idx;
1352                 gate->flags = 0;
1353                 gate->lock = lock;
1354                 gate_hw = &gate->hw;
1355                 gate_ops = &clk_gate_ops;
1356         }
1357
1358         if (offset_mux != NO_MUX) {
1359                 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
1360                 if (!mux) {
1361                         hw = ERR_PTR(-EINVAL);
1362                         goto fail;
1363                 }
1364
1365                 mux->reg = base + offset_mux;
1366                 mux->shift = shift;
1367                 mux->mask = mask;
1368                 mux->flags = 0;
1369                 mux_hw = &mux->hw;
1370                 mux_ops = &clk_mux_ops;
1371         }
1372
1373         if (mux_hw == NULL && gate_hw == NULL) {
1374                 hw = ERR_PTR(-EINVAL);
1375                 goto fail;
1376         }
1377
1378         hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
1379                         mux_hw, mux_ops,
1380                         NULL, NULL,
1381                         gate_hw, gate_ops,
1382                         flags);
1383
1384 fail:
1385         if (IS_ERR(hw)) {
1386                 kfree(gate);
1387                 kfree(mux);
1388         }
1389
1390         return hw;
1391 }
1392
1393 static void __init stm32f4_rcc_init(struct device_node *np)
1394 {
1395         const char *hse_clk, *i2s_in_clk;
1396         int n;
1397         const struct of_device_id *match;
1398         const struct stm32f4_clk_data *data;
1399         unsigned long pllcfgr;
1400         const char *pllsrc;
1401         unsigned long pllm;
1402
1403         base = of_iomap(np, 0);
1404         if (!base) {
1405                 pr_err("%s: unable to map resource", np->name);
1406                 return;
1407         }
1408
1409         pdrm = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1410         if (IS_ERR(pdrm)) {
1411                 pdrm = NULL;
1412                 pr_warn("%s: Unable to get syscfg\n", __func__);
1413         }
1414
1415         match = of_match_node(stm32f4_of_match, np);
1416         if (WARN_ON(!match))
1417                 return;
1418
1419         data = match->data;
1420
1421         stm32fx_end_primary_clk = data->end_primary;
1422
1423         clks = kmalloc_array(data->gates_num + stm32fx_end_primary_clk,
1424                         sizeof(*clks), GFP_KERNEL);
1425         if (!clks)
1426                 goto fail;
1427
1428         stm32f4_gate_map = data->gates_map;
1429
1430         hse_clk = of_clk_get_parent_name(np, 0);
1431
1432         i2s_in_clk = of_clk_get_parent_name(np, 1);
1433
1434         i2s_parents[1] = i2s_in_clk;
1435         sai_parents[2] = i2s_in_clk;
1436
1437         clks[CLK_HSI] = clk_hw_register_fixed_rate_with_accuracy(NULL, "hsi",
1438                         NULL, 0, 16000000, 160000);
1439
1440         pllcfgr = readl(base + STM32F4_RCC_PLLCFGR);
1441         pllsrc = pllcfgr & BIT(22) ? hse_clk : "hsi";
1442         pllm = pllcfgr & 0x3f;
1443
1444         clk_hw_register_fixed_factor(NULL, "vco_in", pllsrc,
1445                                                0, 1, pllm);
1446
1447         stm32f4_rcc_register_pll("vco_in", &data->pll_data[0],
1448                         &stm32f4_clk_lock);
1449
1450         clks[PLL_VCO_I2S] = stm32f4_rcc_register_pll("vco_in",
1451                         &data->pll_data[1], &stm32f4_clk_lock);
1452
1453         clks[PLL_VCO_SAI] = stm32f4_rcc_register_pll("vco_in",
1454                         &data->pll_data[2], &stm32f4_clk_lock);
1455
1456         for (n = 0; n < MAX_POST_DIV; n++) {
1457                 const struct stm32f4_pll_post_div_data *post_div;
1458                 struct clk_hw *hw;
1459
1460                 post_div = &post_div_data[n];
1461
1462                 hw = clk_register_pll_div(post_div->name,
1463                                 post_div->parent,
1464                                 post_div->flag,
1465                                 base + post_div->offset,
1466                                 post_div->shift,
1467                                 post_div->width,
1468                                 post_div->flag_div,
1469                                 post_div->div_table,
1470                                 clks[post_div->pll_num],
1471                                 &stm32f4_clk_lock);
1472
1473                 if (post_div->idx != NO_IDX)
1474                         clks[post_div->idx] = hw;
1475         }
1476
1477         sys_parents[1] = hse_clk;
1478
1479         clks[CLK_SYSCLK] = clk_hw_register_mux_table(
1480             NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0,
1481             base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock);
1482
1483         clk_register_divider_table(NULL, "ahb_div", "sys",
1484                                    CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1485                                    4, 4, 0, ahb_div_table, &stm32f4_clk_lock);
1486
1487         clk_register_divider_table(NULL, "apb1_div", "ahb_div",
1488                                    CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1489                                    10, 3, 0, apb_div_table, &stm32f4_clk_lock);
1490         clk_register_apb_mul(NULL, "apb1_mul", "apb1_div",
1491                              CLK_SET_RATE_PARENT, 12);
1492
1493         clk_register_divider_table(NULL, "apb2_div", "ahb_div",
1494                                    CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1495                                    13, 3, 0, apb_div_table, &stm32f4_clk_lock);
1496         clk_register_apb_mul(NULL, "apb2_mul", "apb2_div",
1497                              CLK_SET_RATE_PARENT, 15);
1498
1499         clks[SYSTICK] = clk_hw_register_fixed_factor(NULL, "systick", "ahb_div",
1500                                                   0, 1, 8);
1501         clks[FCLK] = clk_hw_register_fixed_factor(NULL, "fclk", "ahb_div",
1502                                                0, 1, 1);
1503
1504         for (n = 0; n < data->gates_num; n++) {
1505                 const struct stm32f4_gate_data *gd;
1506                 unsigned int secondary;
1507                 int idx;
1508
1509                 gd = &data->gates_data[n];
1510                 secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) +
1511                         gd->bit_idx;
1512                 idx = stm32f4_rcc_lookup_clk_idx(0, secondary);
1513
1514                 if (idx < 0)
1515                         goto fail;
1516
1517                 clks[idx] = clk_hw_register_gate(
1518                     NULL, gd->name, gd->parent_name, gd->flags,
1519                     base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock);
1520
1521                 if (IS_ERR(clks[idx])) {
1522                         pr_err("%s: Unable to register leaf clock %s\n",
1523                                np->full_name, gd->name);
1524                         goto fail;
1525                 }
1526         }
1527
1528         clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0,
1529                         base + STM32F4_RCC_CSR, 0, 2, 0, &stm32f4_clk_lock);
1530
1531         if (IS_ERR(clks[CLK_LSI])) {
1532                 pr_err("Unable to register lsi clock\n");
1533                 goto fail;
1534         }
1535
1536         clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0,
1537                         base + STM32F4_RCC_BDCR, 0, 2, 0, &stm32f4_clk_lock);
1538
1539         if (IS_ERR(clks[CLK_LSE])) {
1540                 pr_err("Unable to register lse clock\n");
1541                 goto fail;
1542         }
1543
1544         clks[CLK_HSE_RTC] = clk_hw_register_divider(NULL, "hse-rtc", "clk-hse",
1545                         0, base + STM32F4_RCC_CFGR, 16, 5, 0,
1546                         &stm32f4_clk_lock);
1547
1548         if (IS_ERR(clks[CLK_HSE_RTC])) {
1549                 pr_err("Unable to register hse-rtc clock\n");
1550                 goto fail;
1551         }
1552
1553         clks[CLK_RTC] = stm32_register_cclk(NULL, "rtc", rtc_parents, 4,
1554                         base + STM32F4_RCC_BDCR, 15, 8, 0, &stm32f4_clk_lock);
1555
1556         if (IS_ERR(clks[CLK_RTC])) {
1557                 pr_err("Unable to register rtc clock\n");
1558                 goto fail;
1559         }
1560
1561         for (n = 0; n < data->aux_clk_num; n++) {
1562                 const struct stm32_aux_clk *aux_clk;
1563                 struct clk_hw *hw;
1564
1565                 aux_clk = &data->aux_clk[n];
1566
1567                 hw = stm32_register_aux_clk(aux_clk->name,
1568                                 aux_clk->parent_names, aux_clk->num_parents,
1569                                 aux_clk->offset_mux, aux_clk->shift,
1570                                 aux_clk->mask, aux_clk->offset_gate,
1571                                 aux_clk->bit_idx, aux_clk->flags,
1572                                 &stm32f4_clk_lock);
1573
1574                 if (IS_ERR(hw)) {
1575                         pr_warn("Unable to register %s clk\n", aux_clk->name);
1576                         continue;
1577                 }
1578
1579                 if (aux_clk->idx != NO_IDX)
1580                         clks[aux_clk->idx] = hw;
1581         }
1582
1583         if (of_device_is_compatible(np, "st,stm32f746-rcc"))
1584
1585                 clk_hw_register_fixed_factor(NULL, "hsi_div488", "hsi", 0,
1586                                 1, 488);
1587
1588         of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
1589         return;
1590 fail:
1591         kfree(clks);
1592         iounmap(base);
1593 }
1594 CLK_OF_DECLARE_DRIVER(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
1595 CLK_OF_DECLARE_DRIVER(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init);
1596 CLK_OF_DECLARE_DRIVER(stm32f746_rcc, "st,stm32f746-rcc", stm32f4_rcc_init);