2 * Clock implementation for VIA/Wondermedia SoC's
3 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
18 #include <linux/of_address.h>
19 #include <linux/slab.h>
20 #include <linux/bitops.h>
21 #include <linux/clkdev.h>
22 #include <linux/clk-provider.h>
24 #define LEGACY_PMC_BASE 0xD8130000
26 /* All clocks share the same lock as none can be changed concurrently */
27 static DEFINE_SPINLOCK(_lock);
31 void __iomem *div_reg;
32 unsigned int div_mask;
39 * Add new PLL_TYPE_x definitions here as required. Use the first known model
40 * to support the new type as the name.
41 * Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and
42 * vtwm_pll_set_rate() to handle the new PLL_TYPE_x
45 #define PLL_TYPE_VT8500 0
46 #define PLL_TYPE_WM8650 1
47 #define PLL_TYPE_WM8750 2
48 #define PLL_TYPE_WM8850 3
57 static void __iomem *pmc_base;
59 static __init void vtwm_set_pmc_base(void)
61 struct device_node *np =
62 of_find_compatible_node(NULL, NULL, "via,vt8500-pmc");
65 pmc_base = of_iomap(np, 0);
67 pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
71 pr_err("%s:of_iomap(pmc) failed\n", __func__);
74 #define to_clk_device(_hw) container_of(_hw, struct clk_device, hw)
76 #define VT8500_PMC_BUSY_MASK 0x18
78 static void vt8500_pmc_wait_busy(void)
80 while (readl(pmc_base) & VT8500_PMC_BUSY_MASK)
84 static int vt8500_dclk_enable(struct clk_hw *hw)
86 struct clk_device *cdev = to_clk_device(hw);
88 unsigned long flags = 0;
90 spin_lock_irqsave(cdev->lock, flags);
92 en_val = readl(cdev->en_reg);
93 en_val |= BIT(cdev->en_bit);
94 writel(en_val, cdev->en_reg);
96 spin_unlock_irqrestore(cdev->lock, flags);
100 static void vt8500_dclk_disable(struct clk_hw *hw)
102 struct clk_device *cdev = to_clk_device(hw);
104 unsigned long flags = 0;
106 spin_lock_irqsave(cdev->lock, flags);
108 en_val = readl(cdev->en_reg);
109 en_val &= ~BIT(cdev->en_bit);
110 writel(en_val, cdev->en_reg);
112 spin_unlock_irqrestore(cdev->lock, flags);
115 static int vt8500_dclk_is_enabled(struct clk_hw *hw)
117 struct clk_device *cdev = to_clk_device(hw);
118 u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit));
120 return en_val ? 1 : 0;
123 static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
124 unsigned long parent_rate)
126 struct clk_device *cdev = to_clk_device(hw);
127 u32 div = readl(cdev->div_reg) & cdev->div_mask;
129 /* Special case for SDMMC devices */
130 if ((cdev->div_mask == 0x3F) && (div & BIT(5)))
131 div = 64 * (div & 0x1f);
133 /* div == 0 is actually the highest divisor */
135 div = (cdev->div_mask + 1);
137 return parent_rate / div;
140 static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
141 unsigned long *prate)
143 struct clk_device *cdev = to_clk_device(hw);
149 divisor = *prate / rate;
151 /* If prate / rate would be decimal, incr the divisor */
152 if (rate * divisor < *prate)
156 * If this is a request for SDMMC we have to adjust the divisor
157 * when >31 to use the fixed predivisor
159 if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
160 divisor = 64 * ((divisor / 64) + 1);
163 return *prate / divisor;
166 static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
167 unsigned long parent_rate)
169 struct clk_device *cdev = to_clk_device(hw);
171 unsigned long flags = 0;
176 divisor = parent_rate / rate;
178 if (divisor == cdev->div_mask + 1)
181 /* SDMMC mask may need to be corrected before testing if its valid */
182 if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
184 * Bit 5 is a fixed /64 predivisor. If the requested divisor
185 * is >31 then correct for the fixed divisor being required.
187 divisor = 0x20 + (divisor / 64);
190 if (divisor > cdev->div_mask) {
191 pr_err("%s: invalid divisor for clock\n", __func__);
195 spin_lock_irqsave(cdev->lock, flags);
197 vt8500_pmc_wait_busy();
198 writel(divisor, cdev->div_reg);
199 vt8500_pmc_wait_busy();
201 spin_unlock_irqrestore(cdev->lock, flags);
207 static const struct clk_ops vt8500_gated_clk_ops = {
208 .enable = vt8500_dclk_enable,
209 .disable = vt8500_dclk_disable,
210 .is_enabled = vt8500_dclk_is_enabled,
213 static const struct clk_ops vt8500_divisor_clk_ops = {
214 .round_rate = vt8500_dclk_round_rate,
215 .set_rate = vt8500_dclk_set_rate,
216 .recalc_rate = vt8500_dclk_recalc_rate,
219 static const struct clk_ops vt8500_gated_divisor_clk_ops = {
220 .enable = vt8500_dclk_enable,
221 .disable = vt8500_dclk_disable,
222 .is_enabled = vt8500_dclk_is_enabled,
223 .round_rate = vt8500_dclk_round_rate,
224 .set_rate = vt8500_dclk_set_rate,
225 .recalc_rate = vt8500_dclk_recalc_rate,
228 #define CLK_INIT_GATED BIT(0)
229 #define CLK_INIT_DIVISOR BIT(1)
230 #define CLK_INIT_GATED_DIVISOR (CLK_INIT_DIVISOR | CLK_INIT_GATED)
232 static __init void vtwm_device_clk_init(struct device_node *node)
236 struct clk_device *dev_clk;
237 const char *clk_name = node->name;
238 const char *parent_name;
239 struct clk_init_data init;
241 int clk_init_flags = 0;
246 dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL);
247 if (WARN_ON(!dev_clk))
250 dev_clk->lock = &_lock;
252 rc = of_property_read_u32(node, "enable-reg", &en_reg);
254 dev_clk->en_reg = pmc_base + en_reg;
255 rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit);
257 pr_err("%s: enable-bit property required for gated clock\n",
261 clk_init_flags |= CLK_INIT_GATED;
264 rc = of_property_read_u32(node, "divisor-reg", &div_reg);
266 dev_clk->div_reg = pmc_base + div_reg;
268 * use 0x1f as the default mask since it covers
269 * almost all the clocks and reduces dts properties
271 dev_clk->div_mask = 0x1f;
273 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);
274 clk_init_flags |= CLK_INIT_DIVISOR;
277 of_property_read_string(node, "clock-output-names", &clk_name);
279 switch (clk_init_flags) {
281 init.ops = &vt8500_gated_clk_ops;
283 case CLK_INIT_DIVISOR:
284 init.ops = &vt8500_divisor_clk_ops;
286 case CLK_INIT_GATED_DIVISOR:
287 init.ops = &vt8500_gated_divisor_clk_ops;
290 pr_err("%s: Invalid clock description in device tree\n",
296 init.name = clk_name;
298 parent_name = of_clk_get_parent_name(node, 0);
299 init.parent_names = &parent_name;
300 init.num_parents = 1;
302 dev_clk->hw.init = &init;
304 clk = clk_register(NULL, &dev_clk->hw);
305 if (WARN_ON(IS_ERR(clk))) {
309 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
310 clk_register_clkdev(clk, clk_name, NULL);
312 CLK_OF_DECLARE(vt8500_device, "via,vt8500-device-clock", vtwm_device_clk_init);
314 /* PLL clock related functions */
316 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
318 /* Helper macros for PLL_VT8500 */
319 #define VT8500_PLL_MUL(x) ((x & 0x1F) << 1)
320 #define VT8500_PLL_DIV(x) ((x & 0x100) ? 1 : 2)
322 #define VT8500_BITS_TO_FREQ(r, m, d) \
325 #define VT8500_BITS_TO_VAL(m, d) \
326 ((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F))
328 /* Helper macros for PLL_WM8650 */
329 #define WM8650_PLL_MUL(x) (x & 0x3FF)
330 #define WM8650_PLL_DIV(x) (((x >> 10) & 7) * (1 << ((x >> 13) & 3)))
332 #define WM8650_BITS_TO_FREQ(r, m, d1, d2) \
333 (r * m / (d1 * (1 << d2)))
335 #define WM8650_BITS_TO_VAL(m, d1, d2) \
336 ((d2 << 13) | (d1 << 10) | (m & 0x3FF))
338 /* Helper macros for PLL_WM8750 */
339 #define WM8750_PLL_MUL(x) (((x >> 16) & 0xFF) + 1)
340 #define WM8750_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 7)))
342 #define WM8750_BITS_TO_FREQ(r, m, d1, d2) \
343 (r * (m+1) / ((d1+1) * (1 << d2)))
345 #define WM8750_BITS_TO_VAL(f, m, d1, d2) \
346 ((f << 24) | ((m - 1) << 16) | ((d1 - 1) << 8) | d2)
348 /* Helper macros for PLL_WM8850 */
349 #define WM8850_PLL_MUL(x) ((((x >> 16) & 0x7F) + 1) * 2)
350 #define WM8850_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 3)))
352 #define WM8850_BITS_TO_FREQ(r, m, d1, d2) \
353 (r * ((m + 1) * 2) / ((d1+1) * (1 << d2)))
355 #define WM8850_BITS_TO_VAL(m, d1, d2) \
356 ((((m / 2) - 1) << 16) | ((d1 - 1) << 8) | d2)
358 static int vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
359 u32 *multiplier, u32 *prediv)
364 if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) {
365 pr_err("%s: requested rate out of range\n", __func__);
370 if (rate <= parent_rate * 31)
371 /* use the prediv to double the resolution */
376 *multiplier = rate / (parent_rate / *prediv);
377 tclk = (parent_rate / *prediv) * *multiplier;
380 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__,
386 static int wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
387 u32 *multiplier, u32 *divisor1, u32 *divisor2)
391 u32 best_mul, best_div1, best_div2;
392 unsigned long tclk, rate_err, best_err;
394 best_err = (unsigned long)-1;
396 /* Find the closest match (lower or equal to requested) */
397 for (div1 = 5; div1 >= 3; div1--)
398 for (div2 = 3; div2 >= 0; div2--)
399 for (mul = 3; mul <= 1023; mul++) {
400 tclk = parent_rate * mul / (div1 * (1 << div2));
403 /* error will always be +ve */
404 rate_err = rate - tclk;
412 if (rate_err < best_err) {
420 if (best_err == (unsigned long)-1) {
421 pr_warn("%s: impossible rate %lu\n", __func__, rate);
425 /* if we got here, it wasn't an exact match */
426 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
428 *multiplier = best_mul;
429 *divisor1 = best_div1;
430 *divisor2 = best_div2;
435 static u32 wm8750_get_filter(u32 parent_rate, u32 divisor1)
437 /* calculate frequency (MHz) after pre-divisor */
438 u32 freq = (parent_rate / 1000000) / (divisor1 + 1);
440 if ((freq < 10) || (freq > 200))
441 pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n",
446 else if (freq >= 104)
462 static int wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
463 u32 *filter, u32 *multiplier, u32 *divisor1, u32 *divisor2)
467 u32 best_mul, best_div1, best_div2;
468 unsigned long tclk, rate_err, best_err;
470 best_err = (unsigned long)-1;
472 /* Find the closest match (lower or equal to requested) */
473 for (div1 = 1; div1 >= 0; div1--)
474 for (div2 = 7; div2 >= 0; div2--)
475 for (mul = 0; mul <= 255; mul++) {
476 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2));
479 /* error will always be +ve */
480 rate_err = rate - tclk;
482 *filter = wm8750_get_filter(parent_rate, div1);
489 if (rate_err < best_err) {
497 if (best_err == (unsigned long)-1) {
498 pr_warn("%s: impossible rate %lu\n", __func__, rate);
502 /* if we got here, it wasn't an exact match */
503 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
506 *filter = wm8750_get_filter(parent_rate, best_div1);
507 *multiplier = best_mul;
508 *divisor1 = best_div1;
509 *divisor2 = best_div2;
514 static int wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
515 u32 *multiplier, u32 *divisor1, u32 *divisor2)
519 u32 best_mul, best_div1, best_div2;
520 unsigned long tclk, rate_err, best_err;
522 best_err = (unsigned long)-1;
524 /* Find the closest match (lower or equal to requested) */
525 for (div1 = 1; div1 >= 0; div1--)
526 for (div2 = 3; div2 >= 0; div2--)
527 for (mul = 0; mul <= 127; mul++) {
528 tclk = parent_rate * ((mul + 1) * 2) /
529 ((div1 + 1) * (1 << div2));
532 /* error will always be +ve */
533 rate_err = rate - tclk;
541 if (rate_err < best_err) {
549 if (best_err == (unsigned long)-1) {
550 pr_warn("%s: impossible rate %lu\n", __func__, rate);
554 /* if we got here, it wasn't an exact match */
555 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
558 *multiplier = best_mul;
559 *divisor1 = best_div1;
560 *divisor2 = best_div2;
565 static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
566 unsigned long parent_rate)
568 struct clk_pll *pll = to_clk_pll(hw);
569 u32 filter, mul, div1, div2;
571 unsigned long flags = 0;
577 case PLL_TYPE_VT8500:
578 ret = vt8500_find_pll_bits(rate, parent_rate, &mul, &div1);
580 pll_val = VT8500_BITS_TO_VAL(mul, div1);
582 case PLL_TYPE_WM8650:
583 ret = wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
585 pll_val = WM8650_BITS_TO_VAL(mul, div1, div2);
587 case PLL_TYPE_WM8750:
588 ret = wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2);
590 pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2);
592 case PLL_TYPE_WM8850:
593 ret = wm8850_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
595 pll_val = WM8850_BITS_TO_VAL(mul, div1, div2);
598 pr_err("%s: invalid pll type\n", __func__);
605 spin_lock_irqsave(pll->lock, flags);
607 vt8500_pmc_wait_busy();
608 writel(pll_val, pll->reg);
609 vt8500_pmc_wait_busy();
611 spin_unlock_irqrestore(pll->lock, flags);
616 static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
617 unsigned long *prate)
619 struct clk_pll *pll = to_clk_pll(hw);
620 u32 filter, mul, div1, div2;
625 case PLL_TYPE_VT8500:
626 ret = vt8500_find_pll_bits(rate, *prate, &mul, &div1);
628 round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1);
630 case PLL_TYPE_WM8650:
631 ret = wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2);
633 round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2);
635 case PLL_TYPE_WM8750:
636 ret = wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2);
638 round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2);
640 case PLL_TYPE_WM8850:
641 ret = wm8850_find_pll_bits(rate, *prate, &mul, &div1, &div2);
643 round_rate = WM8850_BITS_TO_FREQ(*prate, mul, div1, div2);
655 static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
656 unsigned long parent_rate)
658 struct clk_pll *pll = to_clk_pll(hw);
659 u32 pll_val = readl(pll->reg);
660 unsigned long pll_freq;
663 case PLL_TYPE_VT8500:
664 pll_freq = parent_rate * VT8500_PLL_MUL(pll_val);
665 pll_freq /= VT8500_PLL_DIV(pll_val);
667 case PLL_TYPE_WM8650:
668 pll_freq = parent_rate * WM8650_PLL_MUL(pll_val);
669 pll_freq /= WM8650_PLL_DIV(pll_val);
671 case PLL_TYPE_WM8750:
672 pll_freq = parent_rate * WM8750_PLL_MUL(pll_val);
673 pll_freq /= WM8750_PLL_DIV(pll_val);
675 case PLL_TYPE_WM8850:
676 pll_freq = parent_rate * WM8850_PLL_MUL(pll_val);
677 pll_freq /= WM8850_PLL_DIV(pll_val);
686 static const struct clk_ops vtwm_pll_ops = {
687 .round_rate = vtwm_pll_round_rate,
688 .set_rate = vtwm_pll_set_rate,
689 .recalc_rate = vtwm_pll_recalc_rate,
692 static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type)
696 struct clk_pll *pll_clk;
697 const char *clk_name = node->name;
698 const char *parent_name;
699 struct clk_init_data init;
705 rc = of_property_read_u32(node, "reg", ®);
709 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
710 if (WARN_ON(!pll_clk))
713 pll_clk->reg = pmc_base + reg;
714 pll_clk->lock = &_lock;
715 pll_clk->type = pll_type;
717 of_property_read_string(node, "clock-output-names", &clk_name);
719 init.name = clk_name;
720 init.ops = &vtwm_pll_ops;
722 parent_name = of_clk_get_parent_name(node, 0);
723 init.parent_names = &parent_name;
724 init.num_parents = 1;
726 pll_clk->hw.init = &init;
728 clk = clk_register(NULL, &pll_clk->hw);
729 if (WARN_ON(IS_ERR(clk))) {
733 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
734 clk_register_clkdev(clk, clk_name, NULL);
738 /* Wrappers for initialization functions */
740 static void __init vt8500_pll_init(struct device_node *node)
742 vtwm_pll_clk_init(node, PLL_TYPE_VT8500);
744 CLK_OF_DECLARE(vt8500_pll, "via,vt8500-pll-clock", vt8500_pll_init);
746 static void __init wm8650_pll_init(struct device_node *node)
748 vtwm_pll_clk_init(node, PLL_TYPE_WM8650);
750 CLK_OF_DECLARE(wm8650_pll, "wm,wm8650-pll-clock", wm8650_pll_init);
752 static void __init wm8750_pll_init(struct device_node *node)
754 vtwm_pll_clk_init(node, PLL_TYPE_WM8750);
756 CLK_OF_DECLARE(wm8750_pll, "wm,wm8750-pll-clock", wm8750_pll_init);
758 static void __init wm8850_pll_init(struct device_node *node)
760 vtwm_pll_clk_init(node, PLL_TYPE_WM8850);
762 CLK_OF_DECLARE(wm8850_pll, "wm,wm8850-pll-clock", wm8850_pll_init);