2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0
13 #include <asm/arch/clock.h>
14 #include <asm/arch/cru_rk3288.h>
15 #include <asm/arch/grf_rk3288.h>
16 #include <asm/arch/hardware.h>
17 #include <dt-bindings/clock/rk3288-cru.h>
18 #include <dm/device-internal.h>
20 #include <dm/uclass-internal.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 struct rk3288_clk_plat {
25 enum rk_clk_id clk_id;
28 struct rk3288_clk_priv {
29 struct rk3288_grf *grf;
30 struct rk3288_cru *cru;
41 VCO_MAX_HZ = 2200U * 1000000,
42 VCO_MIN_HZ = 440 * 1000000,
43 OUTPUT_MAX_HZ = 2200U * 1000000,
44 OUTPUT_MIN_HZ = 27500000,
45 FREF_MAX_HZ = 2200U * 1000000,
46 FREF_MIN_HZ = 269 * 1000000,
57 PLL_BWADJ_MASK = 0x0fff,
62 /* CLKSEL1: pd bus clk pll sel: codec or general */
63 PD_BUS_SEL_PLL_MASK = 15,
67 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
68 PD_BUS_PCLK_DIV_SHIFT = 12,
69 PD_BUS_PCLK_DIV_MASK = 7,
71 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
72 PD_BUS_HCLK_DIV_SHIFT = 8,
73 PD_BUS_HCLK_DIV_MASK = 3,
75 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
76 PD_BUS_ACLK_DIV0_SHIFT = 3,
77 PD_BUS_ACLK_DIV0_MASK = 0x1f,
78 PD_BUS_ACLK_DIV1_SHIFT = 0,
79 PD_BUS_ACLK_DIV1_MASK = 0x7,
83 * peripheral bus pclk div:
84 * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
86 PERI_PCLK_DIV_SHIFT = 12,
87 PERI_PCLK_DIV_MASK = 7,
89 /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
90 PERI_HCLK_DIV_SHIFT = 8,
91 PERI_HCLK_DIV_MASK = 3,
94 * peripheral bus aclk div:
95 * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
97 PERI_ACLK_DIV_SHIFT = 0,
98 PERI_ACLK_DIV_MASK = 0x1f,
100 SOCSTS_DPLL_LOCK = 1 << 5,
101 SOCSTS_APLL_LOCK = 1 << 6,
102 SOCSTS_CPLL_LOCK = 1 << 7,
103 SOCSTS_GPLL_LOCK = 1 << 8,
104 SOCSTS_NPLL_LOCK = 1 << 9,
107 #define RATE_TO_DIV(input_rate, output_rate) \
108 ((input_rate) / (output_rate) - 1);
110 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
112 #define PLL_DIVISORS(hz, _nr, _no) {\
113 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
114 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
115 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
116 "divisors on line " __stringify(__LINE__));
118 /* Keep divisors as low as possible to reduce jitter and power usage */
119 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
120 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
121 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
123 int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp)
127 for (uclass_find_first_device(UCLASS_CLK, &dev);
129 uclass_find_next_device(&dev)) {
130 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
132 if (plat->clk_id == clk_id) {
134 return device_probe(dev);
141 void *rockchip_get_cru(void)
143 struct rk3288_clk_priv *priv;
147 ret = rkclk_get_clk(CLK_GENERAL, &dev);
150 priv = dev_get_priv(dev);
154 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
155 const struct pll_div *div)
157 int pll_id = rk_pll_id(clk_id);
158 struct rk3288_pll *pll = &cru->pll[pll_id];
159 /* All PLLs have same VCO and output frequency range restrictions. */
160 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
161 uint output_hz = vco_hz / div->no;
163 debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
164 pll, div->nf, div->nr, div->no, vco_hz, output_hz);
165 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
166 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
167 (div->no == 1 || !(div->no % 2)));
170 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
172 rk_clrsetreg(&pll->con0,
173 CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
174 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
175 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
176 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
180 /* return form rest */
181 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
186 static inline unsigned int log2(unsigned int value)
188 return fls(value) - 1;
191 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
194 static const struct pll_div dpll_cfg[] = {
195 {.nf = 25, .nr = 2, .no = 1},
196 {.nf = 400, .nr = 9, .no = 2},
197 {.nf = 500, .nr = 9, .no = 2},
198 {.nf = 100, .nr = 3, .no = 1},
202 debug("%s: cru=%p, grf=%p, hz=%u\n", __func__, cru, grf, hz);
207 case 533000000: /* actually 533.3P MHz */
210 case 666000000: /* actually 666.6P MHz */
217 debug("Unsupported SDRAM frequency, add to clock.c!");
221 /* pll enter slow-mode */
222 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
223 DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
225 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
227 /* wait for pll lock */
228 while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
231 /* PLL enter normal-mode */
232 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
233 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
238 #ifdef CONFIG_SPL_BUILD
239 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
245 /* pll enter slow-mode */
246 rk_clrsetreg(&cru->cru_mode_con,
247 GPLL_MODE_MASK << GPLL_MODE_SHIFT |
248 CPLL_MODE_MASK << CPLL_MODE_SHIFT,
249 GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
250 CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
253 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
254 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
256 /* waiting for pll lock */
257 while ((readl(&grf->soc_status[1]) &
258 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
259 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
263 * pd_bus clock pll source selection and
264 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
266 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
267 assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
268 hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
269 assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
270 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
272 pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
273 assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
274 PD_BUS_ACLK_HZ && pclk_div < 0x7);
276 rk_clrsetreg(&cru->cru_clksel_con[1],
277 PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT |
278 PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT |
279 PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT |
280 PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT,
281 pclk_div << PD_BUS_PCLK_DIV_SHIFT |
282 hclk_div << PD_BUS_HCLK_DIV_SHIFT |
283 aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
287 * peri clock pll source selection and
288 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
290 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
291 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
293 hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
294 assert((1 << hclk_div) * PERI_HCLK_HZ ==
295 PERI_ACLK_HZ && (hclk_div < 0x4));
297 pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
298 assert((1 << pclk_div) * PERI_PCLK_HZ ==
299 PERI_ACLK_HZ && (pclk_div < 0x4));
301 rk_clrsetreg(&cru->cru_clksel_con[10],
302 PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
303 PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
304 PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
305 pclk_div << PERI_PCLK_DIV_SHIFT |
306 hclk_div << PERI_HCLK_DIV_SHIFT |
307 aclk_div << PERI_ACLK_DIV_SHIFT);
309 /* PLL enter normal-mode */
310 rk_clrsetreg(&cru->cru_mode_con,
311 GPLL_MODE_MASK << GPLL_MODE_SHIFT |
312 CPLL_MODE_MASK << CPLL_MODE_SHIFT,
313 GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
314 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
318 /* Get pll rate by id */
319 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
320 enum rk_clk_id clk_id)
324 int pll_id = rk_pll_id(clk_id);
325 struct rk3288_pll *pll = &cru->pll[pll_id];
326 static u8 clk_shift[CLK_COUNT] = {
327 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
328 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
332 con = readl(&cru->cru_mode_con);
333 shift = clk_shift[clk_id];
334 switch ((con >> shift) & APLL_MODE_MASK) {
337 case APLL_MODE_NORMAL:
339 con = readl(&pll->con0);
340 no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
341 nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
342 con = readl(&pll->con1);
343 nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
345 return (24 * nf / (nr * no)) * 1000000;
352 static ulong rk3288_clk_get_rate(struct udevice *dev)
354 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
355 struct rk3288_clk_priv *priv = dev_get_priv(dev);
357 debug("%s\n", dev->name);
358 return rkclk_pll_get_rate(priv->cru, plat->clk_id);
361 static ulong rk3288_clk_set_rate(struct udevice *dev, ulong rate)
363 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
364 struct rk3288_clk_priv *priv = dev_get_priv(dev);
366 debug("%s\n", dev->name);
367 switch (plat->clk_id) {
369 rkclk_configure_ddr(priv->cru, priv->grf, rate);
378 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
387 con = readl(&cru->cru_clksel_con[12]);
388 mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
389 div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
392 con = readl(&cru->cru_clksel_con[11]);
393 mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
394 div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
397 con = readl(&cru->cru_clksel_con[12]);
398 mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
399 div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
405 src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
406 return DIV_TO_RATE(src_rate, div);
409 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
410 int periph, uint freq)
415 debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
416 src_clk_div = RATE_TO_DIV(gclk_rate, freq);
418 if (src_clk_div > 0x3f) {
419 src_clk_div = RATE_TO_DIV(OSC_HZ, freq);
420 mux = EMMC_PLL_SELECT_24MHZ;
421 assert((int)EMMC_PLL_SELECT_24MHZ ==
422 (int)MMC0_PLL_SELECT_24MHZ);
424 mux = EMMC_PLL_SELECT_GENERAL;
425 assert((int)EMMC_PLL_SELECT_GENERAL ==
426 (int)MMC0_PLL_SELECT_GENERAL);
430 rk_clrsetreg(&cru->cru_clksel_con[12],
431 EMMC_PLL_MASK << EMMC_PLL_SHIFT |
432 EMMC_DIV_MASK << EMMC_DIV_SHIFT,
433 mux << EMMC_PLL_SHIFT |
434 (src_clk_div - 1) << EMMC_DIV_SHIFT);
437 rk_clrsetreg(&cru->cru_clksel_con[11],
438 MMC0_PLL_MASK << MMC0_PLL_SHIFT |
439 MMC0_DIV_MASK << MMC0_DIV_SHIFT,
440 mux << MMC0_PLL_SHIFT |
441 (src_clk_div - 1) << MMC0_DIV_SHIFT);
444 rk_clrsetreg(&cru->cru_clksel_con[12],
445 SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
446 SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
447 mux << SDIO0_PLL_SHIFT |
448 (src_clk_div - 1) << SDIO0_DIV_SHIFT);
454 return rockchip_mmc_get_clk(cru, gclk_rate, periph);
457 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
465 con = readl(&cru->cru_clksel_con[25]);
466 mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK;
467 div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
470 con = readl(&cru->cru_clksel_con[25]);
471 mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK;
472 div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
475 con = readl(&cru->cru_clksel_con[39]);
476 mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK;
477 div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK;
482 assert(mux == SPI0_PLL_SELECT_GENERAL);
484 return DIV_TO_RATE(gclk_rate, div);
487 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
488 int periph, uint freq)
492 debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
493 src_clk_div = RATE_TO_DIV(gclk_rate, freq);
496 rk_clrsetreg(&cru->cru_clksel_con[25],
497 SPI0_PLL_MASK << SPI0_PLL_SHIFT |
498 SPI0_DIV_MASK << SPI0_DIV_SHIFT,
499 SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
500 src_clk_div << SPI0_DIV_SHIFT);
503 rk_clrsetreg(&cru->cru_clksel_con[25],
504 SPI1_PLL_MASK << SPI1_PLL_SHIFT |
505 SPI1_DIV_MASK << SPI1_DIV_SHIFT,
506 SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
507 src_clk_div << SPI1_DIV_SHIFT);
510 rk_clrsetreg(&cru->cru_clksel_con[39],
511 SPI2_PLL_MASK << SPI2_PLL_SHIFT |
512 SPI2_DIV_MASK << SPI2_DIV_SHIFT,
513 SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
514 src_clk_div << SPI2_DIV_SHIFT);
520 return rockchip_spi_get_clk(cru, gclk_rate, periph);
523 static ulong rk3288_get_periph_rate(struct udevice *dev, int periph)
525 struct rk3288_clk_priv *priv = dev_get_priv(dev);
526 struct udevice *gclk;
527 ulong new_rate, gclk_rate;
530 ret = rkclk_get_clk(CLK_GENERAL, &gclk);
533 gclk_rate = clk_get_rate(gclk);
538 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, periph);
543 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, periph);
559 static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
561 struct rk3288_clk_priv *priv = dev_get_priv(dev);
562 struct udevice *gclk;
563 ulong new_rate, gclk_rate;
566 ret = rkclk_get_clk(CLK_GENERAL, &gclk);
569 gclk_rate = clk_get_rate(gclk);
574 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate, periph,
580 new_rate = rockchip_spi_set_clk(priv->cru, gclk_rate, periph,
590 static struct clk_ops rk3288_clk_ops = {
591 .get_rate = rk3288_clk_get_rate,
592 .set_rate = rk3288_clk_set_rate,
593 .set_periph_rate = rk3288_set_periph_rate,
594 .get_periph_rate = rk3288_get_periph_rate,
597 static int rk3288_clk_probe(struct udevice *dev)
599 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
600 struct rk3288_clk_priv *priv = dev_get_priv(dev);
602 if (plat->clk_id != CLK_OSC) {
603 struct rk3288_clk_priv *parent_priv = dev_get_priv(dev->parent);
605 priv->cru = parent_priv->cru;
606 priv->grf = parent_priv->grf;
609 priv->cru = (struct rk3288_cru *)dev_get_addr(dev);
610 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
611 #ifdef CONFIG_SPL_BUILD
612 rkclk_init(priv->cru, priv->grf);
618 static const char *const clk_name[CLK_COUNT] = {
627 static int rk3288_clk_bind(struct udevice *dev)
629 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
632 /* We only need to set up the root clock */
633 if (dev->of_offset == -1) {
634 plat->clk_id = CLK_OSC;
638 /* Create devices for P main clocks */
639 for (pll = 1; pll < CLK_COUNT; pll++) {
640 struct udevice *child;
641 struct rk3288_clk_plat *cplat;
643 debug("%s %s\n", __func__, clk_name[pll]);
644 ret = device_bind_driver(dev, "clk_rk3288", clk_name[pll],
648 cplat = dev_get_platdata(child);
652 /* The reset driver does not have a device node, so bind it here */
653 ret = device_bind_driver(gd->dm_root, "rk3288_reset", "reset", &dev);
655 debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
660 static const struct udevice_id rk3288_clk_ids[] = {
661 { .compatible = "rockchip,rk3288-cru" },
665 U_BOOT_DRIVER(clk_rk3288) = {
666 .name = "clk_rk3288",
668 .of_match = rk3288_clk_ids,
669 .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
670 .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
671 .ops = &rk3288_clk_ops,
672 .bind = rk3288_clk_bind,
673 .probe = rk3288_clk_probe,