2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0
13 #include <asm/arch/clock.h>
14 #include <asm/arch/cru_rk3288.h>
15 #include <asm/arch/grf_rk3288.h>
16 #include <asm/arch/hardware.h>
17 #include <dt-bindings/clock/rk3288-cru.h>
18 #include <dm/device-internal.h>
20 #include <dm/uclass-internal.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 struct rk3288_clk_plat {
25 enum rk_clk_id clk_id;
28 struct rk3288_clk_priv {
29 struct rk3288_grf *grf;
30 struct rk3288_cru *cru;
41 VCO_MAX_HZ = 2200U * 1000000,
42 VCO_MIN_HZ = 440 * 1000000,
43 OUTPUT_MAX_HZ = 2200U * 1000000,
44 OUTPUT_MIN_HZ = 27500000,
45 FREF_MAX_HZ = 2200U * 1000000,
46 FREF_MIN_HZ = 269 * 1000000,
57 PLL_BWADJ_MASK = 0x0fff,
63 CORE_SEL_PLL_MASK = 1,
64 CORE_SEL_PLL_SHIFT = 15,
72 /* CLKSEL1: pd bus clk pll sel: codec or general */
73 PD_BUS_SEL_PLL_MASK = 15,
77 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
78 PD_BUS_PCLK_DIV_SHIFT = 12,
79 PD_BUS_PCLK_DIV_MASK = 7,
81 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
82 PD_BUS_HCLK_DIV_SHIFT = 8,
83 PD_BUS_HCLK_DIV_MASK = 3,
85 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
86 PD_BUS_ACLK_DIV0_SHIFT = 3,
87 PD_BUS_ACLK_DIV0_MASK = 0x1f,
88 PD_BUS_ACLK_DIV1_SHIFT = 0,
89 PD_BUS_ACLK_DIV1_MASK = 0x7,
93 * peripheral bus pclk div:
94 * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
96 PERI_SEL_PLL_MASK = 1,
97 PERI_SEL_PLL_SHIFT = 15,
101 PERI_PCLK_DIV_SHIFT = 12,
102 PERI_PCLK_DIV_MASK = 3,
104 /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
105 PERI_HCLK_DIV_SHIFT = 8,
106 PERI_HCLK_DIV_MASK = 3,
109 * peripheral bus aclk div:
110 * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
112 PERI_ACLK_DIV_SHIFT = 0,
113 PERI_ACLK_DIV_MASK = 0x1f,
115 SOCSTS_DPLL_LOCK = 1 << 5,
116 SOCSTS_APLL_LOCK = 1 << 6,
117 SOCSTS_CPLL_LOCK = 1 << 7,
118 SOCSTS_GPLL_LOCK = 1 << 8,
119 SOCSTS_NPLL_LOCK = 1 << 9,
122 #define RATE_TO_DIV(input_rate, output_rate) \
123 ((input_rate) / (output_rate) - 1);
125 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
127 #define PLL_DIVISORS(hz, _nr, _no) {\
128 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
129 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
130 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
131 "divisors on line " __stringify(__LINE__));
133 /* Keep divisors as low as possible to reduce jitter and power usage */
134 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
135 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
136 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
138 int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp)
142 for (uclass_find_first_device(UCLASS_CLK, &dev);
144 uclass_find_next_device(&dev)) {
145 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
147 if (plat->clk_id == clk_id) {
149 return device_probe(dev);
156 void *rockchip_get_cru(void)
158 struct rk3288_clk_priv *priv;
162 ret = rkclk_get_clk(CLK_GENERAL, &dev);
165 priv = dev_get_priv(dev);
169 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
170 const struct pll_div *div)
172 int pll_id = rk_pll_id(clk_id);
173 struct rk3288_pll *pll = &cru->pll[pll_id];
174 /* All PLLs have same VCO and output frequency range restrictions. */
175 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
176 uint output_hz = vco_hz / div->no;
178 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
179 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
180 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
181 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
182 (div->no == 1 || !(div->no % 2)));
185 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
187 rk_clrsetreg(&pll->con0,
188 CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
189 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
190 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
191 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
195 /* return from reset */
196 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
201 static inline unsigned int log2(unsigned int value)
203 return fls(value) - 1;
206 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
209 static const struct pll_div dpll_cfg[] = {
210 {.nf = 25, .nr = 2, .no = 1},
211 {.nf = 400, .nr = 9, .no = 2},
212 {.nf = 500, .nr = 9, .no = 2},
213 {.nf = 100, .nr = 3, .no = 1},
221 case 533000000: /* actually 533.3P MHz */
224 case 666000000: /* actually 666.6P MHz */
231 debug("Unsupported SDRAM frequency");
235 /* pll enter slow-mode */
236 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
237 DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
239 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
241 /* wait for pll lock */
242 while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
245 /* PLL enter normal-mode */
246 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
247 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
252 #ifndef CONFIG_SPL_BUILD
253 #define VCO_MAX_KHZ 2200000
254 #define VCO_MIN_KHZ 440000
255 #define FREF_MAX_KHZ 2200000
256 #define FREF_MIN_KHZ 269
258 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
260 uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
262 uint diff_khz, best_diff_khz;
263 const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
266 uint freq_khz = freq_hz / 1000;
269 printf("%s: the frequency can not be 0 Hz\n", __func__);
273 no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
275 *ext_div = DIV_ROUND_UP(no, max_no);
276 no = DIV_ROUND_UP(no, *ext_div);
279 /* only even divisors (and 1) are supported */
281 no = DIV_ROUND_UP(no, 2) * 2;
283 vco_khz = freq_khz * no;
287 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
288 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
295 best_diff_khz = vco_khz;
296 for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
297 fref_khz = ref_khz / nr;
298 if (fref_khz < FREF_MIN_KHZ)
300 if (fref_khz > FREF_MAX_KHZ)
303 nf = vco_khz / fref_khz;
306 diff_khz = vco_khz - nf * fref_khz;
307 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
309 diff_khz = fref_khz - diff_khz;
312 if (diff_khz >= best_diff_khz)
315 best_diff_khz = diff_khz;
320 if (best_diff_khz > 4 * 1000) {
321 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
322 __func__, freq_hz, best_diff_khz * 1000);
329 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
330 int periph, unsigned int rate_hz)
332 struct pll_div npll_config = {0};
336 ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
340 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
341 NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
342 rkclk_set_pll(cru, CLK_NEW, &npll_config);
344 /* waiting for pll lock */
346 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
351 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
352 NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
354 /* vop dclk source clk: npll,dclk_div: 1 */
357 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
358 (lcdc_div - 1) << 8 | 2 << 0);
361 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
362 (lcdc_div - 1) << 8 | 2 << 6);
370 #ifdef CONFIG_SPL_BUILD
371 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
377 /* pll enter slow-mode */
378 rk_clrsetreg(&cru->cru_mode_con,
379 GPLL_MODE_MASK << GPLL_MODE_SHIFT |
380 CPLL_MODE_MASK << CPLL_MODE_SHIFT,
381 GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
382 CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
385 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
386 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
388 /* waiting for pll lock */
389 while ((readl(&grf->soc_status[1]) &
390 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
391 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
395 * pd_bus clock pll source selection and
396 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
398 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
399 assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
400 hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
401 assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
402 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
404 pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
405 assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
406 PD_BUS_ACLK_HZ && pclk_div < 0x7);
408 rk_clrsetreg(&cru->cru_clksel_con[1],
409 PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT |
410 PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT |
411 PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT |
412 PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT,
413 pclk_div << PD_BUS_PCLK_DIV_SHIFT |
414 hclk_div << PD_BUS_HCLK_DIV_SHIFT |
415 aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
419 * peri clock pll source selection and
420 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
422 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
423 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
425 hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
426 assert((1 << hclk_div) * PERI_HCLK_HZ ==
427 PERI_ACLK_HZ && (hclk_div < 0x4));
429 pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
430 assert((1 << pclk_div) * PERI_PCLK_HZ ==
431 PERI_ACLK_HZ && (pclk_div < 0x4));
433 rk_clrsetreg(&cru->cru_clksel_con[10],
434 PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
435 PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
436 PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
437 PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
438 pclk_div << PERI_PCLK_DIV_SHIFT |
439 hclk_div << PERI_HCLK_DIV_SHIFT |
440 aclk_div << PERI_ACLK_DIV_SHIFT);
442 /* PLL enter normal-mode */
443 rk_clrsetreg(&cru->cru_mode_con,
444 GPLL_MODE_MASK << GPLL_MODE_SHIFT |
445 CPLL_MODE_MASK << CPLL_MODE_SHIFT,
446 GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
447 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
451 void rkclk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
453 /* pll enter slow-mode */
454 rk_clrsetreg(&cru->cru_mode_con,
455 APLL_MODE_MASK << APLL_MODE_SHIFT,
456 APLL_MODE_SLOW << APLL_MODE_SHIFT);
458 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
460 /* waiting for pll lock */
461 while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
465 * core clock pll source selection and
466 * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
467 * core clock select apll, apll clk = 1800MHz
468 * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
470 rk_clrsetreg(&cru->cru_clksel_con[0],
471 CORE_SEL_PLL_MASK << CORE_SEL_PLL_SHIFT |
472 A17_DIV_MASK << A17_DIV_SHIFT |
473 MP_DIV_MASK << MP_DIV_SHIFT |
474 M0_DIV_MASK << M0_DIV_SHIFT,
480 * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
481 * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
483 rk_clrsetreg(&cru->cru_clksel_con[37],
484 CLK_L2RAM_DIV_MASK << CLK_L2RAM_DIV_SHIFT |
485 ATCLK_CORE_DIV_CON_MASK << ATCLK_CORE_DIV_CON_SHIFT |
486 PCLK_CORE_DBG_DIV_MASK >> PCLK_CORE_DBG_DIV_SHIFT,
487 1 << CLK_L2RAM_DIV_SHIFT |
488 3 << ATCLK_CORE_DIV_CON_SHIFT |
489 3 << PCLK_CORE_DBG_DIV_SHIFT);
491 /* PLL enter normal-mode */
492 rk_clrsetreg(&cru->cru_mode_con,
493 APLL_MODE_MASK << APLL_MODE_SHIFT,
494 APLL_MODE_NORMAL << APLL_MODE_SHIFT);
497 /* Get pll rate by id */
498 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
499 enum rk_clk_id clk_id)
503 int pll_id = rk_pll_id(clk_id);
504 struct rk3288_pll *pll = &cru->pll[pll_id];
505 static u8 clk_shift[CLK_COUNT] = {
506 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
507 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
511 con = readl(&cru->cru_mode_con);
512 shift = clk_shift[clk_id];
513 switch ((con >> shift) & APLL_MODE_MASK) {
516 case APLL_MODE_NORMAL:
518 con = readl(&pll->con0);
519 no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
520 nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
521 con = readl(&pll->con1);
522 nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
524 return (24 * nf / (nr * no)) * 1000000;
531 static ulong rk3288_clk_get_rate(struct udevice *dev)
533 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
534 struct rk3288_clk_priv *priv = dev_get_priv(dev);
536 debug("%s\n", dev->name);
537 return rkclk_pll_get_rate(priv->cru, plat->clk_id);
540 static ulong rk3288_clk_set_rate(struct udevice *dev, ulong rate)
542 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
543 struct rk3288_clk_priv *priv = dev_get_priv(dev);
545 debug("%s\n", dev->name);
546 switch (plat->clk_id) {
548 rkclk_configure_ddr(priv->cru, priv->grf, rate);
557 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
566 con = readl(&cru->cru_clksel_con[12]);
567 mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
568 div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
571 con = readl(&cru->cru_clksel_con[11]);
572 mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
573 div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
576 con = readl(&cru->cru_clksel_con[12]);
577 mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
578 div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
584 src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
585 return DIV_TO_RATE(src_rate, div);
588 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
589 int periph, uint freq)
594 debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
595 src_clk_div = RATE_TO_DIV(gclk_rate, freq);
597 if (src_clk_div > 0x3f) {
598 src_clk_div = RATE_TO_DIV(OSC_HZ, freq);
599 mux = EMMC_PLL_SELECT_24MHZ;
600 assert((int)EMMC_PLL_SELECT_24MHZ ==
601 (int)MMC0_PLL_SELECT_24MHZ);
603 mux = EMMC_PLL_SELECT_GENERAL;
604 assert((int)EMMC_PLL_SELECT_GENERAL ==
605 (int)MMC0_PLL_SELECT_GENERAL);
609 rk_clrsetreg(&cru->cru_clksel_con[12],
610 EMMC_PLL_MASK << EMMC_PLL_SHIFT |
611 EMMC_DIV_MASK << EMMC_DIV_SHIFT,
612 mux << EMMC_PLL_SHIFT |
613 (src_clk_div - 1) << EMMC_DIV_SHIFT);
616 rk_clrsetreg(&cru->cru_clksel_con[11],
617 MMC0_PLL_MASK << MMC0_PLL_SHIFT |
618 MMC0_DIV_MASK << MMC0_DIV_SHIFT,
619 mux << MMC0_PLL_SHIFT |
620 (src_clk_div - 1) << MMC0_DIV_SHIFT);
623 rk_clrsetreg(&cru->cru_clksel_con[12],
624 SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
625 SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
626 mux << SDIO0_PLL_SHIFT |
627 (src_clk_div - 1) << SDIO0_DIV_SHIFT);
633 return rockchip_mmc_get_clk(cru, gclk_rate, periph);
636 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
644 con = readl(&cru->cru_clksel_con[25]);
645 mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK;
646 div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
649 con = readl(&cru->cru_clksel_con[25]);
650 mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK;
651 div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
654 con = readl(&cru->cru_clksel_con[39]);
655 mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK;
656 div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK;
661 assert(mux == SPI0_PLL_SELECT_GENERAL);
663 return DIV_TO_RATE(gclk_rate, div);
666 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
667 int periph, uint freq)
671 debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
672 src_clk_div = RATE_TO_DIV(gclk_rate, freq);
675 rk_clrsetreg(&cru->cru_clksel_con[25],
676 SPI0_PLL_MASK << SPI0_PLL_SHIFT |
677 SPI0_DIV_MASK << SPI0_DIV_SHIFT,
678 SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
679 src_clk_div << SPI0_DIV_SHIFT);
682 rk_clrsetreg(&cru->cru_clksel_con[25],
683 SPI1_PLL_MASK << SPI1_PLL_SHIFT |
684 SPI1_DIV_MASK << SPI1_DIV_SHIFT,
685 SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
686 src_clk_div << SPI1_DIV_SHIFT);
689 rk_clrsetreg(&cru->cru_clksel_con[39],
690 SPI2_PLL_MASK << SPI2_PLL_SHIFT |
691 SPI2_DIV_MASK << SPI2_DIV_SHIFT,
692 SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
693 src_clk_div << SPI2_DIV_SHIFT);
699 return rockchip_spi_get_clk(cru, gclk_rate, periph);
702 static ulong rk3288_get_periph_rate(struct udevice *dev, int periph)
704 struct rk3288_clk_priv *priv = dev_get_priv(dev);
705 struct udevice *gclk;
706 ulong new_rate, gclk_rate;
709 ret = rkclk_get_clk(CLK_GENERAL, &gclk);
712 gclk_rate = clk_get_rate(gclk);
717 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, periph);
722 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, periph);
738 static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
740 struct rk3288_clk_priv *priv = dev_get_priv(dev);
741 struct rk3288_cru *cru = priv->cru;
742 struct udevice *gclk;
743 ulong new_rate, gclk_rate;
746 ret = rkclk_get_clk(CLK_GENERAL, &gclk);
749 gclk_rate = clk_get_rate(gclk);
754 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, periph, rate);
759 new_rate = rockchip_spi_set_clk(cru, gclk_rate, periph, rate);
761 #ifndef CONFIG_SPL_BUILD
764 new_rate = rockchip_vop_set_clk(cru, priv->grf, periph, rate);
767 /* clk_edp_24M source: 24M */
768 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
771 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
773 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
780 /* vop aclk source clk: cpll */
781 div = CPLL_HZ / rate;
782 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
786 rk_clrsetreg(&cru->cru_clksel_con[31],
788 0 << 6 | (div - 1) << 0);
791 rk_clrsetreg(&cru->cru_clksel_con[31],
793 0 << 14 | (div - 1) << 8);
800 /* enable pclk hdmi ctrl */
801 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
803 /* software reset hdmi */
804 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
806 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
817 static struct clk_ops rk3288_clk_ops = {
818 .get_rate = rk3288_clk_get_rate,
819 .set_rate = rk3288_clk_set_rate,
820 .set_periph_rate = rk3288_set_periph_rate,
821 .get_periph_rate = rk3288_get_periph_rate,
824 static int rk3288_clk_probe(struct udevice *dev)
826 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
827 struct rk3288_clk_priv *priv = dev_get_priv(dev);
829 if (plat->clk_id != CLK_OSC) {
830 struct rk3288_clk_priv *parent_priv = dev_get_priv(dev->parent);
832 priv->cru = parent_priv->cru;
833 priv->grf = parent_priv->grf;
836 priv->cru = (struct rk3288_cru *)dev_get_addr(dev);
837 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
838 #ifdef CONFIG_SPL_BUILD
839 rkclk_init(priv->cru, priv->grf);
845 static const char *const clk_name[CLK_COUNT] = {
854 static int rk3288_clk_bind(struct udevice *dev)
856 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
859 /* We only need to set up the root clock */
860 if (dev->of_offset == -1) {
861 plat->clk_id = CLK_OSC;
865 /* Create devices for P main clocks */
866 for (pll = 1; pll < CLK_COUNT; pll++) {
867 struct udevice *child;
868 struct rk3288_clk_plat *cplat;
870 debug("%s %s\n", __func__, clk_name[pll]);
871 ret = device_bind_driver(dev, "clk_rk3288", clk_name[pll],
875 cplat = dev_get_platdata(child);
879 /* The reset driver does not have a device node, so bind it here */
880 ret = device_bind_driver(gd->dm_root, "rk3288_reset", "reset", &dev);
882 debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
887 static const struct udevice_id rk3288_clk_ids[] = {
888 { .compatible = "rockchip,rk3288-cru" },
892 U_BOOT_DRIVER(clk_rk3288) = {
893 .name = "clk_rk3288",
895 .of_match = rk3288_clk_ids,
896 .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
897 .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
898 .ops = &rk3288_clk_ops,
899 .bind = rk3288_clk_bind,
900 .probe = rk3288_clk_probe,