2 * Copyright (c) 2016-2017 Linaro Ltd.
3 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
11 #include <dt-bindings/clock/hi3660-clock.h>
12 #include <linux/clk-provider.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
17 static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = {
18 { HI3660_CLKIN_SYS, "clkin_sys", NULL, 0, 19200000, },
19 { HI3660_CLKIN_REF, "clkin_ref", NULL, 0, 32764, },
20 { HI3660_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 128000000, },
21 { HI3660_CLK_PPLL0, "clk_ppll0", NULL, 0, 1600000000, },
22 { HI3660_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, },
23 { HI3660_CLK_PPLL2, "clk_ppll2", NULL, 0, 960000000, },
24 { HI3660_CLK_PPLL3, "clk_ppll3", NULL, 0, 1290000000, },
25 { HI3660_CLK_SCPLL, "clk_scpll", NULL, 0, 245760000, },
26 { HI3660_PCLK, "pclk", NULL, 0, 20000000, },
27 { HI3660_CLK_UART0_DBG, "clk_uart0_dbg", NULL, 0, 19200000, },
28 { HI3660_CLK_UART6, "clk_uart6", NULL, 0, 19200000, },
29 { HI3660_OSC32K, "osc32k", NULL, 0, 32764, },
30 { HI3660_OSC19M, "osc19m", NULL, 0, 19200000, },
31 { HI3660_CLK_480M, "clk_480m", NULL, 0, 480000000, },
32 { HI3660_CLK_INV, "clk_inv", NULL, 0, 10000000, },
36 static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = {
37 { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 8, 0, },
38 { HI3660_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys", 1, 6, 0, },
39 { HI3660_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_iomcu", 1, 4, 0, },
40 { HI3660_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_iomcu", 1, 4, 0, },
41 { HI3660_CLK_GATE_I2C2, "clk_gate_i2c2", "clk_i2c2_iomcu", 1, 4, 0, },
42 { HI3660_CLK_GATE_I2C6, "clk_gate_i2c6", "clk_i2c6_iomcu", 1, 4, 0, },
43 { HI3660_CLK_DIV_SYSBUS, "clk_div_sysbus", "clk_mux_sysbus", 1, 7, 0, },
44 { HI3660_CLK_DIV_320M, "clk_div_320m", "clk_320m_pll_gt", 1, 5, 0, },
45 { HI3660_CLK_DIV_A53, "clk_div_a53hpm", "clk_a53hpm_andgt", 1, 2, 0, },
46 { HI3660_CLK_GATE_SPI0, "clk_gate_spi0", "clk_ppll0", 1, 8, 0, },
47 { HI3660_CLK_GATE_SPI2, "clk_gate_spi2", "clk_ppll0", 1, 8, 0, },
48 { HI3660_PCIEPHY_REF, "clk_pciephy_ref", "clk_div_pciephy", 1, 1, 0, },
49 { HI3660_CLK_ABB_USB, "clk_abb_usb", "clk_gate_usb_tcxo_en", 1, 1, 0 },
52 static const struct hisi_gate_clock hi3660_crgctrl_gate_sep_clks[] = {
53 { HI3660_HCLK_GATE_SDIO0, "hclk_gate_sdio0", "clk_div_sysbus",
54 CLK_SET_RATE_PARENT, 0x0, 21, 0, },
55 { HI3660_HCLK_GATE_SD, "hclk_gate_sd", "clk_div_sysbus",
56 CLK_SET_RATE_PARENT, 0x0, 30, 0, },
57 { HI3660_CLK_GATE_AOMM, "clk_gate_aomm", "clk_div_aomm",
58 CLK_SET_RATE_PARENT, 0x0, 31, 0, },
59 { HI3660_PCLK_GPIO0, "pclk_gpio0", "clk_div_cfgbus",
60 CLK_SET_RATE_PARENT, 0x10, 0, 0, },
61 { HI3660_PCLK_GPIO1, "pclk_gpio1", "clk_div_cfgbus",
62 CLK_SET_RATE_PARENT, 0x10, 1, 0, },
63 { HI3660_PCLK_GPIO2, "pclk_gpio2", "clk_div_cfgbus",
64 CLK_SET_RATE_PARENT, 0x10, 2, 0, },
65 { HI3660_PCLK_GPIO3, "pclk_gpio3", "clk_div_cfgbus",
66 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
67 { HI3660_PCLK_GPIO4, "pclk_gpio4", "clk_div_cfgbus",
68 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
69 { HI3660_PCLK_GPIO5, "pclk_gpio5", "clk_div_cfgbus",
70 CLK_SET_RATE_PARENT, 0x10, 5, 0, },
71 { HI3660_PCLK_GPIO6, "pclk_gpio6", "clk_div_cfgbus",
72 CLK_SET_RATE_PARENT, 0x10, 6, 0, },
73 { HI3660_PCLK_GPIO7, "pclk_gpio7", "clk_div_cfgbus",
74 CLK_SET_RATE_PARENT, 0x10, 7, 0, },
75 { HI3660_PCLK_GPIO8, "pclk_gpio8", "clk_div_cfgbus",
76 CLK_SET_RATE_PARENT, 0x10, 8, 0, },
77 { HI3660_PCLK_GPIO9, "pclk_gpio9", "clk_div_cfgbus",
78 CLK_SET_RATE_PARENT, 0x10, 9, 0, },
79 { HI3660_PCLK_GPIO10, "pclk_gpio10", "clk_div_cfgbus",
80 CLK_SET_RATE_PARENT, 0x10, 10, 0, },
81 { HI3660_PCLK_GPIO11, "pclk_gpio11", "clk_div_cfgbus",
82 CLK_SET_RATE_PARENT, 0x10, 11, 0, },
83 { HI3660_PCLK_GPIO12, "pclk_gpio12", "clk_div_cfgbus",
84 CLK_SET_RATE_PARENT, 0x10, 12, 0, },
85 { HI3660_PCLK_GPIO13, "pclk_gpio13", "clk_div_cfgbus",
86 CLK_SET_RATE_PARENT, 0x10, 13, 0, },
87 { HI3660_PCLK_GPIO14, "pclk_gpio14", "clk_div_cfgbus",
88 CLK_SET_RATE_PARENT, 0x10, 14, 0, },
89 { HI3660_PCLK_GPIO15, "pclk_gpio15", "clk_div_cfgbus",
90 CLK_SET_RATE_PARENT, 0x10, 15, 0, },
91 { HI3660_PCLK_GPIO16, "pclk_gpio16", "clk_div_cfgbus",
92 CLK_SET_RATE_PARENT, 0x10, 16, 0, },
93 { HI3660_PCLK_GPIO17, "pclk_gpio17", "clk_div_cfgbus",
94 CLK_SET_RATE_PARENT, 0x10, 17, 0, },
95 { HI3660_PCLK_GPIO18, "pclk_gpio18", "clk_div_ioperi",
96 CLK_SET_RATE_PARENT, 0x10, 18, 0, },
97 { HI3660_PCLK_GPIO19, "pclk_gpio19", "clk_div_ioperi",
98 CLK_SET_RATE_PARENT, 0x10, 19, 0, },
99 { HI3660_PCLK_GPIO20, "pclk_gpio20", "clk_div_cfgbus",
100 CLK_SET_RATE_PARENT, 0x10, 20, 0, },
101 { HI3660_PCLK_GPIO21, "pclk_gpio21", "clk_div_cfgbus",
102 CLK_SET_RATE_PARENT, 0x10, 21, 0, },
103 { HI3660_CLK_GATE_SPI3, "clk_gate_spi3", "clk_div_ioperi",
104 CLK_SET_RATE_PARENT, 0x10, 30, 0, },
105 { HI3660_CLK_GATE_I2C7, "clk_gate_i2c7", "clk_mux_i2c",
106 CLK_SET_RATE_PARENT, 0x10, 31, 0, },
107 { HI3660_CLK_GATE_I2C3, "clk_gate_i2c3", "clk_mux_i2c",
108 CLK_SET_RATE_PARENT, 0x20, 7, 0, },
109 { HI3660_CLK_GATE_SPI1, "clk_gate_spi1", "clk_mux_spi",
110 CLK_SET_RATE_PARENT, 0x20, 9, 0, },
111 { HI3660_CLK_GATE_UART1, "clk_gate_uart1", "clk_mux_uarth",
112 CLK_SET_RATE_PARENT, 0x20, 11, 0, },
113 { HI3660_CLK_GATE_UART2, "clk_gate_uart2", "clk_mux_uart1",
114 CLK_SET_RATE_PARENT, 0x20, 12, 0, },
115 { HI3660_CLK_GATE_UART4, "clk_gate_uart4", "clk_mux_uarth",
116 CLK_SET_RATE_PARENT, 0x20, 14, 0, },
117 { HI3660_CLK_GATE_UART5, "clk_gate_uart5", "clk_mux_uart1",
118 CLK_SET_RATE_PARENT, 0x20, 15, 0, },
119 { HI3660_CLK_GATE_I2C4, "clk_gate_i2c4", "clk_mux_i2c",
120 CLK_SET_RATE_PARENT, 0x20, 27, 0, },
121 { HI3660_CLK_GATE_DMAC, "clk_gate_dmac", "clk_div_sysbus",
122 CLK_SET_RATE_PARENT, 0x30, 1, 0, },
123 { HI3660_PCLK_GATE_DSS, "pclk_gate_dss", "clk_div_cfgbus",
124 CLK_SET_RATE_PARENT, 0x30, 12, 0, },
125 { HI3660_ACLK_GATE_DSS, "aclk_gate_dss", "clk_gate_vivobus",
126 CLK_SET_RATE_PARENT, 0x30, 13, 0, },
127 { HI3660_CLK_GATE_LDI1, "clk_gate_ldi1", "clk_div_ldi1",
128 CLK_SET_RATE_PARENT, 0x30, 14, 0, },
129 { HI3660_CLK_GATE_LDI0, "clk_gate_ldi0", "clk_div_ldi0",
130 CLK_SET_RATE_PARENT, 0x30, 15, 0, },
131 { HI3660_CLK_GATE_VIVOBUS, "clk_gate_vivobus", "clk_div_vivobus",
132 CLK_SET_RATE_PARENT, 0x30, 16, 0, },
133 { HI3660_CLK_GATE_EDC0, "clk_gate_edc0", "clk_div_edc0",
134 CLK_SET_RATE_PARENT, 0x30, 17, 0, },
135 { HI3660_CLK_GATE_TXDPHY0_CFG, "clk_gate_txdphy0_cfg", "clkin_sys",
136 CLK_SET_RATE_PARENT, 0x30, 28, 0, },
137 { HI3660_CLK_GATE_TXDPHY0_REF, "clk_gate_txdphy0_ref", "clkin_sys",
138 CLK_SET_RATE_PARENT, 0x30, 29, 0, },
139 { HI3660_CLK_GATE_TXDPHY1_CFG, "clk_gate_txdphy1_cfg", "clkin_sys",
140 CLK_SET_RATE_PARENT, 0x30, 30, 0, },
141 { HI3660_CLK_GATE_TXDPHY1_REF, "clk_gate_txdphy1_ref", "clkin_sys",
142 CLK_SET_RATE_PARENT, 0x30, 31, 0, },
143 { HI3660_ACLK_GATE_USB3OTG, "aclk_gate_usb3otg", "clk_div_mmc0bus",
144 CLK_SET_RATE_PARENT, 0x40, 1, 0, },
145 { HI3660_CLK_GATE_SPI4, "clk_gate_spi4", "clk_mux_spi",
146 CLK_SET_RATE_PARENT, 0x40, 4, 0, },
147 { HI3660_CLK_GATE_SD, "clk_gate_sd", "clk_mux_sd_sys",
148 CLK_SET_RATE_PARENT, 0x40, 17, 0, },
149 { HI3660_CLK_GATE_SDIO0, "clk_gate_sdio0", "clk_mux_sdio_sys",
150 CLK_SET_RATE_PARENT, 0x40, 19, 0, },
151 { HI3660_CLK_GATE_UFS_SUBSYS, "clk_gate_ufs_subsys", "clk_div_sysbus",
152 CLK_SET_RATE_PARENT, 0x50, 21, 0, },
153 { HI3660_PCLK_GATE_DSI0, "pclk_gate_dsi0", "clk_div_cfgbus",
154 CLK_SET_RATE_PARENT, 0x50, 28, 0, },
155 { HI3660_PCLK_GATE_DSI1, "pclk_gate_dsi1", "clk_div_cfgbus",
156 CLK_SET_RATE_PARENT, 0x50, 29, 0, },
157 { HI3660_ACLK_GATE_PCIE, "aclk_gate_pcie", "clk_div_mmc1bus",
158 CLK_SET_RATE_PARENT, 0x420, 5, 0, },
159 { HI3660_PCLK_GATE_PCIE_SYS, "pclk_gate_pcie_sys", "clk_div_mmc1bus",
160 CLK_SET_RATE_PARENT, 0x420, 7, 0, },
161 { HI3660_CLK_GATE_PCIEAUX, "clk_gate_pcieaux", "clkin_sys",
162 CLK_SET_RATE_PARENT, 0x420, 8, 0, },
163 { HI3660_PCLK_GATE_PCIE_PHY, "pclk_gate_pcie_phy", "clk_div_mmc1bus",
164 CLK_SET_RATE_PARENT, 0x420, 9, 0, },
167 static const struct hisi_gate_clock hi3660_crgctrl_gate_clks[] = {
168 { HI3660_CLK_ANDGT_LDI0, "clk_andgt_ldi0", "clk_mux_ldi0",
169 CLK_SET_RATE_PARENT, 0xf0, 6, CLK_GATE_HIWORD_MASK, },
170 { HI3660_CLK_ANDGT_LDI1, "clk_andgt_ldi1", "clk_mux_ldi1",
171 CLK_SET_RATE_PARENT, 0xf0, 7, CLK_GATE_HIWORD_MASK, },
172 { HI3660_CLK_ANDGT_EDC0, "clk_andgt_edc0", "clk_mux_edc0",
173 CLK_SET_RATE_PARENT, 0xf0, 8, CLK_GATE_HIWORD_MASK, },
174 { HI3660_CLK_GATE_UFSPHY_GT, "clk_gate_ufsphy_gt", "clk_div_ufsperi",
175 CLK_SET_RATE_PARENT, 0xf4, 1, CLK_GATE_HIWORD_MASK, },
176 { HI3660_CLK_ANDGT_MMC, "clk_andgt_mmc", "clk_mux_mmc_pll",
177 CLK_SET_RATE_PARENT, 0xf4, 2, CLK_GATE_HIWORD_MASK, },
178 { HI3660_CLK_ANDGT_SD, "clk_andgt_sd", "clk_mux_sd_pll",
179 CLK_SET_RATE_PARENT, 0xf4, 3, CLK_GATE_HIWORD_MASK, },
180 { HI3660_CLK_A53HPM_ANDGT, "clk_a53hpm_andgt", "clk_mux_a53hpm",
181 CLK_SET_RATE_PARENT, 0xf4, 7, CLK_GATE_HIWORD_MASK, },
182 { HI3660_CLK_ANDGT_SDIO, "clk_andgt_sdio", "clk_mux_sdio_pll",
183 CLK_SET_RATE_PARENT, 0xf4, 8, CLK_GATE_HIWORD_MASK, },
184 { HI3660_CLK_ANDGT_UART0, "clk_andgt_uart0", "clk_div_320m",
185 CLK_SET_RATE_PARENT, 0xf4, 9, CLK_GATE_HIWORD_MASK, },
186 { HI3660_CLK_ANDGT_UART1, "clk_andgt_uart1", "clk_div_320m",
187 CLK_SET_RATE_PARENT, 0xf4, 10, CLK_GATE_HIWORD_MASK, },
188 { HI3660_CLK_ANDGT_UARTH, "clk_andgt_uarth", "clk_div_320m",
189 CLK_SET_RATE_PARENT, 0xf4, 11, CLK_GATE_HIWORD_MASK, },
190 { HI3660_CLK_ANDGT_SPI, "clk_andgt_spi", "clk_div_320m",
191 CLK_SET_RATE_PARENT, 0xf4, 13, CLK_GATE_HIWORD_MASK, },
192 { HI3660_CLK_VIVOBUS_ANDGT, "clk_vivobus_andgt", "clk_mux_vivobus",
193 CLK_SET_RATE_PARENT, 0xf8, 1, CLK_GATE_HIWORD_MASK, },
194 { HI3660_CLK_AOMM_ANDGT, "clk_aomm_andgt", "clk_ppll2",
195 CLK_SET_RATE_PARENT, 0xf8, 3, CLK_GATE_HIWORD_MASK, },
196 { HI3660_CLK_320M_PLL_GT, "clk_320m_pll_gt", "clk_mux_320m",
197 CLK_SET_RATE_PARENT, 0xf8, 10, 0, },
198 { HI3660_AUTODIV_EMMC0BUS, "autodiv_emmc0bus", "autodiv_sysbus",
199 CLK_SET_RATE_PARENT, 0x404, 1, CLK_GATE_HIWORD_MASK, },
200 { HI3660_AUTODIV_SYSBUS, "autodiv_sysbus", "clk_div_sysbus",
201 CLK_SET_RATE_PARENT, 0x404, 5, CLK_GATE_HIWORD_MASK, },
202 { HI3660_CLK_GATE_UFSPHY_CFG, "clk_gate_ufsphy_cfg",
203 "clk_div_ufsphy_cfg", CLK_SET_RATE_PARENT, 0x420, 12, 0, },
204 { HI3660_CLK_GATE_UFSIO_REF, "clk_gate_ufsio_ref",
205 "clk_gate_ufs_tcxo_en", CLK_SET_RATE_PARENT, 0x420, 14, 0, },
208 static const char *const
209 clk_mux_sdio_sys_p[] = {"clk_factor_mmc", "clk_div_sdio",};
210 static const char *const
211 clk_mux_sd_sys_p[] = {"clk_factor_mmc", "clk_div_sd",};
212 static const char *const
213 clk_mux_pll_p[] = {"clk_ppll0", "clk_ppll1", "clk_ppll2", "clk_ppll2",};
214 static const char *const
215 clk_mux_pll0123_p[] = {"clk_ppll0", "clk_ppll1", "clk_ppll2", "clk_ppll3",};
216 static const char *const
217 clk_mux_edc0_p[] = {"clk_inv", "clk_ppll0", "clk_ppll1", "clk_inv",
218 "clk_ppll2", "clk_inv", "clk_inv", "clk_inv",
219 "clk_ppll3", "clk_inv", "clk_inv", "clk_inv",
220 "clk_inv", "clk_inv", "clk_inv", "clk_inv",};
221 static const char *const
222 clk_mux_ldi0_p[] = {"clk_inv", "clk_ppll0", "clk_ppll2", "clk_inv",
223 "clk_ppll1", "clk_inv", "clk_inv", "clk_inv",
224 "clk_ppll3", "clk_inv", "clk_inv", "clk_inv",
225 "clk_inv", "clk_inv", "clk_inv", "clk_inv",};
226 static const char *const
227 clk_mux_uart0_p[] = {"clkin_sys", "clk_div_uart0",};
228 static const char *const
229 clk_mux_uart1_p[] = {"clkin_sys", "clk_div_uart1",};
230 static const char *const
231 clk_mux_uarth_p[] = {"clkin_sys", "clk_div_uarth",};
232 static const char *const
233 clk_mux_pll02p[] = {"clk_ppll0", "clk_ppll2",};
234 static const char *const
235 clk_mux_ioperi_p[] = {"clk_div_320m", "clk_div_a53hpm",};
236 static const char *const
237 clk_mux_spi_p[] = {"clkin_sys", "clk_div_spi",};
238 static const char *const
239 clk_mux_i2c_p[] = {"clkin_sys", "clk_div_i2c",};
241 static const struct hisi_mux_clock hi3660_crgctrl_mux_clks[] = {
242 { HI3660_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sdio_sys_p,
243 ARRAY_SIZE(clk_mux_sdio_sys_p), CLK_SET_RATE_PARENT, 0xac, 0, 1,
244 CLK_MUX_HIWORD_MASK, },
245 { HI3660_CLK_MUX_UART0, "clk_mux_uart0", clk_mux_uart0_p,
246 ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT, 0xac, 2, 1,
247 CLK_MUX_HIWORD_MASK, },
248 { HI3660_CLK_MUX_UART1, "clk_mux_uart1", clk_mux_uart1_p,
249 ARRAY_SIZE(clk_mux_uart1_p), CLK_SET_RATE_PARENT, 0xac, 3, 1,
250 CLK_MUX_HIWORD_MASK, },
251 { HI3660_CLK_MUX_UARTH, "clk_mux_uarth", clk_mux_uarth_p,
252 ARRAY_SIZE(clk_mux_uarth_p), CLK_SET_RATE_PARENT, 0xac, 4, 1,
253 CLK_MUX_HIWORD_MASK, },
254 { HI3660_CLK_MUX_SPI, "clk_mux_spi", clk_mux_spi_p,
255 ARRAY_SIZE(clk_mux_spi_p), CLK_SET_RATE_PARENT, 0xac, 8, 1,
256 CLK_MUX_HIWORD_MASK, },
257 { HI3660_CLK_MUX_I2C, "clk_mux_i2c", clk_mux_i2c_p,
258 ARRAY_SIZE(clk_mux_i2c_p), CLK_SET_RATE_PARENT, 0xac, 13, 1,
259 CLK_MUX_HIWORD_MASK, },
260 { HI3660_CLK_MUX_MMC_PLL, "clk_mux_mmc_pll", clk_mux_pll02p,
261 ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0xb4, 0, 1,
262 CLK_MUX_HIWORD_MASK, },
263 { HI3660_CLK_MUX_LDI1, "clk_mux_ldi1", clk_mux_ldi0_p,
264 ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT, 0xb4, 8, 4,
265 CLK_MUX_HIWORD_MASK, },
266 { HI3660_CLK_MUX_LDI0, "clk_mux_ldi0", clk_mux_ldi0_p,
267 ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT, 0xb4, 12, 4,
268 CLK_MUX_HIWORD_MASK, },
269 { HI3660_CLK_MUX_SD_PLL, "clk_mux_sd_pll", clk_mux_pll_p,
270 ARRAY_SIZE(clk_mux_pll_p), CLK_SET_RATE_PARENT, 0xb8, 4, 2,
271 CLK_MUX_HIWORD_MASK, },
272 { HI3660_CLK_MUX_SD_SYS, "clk_mux_sd_sys", clk_mux_sd_sys_p,
273 ARRAY_SIZE(clk_mux_sd_sys_p), CLK_SET_RATE_PARENT, 0xb8, 6, 1,
274 CLK_MUX_HIWORD_MASK, },
275 { HI3660_CLK_MUX_EDC0, "clk_mux_edc0", clk_mux_edc0_p,
276 ARRAY_SIZE(clk_mux_edc0_p), CLK_SET_RATE_PARENT, 0xbc, 6, 4,
277 CLK_MUX_HIWORD_MASK, },
278 { HI3660_CLK_MUX_SDIO_SYS, "clk_mux_sdio_sys", clk_mux_sdio_sys_p,
279 ARRAY_SIZE(clk_mux_sdio_sys_p), CLK_SET_RATE_PARENT, 0xc0, 6, 1,
280 CLK_MUX_HIWORD_MASK, },
281 { HI3660_CLK_MUX_SDIO_PLL, "clk_mux_sdio_pll", clk_mux_pll_p,
282 ARRAY_SIZE(clk_mux_pll_p), CLK_SET_RATE_PARENT, 0xc0, 4, 2,
283 CLK_MUX_HIWORD_MASK, },
284 { HI3660_CLK_MUX_VIVOBUS, "clk_mux_vivobus", clk_mux_pll0123_p,
285 ARRAY_SIZE(clk_mux_pll0123_p), CLK_SET_RATE_PARENT, 0xd0, 12, 2,
286 CLK_MUX_HIWORD_MASK, },
287 { HI3660_CLK_MUX_A53HPM, "clk_mux_a53hpm", clk_mux_pll02p,
288 ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0xd4, 9, 1,
289 CLK_MUX_HIWORD_MASK, },
290 { HI3660_CLK_MUX_320M, "clk_mux_320m", clk_mux_pll02p,
291 ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0x100, 0, 1,
292 CLK_MUX_HIWORD_MASK, },
293 { HI3660_CLK_MUX_IOPERI, "clk_mux_ioperi", clk_mux_ioperi_p,
294 ARRAY_SIZE(clk_mux_ioperi_p), CLK_SET_RATE_PARENT, 0x108, 10, 1,
295 CLK_MUX_HIWORD_MASK, },
298 static const struct hisi_divider_clock hi3660_crgctrl_divider_clks[] = {
299 { HI3660_CLK_DIV_UART0, "clk_div_uart0", "clk_andgt_uart0",
300 CLK_SET_RATE_PARENT, 0xb0, 4, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
301 { HI3660_CLK_DIV_UART1, "clk_div_uart1", "clk_andgt_uart1",
302 CLK_SET_RATE_PARENT, 0xb0, 8, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
303 { HI3660_CLK_DIV_UARTH, "clk_div_uarth", "clk_andgt_uarth",
304 CLK_SET_RATE_PARENT, 0xb0, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
305 { HI3660_CLK_DIV_MMC, "clk_div_mmc", "clk_andgt_mmc",
306 CLK_SET_RATE_PARENT, 0xb4, 3, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
307 { HI3660_CLK_DIV_SD, "clk_div_sd", "clk_andgt_sd",
308 CLK_SET_RATE_PARENT, 0xb8, 0, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
309 { HI3660_CLK_DIV_EDC0, "clk_div_edc0", "clk_andgt_edc0",
310 CLK_SET_RATE_PARENT, 0xbc, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
311 { HI3660_CLK_DIV_LDI0, "clk_div_ldi0", "clk_andgt_ldi0",
312 CLK_SET_RATE_PARENT, 0xbc, 10, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
313 { HI3660_CLK_DIV_SDIO, "clk_div_sdio", "clk_andgt_sdio",
314 CLK_SET_RATE_PARENT, 0xc0, 0, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
315 { HI3660_CLK_DIV_LDI1, "clk_div_ldi1", "clk_andgt_ldi1",
316 CLK_SET_RATE_PARENT, 0xc0, 8, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
317 { HI3660_CLK_DIV_SPI, "clk_div_spi", "clk_andgt_spi",
318 CLK_SET_RATE_PARENT, 0xc4, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
319 { HI3660_CLK_DIV_VIVOBUS, "clk_div_vivobus", "clk_vivobus_andgt",
320 CLK_SET_RATE_PARENT, 0xd0, 7, 5, CLK_DIVIDER_HIWORD_MASK, 0, },
321 { HI3660_CLK_DIV_I2C, "clk_div_i2c", "clk_div_320m",
322 CLK_SET_RATE_PARENT, 0xe8, 4, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
323 { HI3660_CLK_DIV_UFSPHY, "clk_div_ufsphy_cfg", "clk_gate_ufsphy_gt",
324 CLK_SET_RATE_PARENT, 0xe8, 9, 2, CLK_DIVIDER_HIWORD_MASK, 0, },
325 { HI3660_CLK_DIV_CFGBUS, "clk_div_cfgbus", "clk_div_sysbus",
326 CLK_SET_RATE_PARENT, 0xec, 0, 2, CLK_DIVIDER_HIWORD_MASK, 0, },
327 { HI3660_CLK_DIV_MMC0BUS, "clk_div_mmc0bus", "autodiv_emmc0bus",
328 CLK_SET_RATE_PARENT, 0xec, 2, 1, CLK_DIVIDER_HIWORD_MASK, 0, },
329 { HI3660_CLK_DIV_MMC1BUS, "clk_div_mmc1bus", "clk_div_sysbus",
330 CLK_SET_RATE_PARENT, 0xec, 3, 1, CLK_DIVIDER_HIWORD_MASK, 0, },
331 { HI3660_CLK_DIV_UFSPERI, "clk_div_ufsperi", "clk_gate_ufs_subsys",
332 CLK_SET_RATE_PARENT, 0xec, 14, 1, CLK_DIVIDER_HIWORD_MASK, 0, },
333 { HI3660_CLK_DIV_AOMM, "clk_div_aomm", "clk_aomm_andgt",
334 CLK_SET_RATE_PARENT, 0x100, 7, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
335 { HI3660_CLK_DIV_IOPERI, "clk_div_ioperi", "clk_mux_ioperi",
336 CLK_SET_RATE_PARENT, 0x108, 11, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
340 /* pmu register need shift 2 bits */
341 static const struct hisi_gate_clock hi3660_pmu_gate_clks[] = {
342 { HI3660_GATE_ABB_192, "clk_gate_abb_192", "clkin_sys",
343 CLK_SET_RATE_PARENT, (0x10a << 2), 3, 0, },
347 static const struct hisi_gate_clock hi3660_pctrl_gate_clks[] = {
348 { HI3660_GATE_UFS_TCXO_EN, "clk_gate_ufs_tcxo_en",
349 "clk_gate_abb_192", CLK_SET_RATE_PARENT, 0x10, 0,
350 CLK_GATE_HIWORD_MASK, },
351 { HI3660_GATE_USB_TCXO_EN, "clk_gate_usb_tcxo_en", "clk_gate_abb_192",
352 CLK_SET_RATE_PARENT, 0x10, 1, CLK_GATE_HIWORD_MASK, },
356 static const struct hisi_gate_clock hi3660_sctrl_gate_sep_clks[] = {
357 { HI3660_PCLK_AO_GPIO0, "pclk_ao_gpio0", "clk_div_aobus",
358 CLK_SET_RATE_PARENT, 0x160, 11, 0, },
359 { HI3660_PCLK_AO_GPIO1, "pclk_ao_gpio1", "clk_div_aobus",
360 CLK_SET_RATE_PARENT, 0x160, 12, 0, },
361 { HI3660_PCLK_AO_GPIO2, "pclk_ao_gpio2", "clk_div_aobus",
362 CLK_SET_RATE_PARENT, 0x160, 13, 0, },
363 { HI3660_PCLK_AO_GPIO3, "pclk_ao_gpio3", "clk_div_aobus",
364 CLK_SET_RATE_PARENT, 0x160, 14, 0, },
365 { HI3660_PCLK_AO_GPIO4, "pclk_ao_gpio4", "clk_div_aobus",
366 CLK_SET_RATE_PARENT, 0x160, 21, 0, },
367 { HI3660_PCLK_AO_GPIO5, "pclk_ao_gpio5", "clk_div_aobus",
368 CLK_SET_RATE_PARENT, 0x160, 22, 0, },
369 { HI3660_PCLK_AO_GPIO6, "pclk_ao_gpio6", "clk_div_aobus",
370 CLK_SET_RATE_PARENT, 0x160, 25, 0, },
371 { HI3660_PCLK_GATE_MMBUF, "pclk_gate_mmbuf", "pclk_div_mmbuf",
372 CLK_SET_RATE_PARENT, 0x170, 23, 0, },
373 { HI3660_CLK_GATE_DSS_AXI_MM, "clk_gate_dss_axi_mm", "aclk_mux_mmbuf",
374 CLK_SET_RATE_PARENT, 0x170, 24, 0, },
377 static const struct hisi_gate_clock hi3660_sctrl_gate_clks[] = {
378 { HI3660_PCLK_MMBUF_ANDGT, "pclk_mmbuf_andgt", "clk_sw_mmbuf",
379 CLK_SET_RATE_PARENT, 0x258, 7, CLK_GATE_HIWORD_MASK, },
380 { HI3660_CLK_MMBUF_PLL_ANDGT, "clk_mmbuf_pll_andgt", "clk_ppll0",
381 CLK_SET_RATE_PARENT, 0x260, 11, CLK_DIVIDER_HIWORD_MASK, 0, },
382 { HI3660_CLK_FLL_MMBUF_ANDGT, "clk_fll_mmbuf_andgt", "clk_fll_src",
383 CLK_SET_RATE_PARENT, 0x260, 12, CLK_DIVIDER_HIWORD_MASK, 0, },
384 { HI3660_CLK_SYS_MMBUF_ANDGT, "clk_sys_mmbuf_andgt", "clkin_sys",
385 CLK_SET_RATE_PARENT, 0x260, 13, CLK_DIVIDER_HIWORD_MASK, 0, },
386 { HI3660_CLK_GATE_PCIEPHY_GT, "clk_gate_pciephy_gt", "clk_ppll0",
387 CLK_SET_RATE_PARENT, 0x268, 11, CLK_DIVIDER_HIWORD_MASK, 0, },
390 static const char *const
391 aclk_mux_mmbuf_p[] = {"aclk_div_mmbuf", "clk_gate_aomm",};
392 static const char *const
393 clk_sw_mmbuf_p[] = {"clk_sys_mmbuf_andgt", "clk_fll_mmbuf_andgt",
394 "aclk_mux_mmbuf", "aclk_mux_mmbuf"};
396 static const struct hisi_mux_clock hi3660_sctrl_mux_clks[] = {
397 { HI3660_ACLK_MUX_MMBUF, "aclk_mux_mmbuf", aclk_mux_mmbuf_p,
398 ARRAY_SIZE(aclk_mux_mmbuf_p), CLK_SET_RATE_PARENT, 0x250, 12, 1,
399 CLK_MUX_HIWORD_MASK, },
400 { HI3660_CLK_SW_MMBUF, "clk_sw_mmbuf", clk_sw_mmbuf_p,
401 ARRAY_SIZE(clk_sw_mmbuf_p), CLK_SET_RATE_PARENT, 0x258, 8, 2,
402 CLK_MUX_HIWORD_MASK, },
405 static const struct hisi_divider_clock hi3660_sctrl_divider_clks[] = {
406 { HI3660_CLK_DIV_AOBUS, "clk_div_aobus", "clk_ppll0",
407 CLK_SET_RATE_PARENT, 0x254, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
408 { HI3660_PCLK_DIV_MMBUF, "pclk_div_mmbuf", "pclk_mmbuf_andgt",
409 CLK_SET_RATE_PARENT, 0x258, 10, 2, CLK_DIVIDER_HIWORD_MASK, 0, },
410 { HI3660_ACLK_DIV_MMBUF, "aclk_div_mmbuf", "clk_mmbuf_pll_andgt",
411 CLK_SET_RATE_PARENT, 0x258, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
412 { HI3660_CLK_DIV_PCIEPHY, "clk_div_pciephy", "clk_gate_pciephy_gt",
413 CLK_SET_RATE_PARENT, 0x268, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
417 static const struct hisi_gate_clock hi3660_iomcu_gate_sep_clks[] = {
418 { HI3660_CLK_I2C0_IOMCU, "clk_i2c0_iomcu", "clk_fll_src",
419 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
420 { HI3660_CLK_I2C1_IOMCU, "clk_i2c1_iomcu", "clk_fll_src",
421 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
422 { HI3660_CLK_I2C2_IOMCU, "clk_i2c2_iomcu", "clk_fll_src",
423 CLK_SET_RATE_PARENT, 0x10, 5, 0, },
424 { HI3660_CLK_I2C6_IOMCU, "clk_i2c6_iomcu", "clk_fll_src",
425 CLK_SET_RATE_PARENT, 0x10, 27, 0, },
426 { HI3660_CLK_IOMCU_PERI0, "iomcu_peri0", "clk_ppll0",
427 CLK_SET_RATE_PARENT, 0x90, 0, 0, },
430 static void hi3660_clk_iomcu_init(struct device_node *np)
432 struct hisi_clock_data *clk_data;
433 int nr = ARRAY_SIZE(hi3660_iomcu_gate_sep_clks);
435 clk_data = hisi_clk_init(np, nr);
439 hisi_clk_register_gate_sep(hi3660_iomcu_gate_sep_clks,
440 ARRAY_SIZE(hi3660_iomcu_gate_sep_clks),
444 static void hi3660_clk_pmuctrl_init(struct device_node *np)
446 struct hisi_clock_data *clk_data;
447 int nr = ARRAY_SIZE(hi3660_pmu_gate_clks);
449 clk_data = hisi_clk_init(np, nr);
453 hisi_clk_register_gate(hi3660_pmu_gate_clks,
454 ARRAY_SIZE(hi3660_pmu_gate_clks), clk_data);
457 static void hi3660_clk_pctrl_init(struct device_node *np)
459 struct hisi_clock_data *clk_data;
460 int nr = ARRAY_SIZE(hi3660_pctrl_gate_clks);
462 clk_data = hisi_clk_init(np, nr);
465 hisi_clk_register_gate(hi3660_pctrl_gate_clks,
466 ARRAY_SIZE(hi3660_pctrl_gate_clks), clk_data);
469 static void hi3660_clk_sctrl_init(struct device_node *np)
471 struct hisi_clock_data *clk_data;
472 int nr = ARRAY_SIZE(hi3660_sctrl_gate_clks) +
473 ARRAY_SIZE(hi3660_sctrl_gate_sep_clks) +
474 ARRAY_SIZE(hi3660_sctrl_mux_clks) +
475 ARRAY_SIZE(hi3660_sctrl_divider_clks);
477 clk_data = hisi_clk_init(np, nr);
480 hisi_clk_register_gate(hi3660_sctrl_gate_clks,
481 ARRAY_SIZE(hi3660_sctrl_gate_clks), clk_data);
482 hisi_clk_register_gate_sep(hi3660_sctrl_gate_sep_clks,
483 ARRAY_SIZE(hi3660_sctrl_gate_sep_clks),
485 hisi_clk_register_mux(hi3660_sctrl_mux_clks,
486 ARRAY_SIZE(hi3660_sctrl_mux_clks), clk_data);
487 hisi_clk_register_divider(hi3660_sctrl_divider_clks,
488 ARRAY_SIZE(hi3660_sctrl_divider_clks),
492 static void hi3660_clk_crgctrl_init(struct device_node *np)
494 struct hisi_clock_data *clk_data;
495 int nr = ARRAY_SIZE(hi3660_fixed_rate_clks) +
496 ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks) +
497 ARRAY_SIZE(hi3660_crgctrl_gate_clks) +
498 ARRAY_SIZE(hi3660_crgctrl_mux_clks) +
499 ARRAY_SIZE(hi3660_crg_fixed_factor_clks) +
500 ARRAY_SIZE(hi3660_crgctrl_divider_clks);
502 clk_data = hisi_clk_init(np, nr);
506 hisi_clk_register_fixed_rate(hi3660_fixed_rate_clks,
507 ARRAY_SIZE(hi3660_fixed_rate_clks),
509 hisi_clk_register_gate_sep(hi3660_crgctrl_gate_sep_clks,
510 ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks),
512 hisi_clk_register_gate(hi3660_crgctrl_gate_clks,
513 ARRAY_SIZE(hi3660_crgctrl_gate_clks),
515 hisi_clk_register_mux(hi3660_crgctrl_mux_clks,
516 ARRAY_SIZE(hi3660_crgctrl_mux_clks),
518 hisi_clk_register_fixed_factor(hi3660_crg_fixed_factor_clks,
519 ARRAY_SIZE(hi3660_crg_fixed_factor_clks),
521 hisi_clk_register_divider(hi3660_crgctrl_divider_clks,
522 ARRAY_SIZE(hi3660_crgctrl_divider_clks),
526 static const struct of_device_id hi3660_clk_match_table[] = {
527 { .compatible = "hisilicon,hi3660-crgctrl",
528 .data = hi3660_clk_crgctrl_init },
529 { .compatible = "hisilicon,hi3660-pctrl",
530 .data = hi3660_clk_pctrl_init },
531 { .compatible = "hisilicon,hi3660-pmuctrl",
532 .data = hi3660_clk_pmuctrl_init },
533 { .compatible = "hisilicon,hi3660-sctrl",
534 .data = hi3660_clk_sctrl_init },
535 { .compatible = "hisilicon,hi3660-iomcu",
536 .data = hi3660_clk_iomcu_init },
540 static int hi3660_clk_probe(struct platform_device *pdev)
542 struct device *dev = &pdev->dev;
543 struct device_node *np = pdev->dev.of_node;
544 void (*init_func)(struct device_node *np);
546 init_func = of_device_get_match_data(dev);
555 static struct platform_driver hi3660_clk_driver = {
556 .probe = hi3660_clk_probe,
558 .name = "hi3660-clk",
559 .of_match_table = hi3660_clk_match_table,
563 static int __init hi3660_clk_init(void)
565 return platform_driver_register(&hi3660_clk_driver);
567 core_initcall(hi3660_clk_init);