drivers/clk/mediatek/clk-mt2701.c

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Shunli Wang <shunli.wang@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/clk-provider.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_device.h>
  19 #include <linux/platform_device.h>
  20
  21 #include "clk-mtk.h"
  22 #include "clk-gate.h"
  23
  24 #include <dt-bindings/clock/mt2701-clk.h>
  25
  26 /*
  27  * For some clocks, we don't care what their actual rates are. And these
  28  * clocks may change their rate on different products or different scenarios.
  29  * So we model these clocks' rate as 0, to denote it's not an actual rate.
  30  */
  31 #define DUMMY_RATE              0
  32
  33 static DEFINE_SPINLOCK(mt2701_clk_lock);
  34
  35 static const struct mtk_fixed_clk top_fixed_clks[] = {
  36         FIXED_CLK(CLK_TOP_DPI, "dpi_ck", "clk26m",
  37                 108 * MHZ),
  38         FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", "clk26m",
  39                 400 * MHZ),
  40         FIXED_CLK(CLK_TOP_VENCPLL, "vencpll_ck", "clk26m",
  41                 295750000),
  42         FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, "hdmi_0_pix340m", "clk26m",
  43                 340 * MHZ),
  44         FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, "hdmi_0_deep340m", "clk26m",
  45                 340 * MHZ),
  46         FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m",
  47                 340 * MHZ),
  48         FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_dig_cts", "clk26m",
  49                 300 * MHZ),
  50         FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m",
  51                 27 * MHZ),
  52         FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m",
  53                 416 * MHZ),
  54         FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, "dsi0_lntc_dsi", "clk26m",
  55                 143 * MHZ),
  56         FIXED_CLK(CLK_TOP_HDMI_SCL_RX, "hdmi_scl_rx", "clk26m",
  57                 27 * MHZ),
  58         FIXED_CLK(CLK_TOP_AUD_EXT1, "aud_ext1", "clk26m",
  59                 DUMMY_RATE),
  60         FIXED_CLK(CLK_TOP_AUD_EXT2, "aud_ext2", "clk26m",
  61                 DUMMY_RATE),
  62         FIXED_CLK(CLK_TOP_NFI1X_PAD, "nfi1x_pad", "clk26m",
  63                 DUMMY_RATE),
  64 };
  65
  66 static const struct mtk_fixed_factor top_fixed_divs[] = {
  67         FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
  68         FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
  69         FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
  70         FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
  71         FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
  72         FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
  73         FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
  74         FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
  75         FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
  76         FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
  77         FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
  78         FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
  79         FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
  80         FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
  81         FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
  82         FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
  83
  84         FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1),
  85         FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
  86         FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
  87         FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
  88         FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
  89         FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
  90         FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll", 1, 52),
  91         FACTOR(CLK_TOP_UNIVPLL_D108, "univpll_d108", "univpll", 1, 108),
  92         FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
  93         FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
  94         FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
  95         FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
  96         FACTOR(CLK_TOP_8BDAC, "8bdac_ck", "univpll_d2", 1, 1),
  97         FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
  98         FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
  99         FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
 100         FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll_d3", 1, 16),
 101         FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32),
 102         FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
 103         FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
 104         FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
 105
 106         FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
 107         FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
 108         FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
 109         FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
 110
 111         FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
 112         FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
 113
 114         FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "dmpll_ck", 1, 2),
 115         FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "dmpll_ck", 1, 4),
 116         FACTOR(CLK_TOP_DMPLL_X2, "dmpll_x2", "dmpll_ck", 1, 1),
 117
 118         FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
 119         FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
 120         FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
 121
 122         FACTOR(CLK_TOP_VDECPLL, "vdecpll_ck", "vdecpll", 1, 1),
 123         FACTOR(CLK_TOP_TVD2PLL, "tvd2pll_ck", "tvd2pll", 1, 1),
 124         FACTOR(CLK_TOP_TVD2PLL_D2, "tvd2pll_d2", "tvd2pll", 1, 2),
 125
 126         FACTOR(CLK_TOP_MIPIPLL, "mipipll", "dpi_ck", 1, 1),
 127         FACTOR(CLK_TOP_MIPIPLL_D2, "mipipll_d2", "dpi_ck", 1, 2),
 128         FACTOR(CLK_TOP_MIPIPLL_D4, "mipipll_d4", "dpi_ck", 1, 4),
 129
 130         FACTOR(CLK_TOP_HDMIPLL, "hdmipll_ck", "hdmitx_dig_cts", 1, 1),
 131         FACTOR(CLK_TOP_HDMIPLL_D2, "hdmipll_d2", "hdmitx_dig_cts", 1, 2),
 132         FACTOR(CLK_TOP_HDMIPLL_D3, "hdmipll_d3", "hdmitx_dig_cts", 1, 3),
 133
 134         FACTOR(CLK_TOP_ARMPLL_1P3G, "armpll_1p3g_ck", "armpll", 1, 1),
 135
 136         FACTOR(CLK_TOP_AUDPLL, "audpll", "audpll_sel", 1, 1),
 137         FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll_sel", 1, 4),
 138         FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll_sel", 1, 8),
 139         FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll_sel", 1, 16),
 140         FACTOR(CLK_TOP_AUDPLL_D24, "audpll_d24", "audpll_sel", 1, 24),
 141
 142         FACTOR(CLK_TOP_AUD1PLL_98M, "aud1pll_98m_ck", "aud1pll", 1, 3),
 143         FACTOR(CLK_TOP_AUD2PLL_90M, "aud2pll_90m_ck", "aud2pll", 1, 3),
 144         FACTOR(CLK_TOP_HADDS2PLL_98M, "hadds2pll_98m", "hadds2pll", 1, 3),
 145         FACTOR(CLK_TOP_HADDS2PLL_294M, "hadds2pll_294m", "hadds2pll", 1, 1),
 146         FACTOR(CLK_TOP_ETHPLL_500M, "ethpll_500m_ck", "ethpll", 1, 1),
 147         FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8),
 148         FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793),
 149         FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1),
 150 };
 151
 152 static const char * const axi_parents[] = {
 153         "clk26m",
 154         "syspll1_d2",
 155         "syspll_d5",
 156         "syspll1_d4",
 157         "univpll_d5",
 158         "univpll2_d2",
 159         "mmpll_d2",
 160         "dmpll_d2"
 161 };
 162
 163 static const char * const mem_parents[] = {
 164         "clk26m",
 165         "dmpll_ck"
 166 };
 167
 168 static const char * const ddrphycfg_parents[] = {
 169         "clk26m",
 170         "syspll1_d8"
 171 };
 172
 173 static const char * const mm_parents[] = {
 174         "clk26m",
 175         "vencpll_ck",
 176         "syspll1_d2",
 177         "syspll1_d4",
 178         "univpll_d5",
 179         "univpll1_d2",
 180         "univpll2_d2",
 181         "dmpll_ck"
 182 };
 183
 184 static const char * const pwm_parents[] = {
 185         "clk26m",
 186         "univpll2_d4",
 187         "univpll3_d2",
 188         "univpll1_d4",
 189 };
 190
 191 static const char * const vdec_parents[] = {
 192         "clk26m",
 193         "vdecpll_ck",
 194         "syspll_d5",
 195         "syspll1_d4",
 196         "univpll_d5",
 197         "univpll2_d2",
 198         "vencpll_ck",
 199         "msdcpll_d2",
 200         "mmpll_d2"
 201 };
 202
 203 static const char * const mfg_parents[] = {
 204         "clk26m",
 205         "mmpll_ck",
 206         "dmpll_x2_ck",
 207         "msdcpll_ck",
 208         "clk26m",
 209         "syspll_d3",
 210         "univpll_d3",
 211         "univpll1_d2"
 212 };
 213
 214 static const char * const camtg_parents[] = {
 215         "clk26m",
 216         "univpll_d26",
 217         "univpll2_d2",
 218         "syspll3_d2",
 219         "syspll3_d4",
 220         "msdcpll_d2",
 221         "mmpll_d2"
 222 };
 223
 224 static const char * const uart_parents[] = {
 225         "clk26m",
 226         "univpll2_d8"
 227 };
 228
 229 static const char * const spi_parents[] = {
 230         "clk26m",
 231         "syspll3_d2",
 232         "syspll4_d2",
 233         "univpll2_d4",
 234         "univpll1_d8"
 235 };
 236
 237 static const char * const usb20_parents[] = {
 238         "clk26m",
 239         "univpll1_d8",
 240         "univpll3_d4"
 241 };
 242
 243 static const char * const msdc30_parents[] = {
 244         "clk26m",
 245         "msdcpll_d2",
 246         "syspll2_d2",
 247         "syspll1_d4",
 248         "univpll1_d4",
 249         "univpll2_d4"
 250 };
 251
 252 static const char * const audio_parents[] = {
 253         "clk26m",
 254         "syspll1_d16"
 255 };
 256
 257 static const char * const aud_intbus_parents[] = {
 258         "clk26m",
 259         "syspll1_d4",
 260         "syspll3_d2",
 261         "syspll4_d2",
 262         "univpll3_d2",
 263         "univpll2_d4"
 264 };
 265
 266 static const char * const pmicspi_parents[] = {
 267         "clk26m",
 268         "syspll1_d8",
 269         "syspll2_d4",
 270         "syspll4_d2",
 271         "syspll3_d4",
 272         "syspll2_d8",
 273         "syspll1_d16",
 274         "univpll3_d4",
 275         "univpll_d26",
 276         "dmpll_d2",
 277         "dmpll_d4"
 278 };
 279
 280 static const char * const scp_parents[] = {
 281         "clk26m",
 282         "syspll1_d8",
 283         "dmpll_d2",
 284         "dmpll_d4"
 285 };
 286
 287 static const char * const dpi0_parents[] = {
 288         "clk26m",
 289         "mipipll",
 290         "mipipll_d2",
 291         "mipipll_d4",
 292         "clk26m",
 293         "tvdpll_ck",
 294         "tvdpll_d2",
 295         "tvdpll_d4"
 296 };
 297
 298 static const char * const dpi1_parents[] = {
 299         "clk26m",
 300         "tvdpll_ck",
 301         "tvdpll_d2",
 302         "tvdpll_d4"
 303 };
 304
 305 static const char * const tve_parents[] = {
 306         "clk26m",
 307         "mipipll",
 308         "mipipll_d2",
 309         "mipipll_d4",
 310         "clk26m",
 311         "tvdpll_ck",
 312         "tvdpll_d2",
 313         "tvdpll_d4"
 314 };
 315
 316 static const char * const hdmi_parents[] = {
 317         "clk26m",
 318         "hdmipll_ck",
 319         "hdmipll_d2",
 320         "hdmipll_d3"
 321 };
 322
 323 static const char * const apll_parents[] = {
 324         "clk26m",
 325         "audpll",
 326         "audpll_d4",
 327         "audpll_d8",
 328         "audpll_d16",
 329         "audpll_d24",
 330         "clk26m",
 331         "clk26m"
 332 };
 333
 334 static const char * const rtc_parents[] = {
 335         "32k_internal",
 336         "32k_external",
 337         "clk26m",
 338         "univpll3_d8"
 339 };
 340
 341 static const char * const nfi2x_parents[] = {
 342         "clk26m",
 343         "syspll2_d2",
 344         "syspll_d7",
 345         "univpll3_d2",
 346         "syspll2_d4",
 347         "univpll3_d4",
 348         "syspll4_d4",
 349         "clk26m"
 350 };
 351
 352 static const char * const emmc_hclk_parents[] = {
 353         "clk26m",
 354         "syspll1_d2",
 355         "syspll1_d4",
 356         "syspll2_d2"
 357 };
 358
 359 static const char * const flash_parents[] = {
 360         "clk26m_d8",
 361         "clk26m",
 362         "syspll2_d8",
 363         "syspll3_d4",
 364         "univpll3_d4",
 365         "syspll4_d2",
 366         "syspll2_d4",
 367         "univpll2_d4"
 368 };
 369
 370 static const char * const di_parents[] = {
 371         "clk26m",
 372         "tvd2pll_ck",
 373         "tvd2pll_d2",
 374         "clk26m"
 375 };
 376
 377 static const char * const nr_osd_parents[] = {
 378         "clk26m",
 379         "vencpll_ck",
 380         "syspll1_d2",
 381         "syspll1_d4",
 382         "univpll_d5",
 383         "univpll1_d2",
 384         "univpll2_d2",
 385         "dmpll_ck"
 386 };
 387
 388 static const char * const hdmirx_bist_parents[] = {
 389         "clk26m",
 390         "syspll_d3",
 391         "clk26m",
 392         "syspll1_d16",
 393         "syspll4_d2",
 394         "syspll1_d4",
 395         "vencpll_ck",
 396         "clk26m"
 397 };
 398
 399 static const char * const intdir_parents[] = {
 400         "clk26m",
 401         "mmpll_ck",
 402         "syspll_d2",
 403         "univpll_d2"
 404 };
 405
 406 static const char * const asm_parents[] = {
 407         "clk26m",
 408         "univpll2_d4",
 409         "univpll2_d2",
 410         "syspll_d5"
 411 };
 412
 413 static const char * const ms_card_parents[] = {
 414         "clk26m",
 415         "univpll3_d8",
 416         "syspll4_d4"
 417 };
 418
 419 static const char * const ethif_parents[] = {
 420         "clk26m",
 421         "syspll1_d2",
 422         "syspll_d5",
 423         "syspll1_d4",
 424         "univpll_d5",
 425         "univpll1_d2",
 426         "dmpll_ck",
 427         "dmpll_d2"
 428 };
 429
 430 static const char * const hdmirx_parents[] = {
 431         "clk26m",
 432         "univpll_d52"
 433 };
 434
 435 static const char * const cmsys_parents[] = {
 436         "clk26m",
 437         "syspll1_d2",
 438         "univpll1_d2",
 439         "univpll_d5",
 440         "syspll_d5",
 441         "syspll2_d2",
 442         "syspll1_d4",
 443         "syspll3_d2",
 444         "syspll2_d4",
 445         "syspll1_d8",
 446         "clk26m",
 447         "clk26m",
 448         "clk26m",
 449         "clk26m",
 450         "clk26m"
 451 };
 452
 453 static const char * const clk_8bdac_parents[] = {
 454         "32k_internal",
 455         "8bdac_ck",
 456         "clk26m",
 457         "clk26m"
 458 };
 459
 460 static const char * const aud2dvd_parents[] = {
 461         "a1sys_hp_ck",
 462         "a2sys_hp_ck"
 463 };
 464
 465 static const char * const padmclk_parents[] = {
 466         "clk26m",
 467         "univpll_d26",
 468         "univpll_d52",
 469         "univpll_d108",
 470         "univpll2_d8",
 471         "univpll2_d16",
 472         "univpll2_d32"
 473 };
 474
 475 static const char * const aud_mux_parents[] = {
 476         "clk26m",
 477         "aud1pll_98m_ck",
 478         "aud2pll_90m_ck",
 479         "hadds2pll_98m",
 480         "audio_ext1_ck",
 481         "audio_ext2_ck"
 482 };
 483
 484 static const char * const aud_src_parents[] = {
 485         "aud_mux1_sel",
 486         "aud_mux2_sel"
 487 };
 488
 489 static const char * const cpu_parents[] = {
 490         "clk26m",
 491         "armpll",
 492         "mainpll",
 493         "mmpll"
 494 };
 495
 496 static const struct mtk_composite top_muxes[] = {
 497         MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
 498                 0x0040, 0, 3, 7, CLK_IS_CRITICAL),
 499         MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
 500                 0x0040, 8, 1, 15, CLK_IS_CRITICAL),
 501         MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel",
 502                 ddrphycfg_parents, 0x0040, 16, 1, 23, CLK_IS_CRITICAL),
 503         MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
 504                 0x0040, 24, 3, 31),
 505
 506         MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
 507                 0x0050, 0, 2, 7),
 508         MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents,
 509                 0x0050, 8, 4, 15),
 510         MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents,
 511                 0x0050, 16, 3, 23),
 512         MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
 513                 0x0050, 24, 3, 31),
 514         MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
 515                 0x0060, 0, 1, 7),
 516
 517         MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents,
 518                 0x0060, 8, 3, 15),
 519         MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents,
 520                 0x0060, 16, 2, 23),
 521         MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents,
 522                 0x0060, 24, 3, 31),
 523
 524         MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents,
 525                 0x0070, 0, 3, 7),
 526         MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents,
 527                 0x0070, 8, 3, 15),
 528         MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", msdc30_parents,
 529                 0x0070, 16, 1, 23),
 530         MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
 531                 0x0070, 24, 3, 31),
 532
 533         MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
 534                 0x0080, 0, 4, 7),
 535         MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
 536                 0x0080, 8, 2, 15),
 537         MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,
 538                 0x0080, 16, 3, 23),
 539         MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
 540                 0x0080, 24, 2, 31),
 541
 542         MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents,
 543                 0x0090, 0, 3, 7),
 544         MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents,
 545                 0x0090, 8, 2, 15),
 546         MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents,
 547                 0x0090, 16, 3, 23),
 548
 549         MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents,
 550                 0x00A0, 0, 2, 7, CLK_IS_CRITICAL),
 551         MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,
 552                 0x00A0, 8, 3, 15),
 553         MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, "emmc_hclk_sel", emmc_hclk_parents,
 554                 0x00A0, 24, 2, 31),
 555
 556         MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
 557                 0x00B0, 0, 3, 7),
 558         MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents,
 559                 0x00B0, 8, 2, 15),
 560         MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_osd_parents,
 561                 0x00B0, 16, 3, 23),
 562         MUX_GATE(CLK_TOP_OSD_SEL, "osd_sel", nr_osd_parents,
 563                 0x00B0, 24, 3, 31),
 564
 565         MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, "hdmirx_bist_sel",
 566                 hdmirx_bist_parents, 0x00C0, 0, 3, 7),
 567         MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
 568                 0x00C0, 8, 2, 15),
 569         MUX_GATE(CLK_TOP_ASM_I_SEL, "asm_i_sel", asm_parents,
 570                 0x00C0, 16, 2, 23),
 571         MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_parents,
 572                 0x00C0, 24, 3, 31),
 573
 574         MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_parents,
 575                 0x00D0, 0, 2, 7),
 576         MUX_GATE(CLK_TOP_MS_CARD_SEL, "ms_card_sel", ms_card_parents,
 577                 0x00D0, 16, 2, 23),
 578         MUX_GATE(CLK_TOP_ETHIF_SEL, "ethif_sel", ethif_parents,
 579                 0x00D0, 24, 3, 31),
 580
 581         MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, "hdmirx26_24_sel", hdmirx_parents,
 582                 0x00E0, 0, 1, 7),
 583         MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents,
 584                 0x00E0, 8, 3, 15),
 585         MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents,
 586                 0x00E0, 16, 4, 23),
 587
 588         MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents,
 589                 0x00E0, 24, 3, 31),
 590         MUX_GATE(CLK_TOP_SPI2_SEL, "spi1_sel", spi_parents,
 591                 0x00F0, 0, 3, 7),
 592         MUX_GATE(CLK_TOP_8BDAC_SEL, "8bdac_sel", clk_8bdac_parents,
 593                 0x00F0, 8, 2, 15),
 594         MUX_GATE(CLK_TOP_AUD2DVD_SEL, "aud2dvd_sel", aud2dvd_parents,
 595                 0x00F0, 16, 1, 23),
 596
 597         MUX(CLK_TOP_PADMCLK_SEL, "padmclk_sel", padmclk_parents,
 598                 0x0100, 0, 3),
 599
 600         MUX(CLK_TOP_AUD_MUX1_SEL, "aud_mux1_sel", aud_mux_parents,
 601                 0x012c, 0, 3),
 602         MUX(CLK_TOP_AUD_MUX2_SEL, "aud_mux2_sel", aud_mux_parents,
 603                 0x012c, 3, 3),
 604         MUX(CLK_TOP_AUDPLL_MUX_SEL, "audpll_sel", aud_mux_parents,
 605                 0x012c, 6, 3),
 606         MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, "aud_k1_src_sel", aud_src_parents,
 607                 0x012c, 15, 1, 23),
 608         MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, "aud_k2_src_sel", aud_src_parents,
 609                 0x012c, 16, 1, 24),
 610         MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, "aud_k3_src_sel", aud_src_parents,
 611                 0x012c, 17, 1, 25),
 612         MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, "aud_k4_src_sel", aud_src_parents,
 613                 0x012c, 18, 1, 26),
 614         MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, "aud_k5_src_sel", aud_src_parents,
 615                 0x012c, 19, 1, 27),
 616         MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, "aud_k6_src_sel", aud_src_parents,
 617                 0x012c, 20, 1, 28),
 618 };
 619
 620 static const struct mtk_clk_divider top_adj_divs[] = {
 621         DIV_ADJ(CLK_TOP_AUD_EXTCK1_DIV, "audio_ext1_ck", "aud_ext1",
 622                 0x0120, 0, 8),
 623         DIV_ADJ(CLK_TOP_AUD_EXTCK2_DIV, "audio_ext2_ck", "aud_ext2",
 624                 0x0120, 8, 8),
 625         DIV_ADJ(CLK_TOP_AUD_MUX1_DIV, "aud_mux1_div", "aud_mux1_sel",
 626                 0x0120, 16, 8),
 627         DIV_ADJ(CLK_TOP_AUD_MUX2_DIV, "aud_mux2_div", "aud_mux2_sel",
 628                 0x0120, 24, 8),
 629         DIV_ADJ(CLK_TOP_AUD_K1_SRC_DIV, "aud_k1_src_div", "aud_k1_src_sel",
 630                 0x0124, 0, 8),
 631         DIV_ADJ(CLK_TOP_AUD_K2_SRC_DIV, "aud_k2_src_div", "aud_k2_src_sel",
 632                 0x0124, 8, 8),
 633         DIV_ADJ(CLK_TOP_AUD_K3_SRC_DIV, "aud_k3_src_div", "aud_k3_src_sel",
 634                 0x0124, 16, 8),
 635         DIV_ADJ(CLK_TOP_AUD_K4_SRC_DIV, "aud_k4_src_div", "aud_k4_src_sel",
 636                 0x0124, 24, 8),
 637         DIV_ADJ(CLK_TOP_AUD_K5_SRC_DIV, "aud_k5_src_div", "aud_k5_src_sel",
 638                 0x0128, 0, 8),
 639         DIV_ADJ(CLK_TOP_AUD_K6_SRC_DIV, "aud_k6_src_div", "aud_k6_src_sel",
 640                 0x0128, 8, 8),
 641 };
 642
 643 static const struct mtk_gate_regs top_aud_cg_regs = {
 644         .sta_ofs = 0x012C,
 645 };
 646
 647 #define GATE_TOP_AUD(_id, _name, _parent, _shift) {     \
 648                 .id = _id,                              \
 649                 .name = _name,                          \
 650                 .parent_name = _parent,                 \
 651                 .regs = &top_aud_cg_regs,               \
 652                 .shift = _shift,                        \
 653                 .ops = &mtk_clk_gate_ops_no_setclr,     \
 654         }
 655
 656 static const struct mtk_gate top_clks[] = {
 657         GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div",
 658                 21),
 659         GATE_TOP_AUD(CLK_TOP_AUD_44K_TIMING, "a2sys_hp_ck", "aud_mux2_div",
 660                 22),
 661         GATE_TOP_AUD(CLK_TOP_AUD_I2S1_MCLK, "aud_i2s1_mclk", "aud_k1_src_div",
 662                 23),
 663         GATE_TOP_AUD(CLK_TOP_AUD_I2S2_MCLK, "aud_i2s2_mclk", "aud_k2_src_div",
 664                 24),
 665         GATE_TOP_AUD(CLK_TOP_AUD_I2S3_MCLK, "aud_i2s3_mclk", "aud_k3_src_div",
 666                 25),
 667         GATE_TOP_AUD(CLK_TOP_AUD_I2S4_MCLK, "aud_i2s4_mclk", "aud_k4_src_div",
 668                 26),
 669         GATE_TOP_AUD(CLK_TOP_AUD_I2S5_MCLK, "aud_i2s5_mclk", "aud_k5_src_div",
 670                 27),
 671         GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div",
 672                 28),
 673 };
 674
 675 static int mtk_topckgen_init(struct platform_device *pdev)
 676 {
 677         struct clk_onecell_data *clk_data;
 678         void __iomem *base;
 679         struct device_node *node = pdev->dev.of_node;
 680         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 681
 682         base = devm_ioremap_resource(&pdev->dev, res);
 683         if (IS_ERR(base))
 684                 return PTR_ERR(base);
 685
 686         clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
 687
 688         mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
 689                                                                 clk_data);
 690
 691         mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
 692                                                                 clk_data);
 693
 694         mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
 695                                 base, &mt2701_clk_lock, clk_data);
 696
 697         mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
 698                                 base, &mt2701_clk_lock, clk_data);
 699
 700         mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
 701                                                 clk_data);
 702
 703         return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 704 }
 705
 706 static const struct mtk_gate_regs infra_cg_regs = {
 707         .set_ofs = 0x0040,
 708         .clr_ofs = 0x0044,
 709         .sta_ofs = 0x0048,
 710 };
 711
 712 #define GATE_ICG(_id, _name, _parent, _shift) {         \
 713                 .id = _id,                              \
 714                 .name = _name,                          \
 715                 .parent_name = _parent,                 \
 716                 .regs = &infra_cg_regs,                 \
 717                 .shift = _shift,                        \
 718                 .ops = &mtk_clk_gate_ops_setclr,        \
 719         }
 720
 721 static const struct mtk_gate infra_clks[] = {
 722         GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0),
 723         GATE_ICG(CLK_INFRA_SMI, "smi_ck", "mm_sel", 1),
 724         GATE_ICG(CLK_INFRA_QAXI_CM4, "cm4_ck", "axi_sel", 2),
 725         GATE_ICG(CLK_INFRA_AUD_SPLIN_B, "audio_splin_bck", "hadds2pll_294m", 4),
 726         GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "clk26m", 5),
 727         GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "clk26m", 6),
 728         GATE_ICG(CLK_INFRA_L2C_SRAM, "l2c_sram_ck", "mm_sel", 7),
 729         GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
 730         GATE_ICG(CLK_INFRA_CONNMCU, "connsys_bus", "wbg_dig_ck_416m", 12),
 731         GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 13),
 732         GATE_ICG(CLK_INFRA_RAMBUFIF, "rambufif_ck", "mem_sel", 14),
 733         GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "mem_sel", 15),
 734         GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
 735         GATE_ICG(CLK_INFRA_CEC, "cec_ck", "rtc_sel", 18),
 736         GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 19),
 737         GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
 738         GATE_ICG(CLK_INFRA_PMICWRAP, "pmicwrap_ck", "axi_sel", 23),
 739         GATE_ICG(CLK_INFRA_DDCCI, "ddcci_ck", "axi_sel", 24),
 740 };
 741
 742 static const struct mtk_fixed_factor infra_fixed_divs[] = {
 743         FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
 744 };
 745
 746 static struct clk_onecell_data *infra_clk_data;
 747
 748 static void mtk_infrasys_init_early(struct device_node *node)
 749 {
 750         int r, i;
 751
 752         if (!infra_clk_data) {
 753                 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
 754
 755                 for (i = 0; i < CLK_INFRA_NR; i++)
 756                         infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
 757         }
 758
 759         mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
 760                                                 infra_clk_data);
 761
 762         r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
 763         if (r)
 764                 pr_err("%s(): could not register clock provider: %d\n",
 765                         __func__, r);
 766 }
 767 CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg",
 768                         mtk_infrasys_init_early);
 769
 770 static int mtk_infrasys_init(struct platform_device *pdev)
 771 {
 772         int r, i;
 773         struct device_node *node = pdev->dev.of_node;
 774
 775         if (!infra_clk_data) {
 776                 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
 777         } else {
 778                 for (i = 0; i < CLK_INFRA_NR; i++) {
 779                         if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
 780                                 infra_clk_data->clks[i] = ERR_PTR(-ENOENT);
 781                 }
 782         }
 783
 784         mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
 785                                                 infra_clk_data);
 786         mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
 787                                                 infra_clk_data);
 788
 789         r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
 790         if (r)
 791                 return r;
 792
 793         mtk_register_reset_controller(node, 2, 0x30);
 794
 795         return 0;
 796 }
 797
 798 static const struct mtk_gate_regs peri0_cg_regs = {
 799         .set_ofs = 0x0008,
 800         .clr_ofs = 0x0010,
 801         .sta_ofs = 0x0018,
 802 };
 803
 804 static const struct mtk_gate_regs peri1_cg_regs = {
 805         .set_ofs = 0x000c,
 806         .clr_ofs = 0x0014,
 807         .sta_ofs = 0x001c,
 808 };
 809
 810 #define GATE_PERI0(_id, _name, _parent, _shift) {       \
 811                 .id = _id,                              \
 812                 .name = _name,                          \
 813                 .parent_name = _parent,                 \
 814                 .regs = &peri0_cg_regs,                 \
 815                 .shift = _shift,                        \
 816                 .ops = &mtk_clk_gate_ops_setclr,        \
 817         }
 818
 819 #define GATE_PERI1(_id, _name, _parent, _shift) {       \
 820                 .id = _id,                              \
 821                 .name = _name,                          \
 822                 .parent_name = _parent,                 \
 823                 .regs = &peri1_cg_regs,                 \
 824                 .shift = _shift,                        \
 825                 .ops = &mtk_clk_gate_ops_setclr,        \
 826         }
 827
 828 static const struct mtk_gate peri_clks[] = {
 829         GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31),
 830         GATE_PERI0(CLK_PERI_ETH, "eth_ck", "clk26m", 30),
 831         GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29),
 832         GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28),
 833         GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27),
 834         GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26),
 835         GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25),
 836         GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24),
 837         GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23),
 838         GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22),
 839         GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21),
 840         GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20),
 841         GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
 842         GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18),
 843         GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17),
 844         GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16),
 845         GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15),
 846         GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14),
 847         GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13),
 848         GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
 849         GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
 850         GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
 851         GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
 852         GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
 853         GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
 854         GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
 855         GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
 856         GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
 857         GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
 858         GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
 859         GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
 860         GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),
 861
 862         GATE_PERI1(CLK_PERI_FCI, "fci_ck", "ms_card_sel", 11),
 863         GATE_PERI1(CLK_PERI_SPI2, "spi2_ck", "spi2_sel", 10),
 864         GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi1_sel", 9),
 865         GATE_PERI1(CLK_PERI_HOST89_DVD, "host89_dvd_ck", "aud2dvd_sel", 8),
 866         GATE_PERI1(CLK_PERI_HOST89_SPI, "host89_spi_ck", "spi0_sel", 7),
 867         GATE_PERI1(CLK_PERI_HOST89_INT, "host89_int_ck", "axi_sel", 6),
 868         GATE_PERI1(CLK_PERI_FLASH, "flash_ck", "nfi2x_sel", 5),
 869         GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "nfi1x_pad", 4),
 870         GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "nfi1x_pad", 3),
 871         GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 2),
 872         GATE_PERI1(CLK_PERI_USB_SLV, "usbslv_ck", "axi_sel", 1),
 873         GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 0),
 874 };
 875
 876 static const char * const uart_ck_sel_parents[] = {
 877         "clk26m",
 878         "uart_sel",
 879 };
 880
 881 static const struct mtk_composite peri_muxs[] = {
 882         MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents,
 883                 0x40c, 0, 1),
 884         MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents,
 885                 0x40c, 1, 1),
 886         MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents,
 887                 0x40c, 2, 1),
 888         MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents,
 889                 0x40c, 3, 1),
 890 };
 891
 892 static int mtk_pericfg_init(struct platform_device *pdev)
 893 {
 894         struct clk_onecell_data *clk_data;
 895         void __iomem *base;
 896         int r;
 897         struct device_node *node = pdev->dev.of_node;
 898         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 899
 900         base = devm_ioremap_resource(&pdev->dev, res);
 901         if (IS_ERR(base))
 902                 return PTR_ERR(base);
 903
 904         clk_data = mtk_alloc_clk_data(CLK_PERI_NR);
 905
 906         mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
 907                                                 clk_data);
 908
 909         mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
 910                         &mt2701_clk_lock, clk_data);
 911
 912         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 913         if (r)
 914                 return r;
 915
 916         mtk_register_reset_controller(node, 2, 0x0);
 917
 918         return 0;
 919 }
 920
 921 #define MT8590_PLL_FMAX         (2000 * MHZ)
 922 #define CON0_MT8590_RST_BAR     BIT(27)
 923
 924 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
 925                         _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) {  \
 926                 .id = _id,                                              \
 927                 .name = _name,                                          \
 928                 .reg = _reg,                                            \
 929                 .pwr_reg = _pwr_reg,                                    \
 930                 .en_mask = _en_mask,                                    \
 931                 .flags = _flags,                                        \
 932                 .rst_bar_mask = CON0_MT8590_RST_BAR,                    \
 933                 .fmax = MT8590_PLL_FMAX,                                \
 934                 .pcwbits = _pcwbits,                                    \
 935                 .pd_reg = _pd_reg,                                      \
 936                 .pd_shift = _pd_shift,                                  \
 937                 .tuner_reg = _tuner_reg,                                \
 938                 .pcw_reg = _pcw_reg,                                    \
 939                 .pcw_shift = _pcw_shift,                                \
 940         }
 941
 942 static const struct mtk_pll_data apmixed_plls[] = {
 943         PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000001,
 944                         PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0),
 945         PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000001,
 946                   HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0),
 947         PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000001,
 948                   HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14),
 949         PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0,
 950                                 21, 0x230, 4, 0x0, 0x234, 0),
 951         PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
 952                                 21, 0x240, 4, 0x0, 0x244, 0),
 953         PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
 954                                 21, 0x250, 4, 0x0, 0x254, 0),
 955         PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
 956                                 31, 0x270, 4, 0x0, 0x274, 0),
 957         PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
 958                                 31, 0x280, 4, 0x0, 0x284, 0),
 959         PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
 960                                 31, 0x290, 4, 0x0, 0x294, 0),
 961         PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0,
 962                                 31, 0x2a0, 4, 0x0, 0x2a4, 0),
 963         PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0,
 964                                 31, 0x2b0, 4, 0x0, 0x2b4, 0),
 965         PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0,
 966                                 31, 0x2c0, 4, 0x0, 0x2c4, 0),
 967         PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0,
 968                                 21, 0x2d0, 4, 0x0, 0x2d4, 0),
 969 };
 970
 971 static int mtk_apmixedsys_init(struct platform_device *pdev)
 972 {
 973         struct clk_onecell_data *clk_data;
 974         struct device_node *node = pdev->dev.of_node;
 975
 976         clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
 977         if (!clk_data)
 978                 return -ENOMEM;
 979
 980         mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls),
 981                                                                 clk_data);
 982
 983         return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 984 }
 985
 986 static const struct of_device_id of_match_clk_mt2701[] = {
 987         {
 988                 .compatible = "mediatek,mt2701-topckgen",
 989                 .data = mtk_topckgen_init,
 990         }, {
 991                 .compatible = "mediatek,mt2701-infracfg",
 992                 .data = mtk_infrasys_init,
 993         }, {
 994                 .compatible = "mediatek,mt2701-pericfg",
 995                 .data = mtk_pericfg_init,
 996         }, {
 997                 .compatible = "mediatek,mt2701-apmixedsys",
 998                 .data = mtk_apmixedsys_init,
 999         }, {
1000                 /* sentinel */
1001         }
1002 };
1003
1004 static int clk_mt2701_probe(struct platform_device *pdev)
1005 {
1006         int (*clk_init)(struct platform_device *);
1007         int r;
1008
1009         clk_init = of_device_get_match_data(&pdev->dev);
1010         if (!clk_init)
1011                 return -EINVAL;
1012
1013         r = clk_init(pdev);
1014         if (r)
1015                 dev_err(&pdev->dev,
1016                         "could not register clock provider: %s: %d\n",
1017                         pdev->name, r);
1018
1019         return r;
1020 }
1021
1022 static struct platform_driver clk_mt2701_drv = {
1023         .probe = clk_mt2701_probe,
1024         .driver = {
1025                 .name = "clk-mt2701",
1026                 .of_match_table = of_match_clk_mt2701,
1027         },
1028 };
1029
1030 static int __init clk_mt2701_init(void)
1031 {
1032         return platform_driver_register(&clk_mt2701_drv);
1033 }
1034
1035 arch_initcall(clk_mt2701_init);