2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: James Liao <jamesjj.liao@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/clk.h>
17 #include <linux/of_address.h>
18 #include <linux/slab.h>
19 #include <linux/mfd/syscon.h>
20 #include <dt-bindings/clock/mt8135-clk.h>
25 static DEFINE_SPINLOCK(mt8135_clk_lock);
27 static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
28 FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1),
29 FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1),
30 FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1),
31 FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1),
34 static const struct mtk_fixed_factor top_divs[] __initconst = {
35 FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2),
36 FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_537p3m", "mainpll", 1, 3),
37 FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_322p4m", "mainpll", 1, 5),
38 FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_230p3m", "mainpll", 1, 7),
40 FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2),
41 FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3),
42 FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5),
43 FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7),
44 FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26),
46 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
47 FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3", "mmpll", 1, 3),
48 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
49 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
50 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_d2", 1, 2),
51 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_d3", 1, 2),
53 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll_806m", 1, 1),
54 FACTOR(CLK_TOP_SYSPLL_D4, "syspll_d4", "mainpll_806m", 1, 2),
55 FACTOR(CLK_TOP_SYSPLL_D6, "syspll_d6", "mainpll_806m", 1, 3),
56 FACTOR(CLK_TOP_SYSPLL_D8, "syspll_d8", "mainpll_806m", 1, 4),
57 FACTOR(CLK_TOP_SYSPLL_D10, "syspll_d10", "mainpll_806m", 1, 5),
58 FACTOR(CLK_TOP_SYSPLL_D12, "syspll_d12", "mainpll_806m", 1, 6),
59 FACTOR(CLK_TOP_SYSPLL_D16, "syspll_d16", "mainpll_806m", 1, 8),
60 FACTOR(CLK_TOP_SYSPLL_D24, "syspll_d24", "mainpll_806m", 1, 12),
62 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_537p3m", 1, 1),
64 FACTOR(CLK_TOP_SYSPLL_D2P5, "syspll_d2p5", "mainpll_322p4m", 2, 1),
65 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_322p4m", 1, 1),
67 FACTOR(CLK_TOP_SYSPLL_D3P5, "syspll_d3p5", "mainpll_230p3m", 2, 1),
69 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
70 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
71 FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6),
72 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
73 FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10),
75 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2),
76 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4),
77 FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6),
78 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8),
80 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_416m", 1, 1),
81 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1),
82 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_178p3m", 1, 1),
83 FACTOR(CLK_TOP_UNIVPLL_D10, "univpll_d10", "univpll_249p6m", 1, 2),
84 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1),
86 FACTOR(CLK_TOP_APLL, "apll_ck", "audpll", 1, 1),
87 FACTOR(CLK_TOP_APLL_D4, "apll_d4", "audpll", 1, 4),
88 FACTOR(CLK_TOP_APLL_D8, "apll_d8", "audpll", 1, 8),
89 FACTOR(CLK_TOP_APLL_D16, "apll_d16", "audpll", 1, 16),
90 FACTOR(CLK_TOP_APLL_D24, "apll_d24", "audpll", 1, 24),
92 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
93 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
94 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
96 FACTOR(CLK_TOP_LVDSTX_CLKDIG_CT, "lvdstx_clkdig_cts", "lvdspll", 1, 1),
97 FACTOR(CLK_TOP_VPLL_DPIX, "vpll_dpix_ck", "lvdspll", 1, 1),
99 FACTOR(CLK_TOP_TVHDMI_H, "tvhdmi_h_ck", "tvdpll", 1, 1),
101 FACTOR(CLK_TOP_HDMITX_CLKDIG_D2, "hdmitx_clkdig_d2", "hdmitx_clkdig_cts", 1, 2),
102 FACTOR(CLK_TOP_HDMITX_CLKDIG_D3, "hdmitx_clkdig_d3", "hdmitx_clkdig_cts", 1, 3),
104 FACTOR(CLK_TOP_TVHDMI_D2, "tvhdmi_d2", "tvhdmi_h_ck", 1, 2),
105 FACTOR(CLK_TOP_TVHDMI_D4, "tvhdmi_d4", "tvhdmi_h_ck", 1, 4),
107 FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4),
110 static const char * const axi_parents[] __initconst = {
120 static const char * const smi_parents[] __initconst = {
138 static const char * const mfg_parents[] __initconst = {
154 static const char * const irda_parents[] __initconst = {
160 static const char * const cam_parents[] __initconst = {
171 static const char * const aud_intbus_parents[] __initconst = {
177 static const char * const jpg_parents[] __initconst = {
187 static const char * const disp_parents[] __initconst = {
198 static const char * const msdc30_parents[] __initconst = {
207 static const char * const usb20_parents[] __initconst = {
213 static const char * const venc_parents[] __initconst = {
224 static const char * const spi_parents[] __initconst = {
233 static const char * const uart_parents[] __initconst = {
238 static const char * const mem_parents[] __initconst = {
243 static const char * const camtg_parents[] __initconst = {
251 static const char * const audio_parents[] __initconst = {
256 static const char * const fix_parents[] __initconst = {
267 static const char * const vdec_parents[] __initconst = {
286 static const char * const ddrphycfg_parents[] __initconst = {
292 static const char * const dpilvds_parents[] __initconst = {
300 static const char * const pmicspi_parents[] __initconst = {
311 static const char * const smi_mfg_as_parents[] __initconst = {
318 static const char * const gcpu_parents[] __initconst = {
326 static const char * const dpi1_parents[] __initconst = {
333 static const char * const cci_parents[] __initconst = {
342 static const char * const apll_parents[] __initconst = {
351 static const char * const hdmipll_parents[] __initconst = {
358 static const struct mtk_composite top_muxes[] __initconst = {
360 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
361 0x0140, 0, 3, INVALID_MUX_GATE_BIT),
362 MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15),
363 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23),
364 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31),
366 MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7),
367 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
369 MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23),
370 MUX_GATE(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x0144, 24, 3, 31),
372 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7),
373 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15),
374 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23),
375 MUX_GATE(CLK_TOP_MSDC30_4_SEL, "msdc30_4_sel", msdc30_parents, 0x0148, 24, 3, 31),
377 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x014c, 0, 2, 7),
379 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15),
380 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
381 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
383 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
384 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15),
385 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0158, 24, 2, 31),
387 MUX_GATE(CLK_TOP_FIX_SEL, "fix_sel", fix_parents, 0x015c, 0, 3, 7),
388 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15),
389 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
391 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x015c, 24, 3, 31),
393 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0164, 0, 3, 7),
394 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15),
395 MUX_GATE(CLK_TOP_SMI_MFG_AS_SEL, "smi_mfg_as_sel", smi_mfg_as_parents,
397 MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31),
399 MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7),
400 MUX_GATE(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15),
401 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23),
402 MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31),
405 static const struct mtk_gate_regs infra_cg_regs = {
411 #define GATE_ICG(_id, _name, _parent, _shift) { \
414 .parent_name = _parent, \
415 .regs = &infra_cg_regs, \
417 .ops = &mtk_clk_gate_ops_setclr, \
420 static const struct mtk_gate infra_clks[] __initconst = {
421 GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23),
422 GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
423 GATE_ICG(CLK_INFRA_CCIF1_AP_CTRL, "ccif1_ap_ctrl", "axi_sel", 21),
424 GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20),
425 GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
426 GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15),
427 GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
428 GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7),
429 GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6),
430 GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5),
431 GATE_ICG(CLK_INFRA_MFG_BUS, "mfg_bus_ck", "axi_sel", 2),
432 GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1),
433 GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0),
436 static const struct mtk_gate_regs peri0_cg_regs = {
442 static const struct mtk_gate_regs peri1_cg_regs = {
448 #define GATE_PERI0(_id, _name, _parent, _shift) { \
451 .parent_name = _parent, \
452 .regs = &peri0_cg_regs, \
454 .ops = &mtk_clk_gate_ops_setclr, \
457 #define GATE_PERI1(_id, _name, _parent, _shift) { \
460 .parent_name = _parent, \
461 .regs = &peri1_cg_regs, \
463 .ops = &mtk_clk_gate_ops_setclr, \
466 static const struct mtk_gate peri_gates[] __initconst = {
468 GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31),
469 GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30),
470 GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29),
471 GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28),
472 GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27),
473 GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26),
474 GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25),
475 GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24),
476 GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23),
477 GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22),
478 GATE_PERI0(CLK_PERI_IRDA, "irda_ck", "irda_sel", 21),
479 GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 20),
480 GATE_PERI0(CLK_PERI_MD_HIF, "md_hif_ck", "axi_sel", 19),
481 GATE_PERI0(CLK_PERI_AP_HIF, "ap_hif_ck", "axi_sel", 18),
482 GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_4_sel", 17),
483 GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_3_sel", 16),
484 GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_2_sel", 15),
485 GATE_PERI0(CLK_PERI_MSDC20_2, "msdc20_2_ck", "msdc30_1_sel", 14),
486 GATE_PERI0(CLK_PERI_MSDC20_1, "msdc20_1_ck", "msdc30_0_sel", 13),
487 GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
488 GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
489 GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
490 GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
491 GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
492 GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
493 GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
494 GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
495 GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
496 GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
497 GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
498 GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
499 GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0),
501 GATE_PERI1(CLK_PERI_USBSLV, "usbslv_ck", "axi_sel", 8),
502 GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 7),
503 GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 6),
504 GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "gcpu_sel", 5),
505 GATE_PERI1(CLK_PERI_FHCTL, "fhctl_ck", "clk26m", 4),
506 GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi_sel", 3),
507 GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 2),
508 GATE_PERI1(CLK_PERI_PERI_PWRAP, "peri_pwrap_ck", "axi_sel", 1),
509 GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0),
512 static const char * const uart_ck_sel_parents[] __initconst = {
517 static const struct mtk_composite peri_clks[] __initconst = {
518 MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
519 MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
520 MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
521 MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
524 static void __init mtk_topckgen_init(struct device_node *node)
526 struct clk_onecell_data *clk_data;
530 base = of_iomap(node, 0);
532 pr_err("%s(): ioremap failed\n", __func__);
536 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
538 mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
539 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
540 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
541 &mt8135_clk_lock, clk_data);
543 clk_prepare_enable(clk_data->clks[CLK_TOP_CCI_SEL]);
545 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
547 pr_err("%s(): could not register clock provider: %d\n",
550 CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8135-topckgen", mtk_topckgen_init);
552 static void __init mtk_infrasys_init(struct device_node *node)
554 struct clk_onecell_data *clk_data;
557 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
559 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
562 clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]);
564 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
566 pr_err("%s(): could not register clock provider: %d\n",
569 mtk_register_reset_controller(node, 2, 0x30);
571 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
573 static void __init mtk_pericfg_init(struct device_node *node)
575 struct clk_onecell_data *clk_data;
579 base = of_iomap(node, 0);
581 pr_err("%s(): ioremap failed\n", __func__);
585 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
587 mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
589 mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
590 &mt8135_clk_lock, clk_data);
592 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
594 pr_err("%s(): could not register clock provider: %d\n",
597 mtk_register_reset_controller(node, 2, 0);
599 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
601 #define MT8135_PLL_FMAX (2000 * MHZ)
602 #define CON0_MT8135_RST_BAR BIT(27)
604 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
608 .pwr_reg = _pwr_reg, \
609 .en_mask = _en_mask, \
611 .rst_bar_mask = CON0_MT8135_RST_BAR, \
612 .fmax = MT8135_PLL_FMAX, \
613 .pcwbits = _pcwbits, \
615 .pd_shift = _pd_shift, \
616 .tuner_reg = _tuner_reg, \
617 .pcw_reg = _pcw_reg, \
618 .pcw_shift = _pcw_shift, \
621 static const struct mtk_pll_data plls[] = {
622 PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
623 PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000001, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
624 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000001, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0),
625 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000001, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9),
626 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000001, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0),
627 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000001, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
628 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000001, 0, 31, 0x294, 6, 0x0, 0x298, 0),
629 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
630 PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000001, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
631 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
634 static void __init mtk_apmixedsys_init(struct device_node *node)
636 struct clk_onecell_data *clk_data;
638 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
642 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
644 CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8135-apmixedsys",
645 mtk_apmixedsys_init);