2 * Copyright (c) 2015 Endless Mobile, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #define PMASK(width) GENMASK(width - 1, 0)
22 #define SETPMASK(width, shift) GENMASK(shift + width - 1, shift)
23 #define CLRPMASK(width, shift) (~SETPMASK(width, shift))
25 #define PARM_GET(width, shift, reg) \
26 (((reg) & SETPMASK(width, shift)) >> (shift))
27 #define PARM_SET(width, shift, reg, val) \
28 (((reg) & CLRPMASK(width, shift)) | ((val) << (shift)))
30 #define MESON_PARM_APPLICABLE(p) (!!((p)->width))
38 struct pll_rate_table {
47 #define PLL_RATE(_r, _m, _n, _od) \
55 #define PLL_FRAC_RATE(_r, _m, _n, _od, _od2, _frac) \
65 struct pll_params_table {
70 #define PLL_PARAM(_reg, _val) \
76 struct pll_setup_params {
77 struct pll_params_table *params_table;
78 unsigned int params_count;
79 /* Workaround for GP0, do not reset before configuring */
81 /* Workaround for GP0, unreset right before checking for lock */
82 bool clear_reset_for_lock;
83 /* Workaround for GXL GP0, reset in the lock checking loop */
87 struct meson_clk_pll {
95 const struct pll_setup_params params;
96 const struct pll_rate_table *rate_table;
97 unsigned int rate_count;
101 #define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw)
103 struct meson_clk_cpu {
107 struct notifier_block clk_nb;
108 const struct clk_div_table *div_table;
111 int meson_clk_cpu_notifier_cb(struct notifier_block *nb, unsigned long event,
114 struct meson_clk_mpll {
125 struct meson_clk_audio_divider {
133 #define MESON_GATE(_name, _reg, _bit) \
134 struct clk_gate _name = { \
135 .reg = (void __iomem *) _reg, \
138 .hw.init = &(struct clk_init_data) { \
140 .ops = &clk_gate_ops, \
141 .parent_names = (const char *[]){ "clk81" }, \
143 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
148 extern const struct clk_ops meson_clk_pll_ro_ops;
149 extern const struct clk_ops meson_clk_pll_ops;
150 extern const struct clk_ops meson_clk_cpu_ops;
151 extern const struct clk_ops meson_clk_mpll_ro_ops;
152 extern const struct clk_ops meson_clk_mpll_ops;
153 extern const struct clk_ops meson_clk_audio_divider_ro_ops;
154 extern const struct clk_ops meson_clk_audio_divider_ops;
156 #endif /* __CLKC_H */