2 * AmLogic S805 / Meson8b Clock Controller Driver
4 * Copyright (c) 2015 Endless Mobile, Inc.
5 * Author: Carlo Caione <carlo@endlessm.com>
7 * Copyright (c) 2016 BayLibre, Inc.
8 * Michael Turquette <mturquette@baylibre.com>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <linux/clk.h>
24 #include <linux/clk-provider.h>
25 #include <linux/of_address.h>
26 #include <linux/platform_device.h>
27 #include <linux/init.h>
32 static DEFINE_SPINLOCK(clk_lock);
34 static const struct pll_rate_table sys_pll_rate_table[] = {
35 PLL_RATE(312000000, 52, 1, 2),
36 PLL_RATE(336000000, 56, 1, 2),
37 PLL_RATE(360000000, 60, 1, 2),
38 PLL_RATE(384000000, 64, 1, 2),
39 PLL_RATE(408000000, 68, 1, 2),
40 PLL_RATE(432000000, 72, 1, 2),
41 PLL_RATE(456000000, 76, 1, 2),
42 PLL_RATE(480000000, 80, 1, 2),
43 PLL_RATE(504000000, 84, 1, 2),
44 PLL_RATE(528000000, 88, 1, 2),
45 PLL_RATE(552000000, 92, 1, 2),
46 PLL_RATE(576000000, 96, 1, 2),
47 PLL_RATE(600000000, 50, 1, 1),
48 PLL_RATE(624000000, 52, 1, 1),
49 PLL_RATE(648000000, 54, 1, 1),
50 PLL_RATE(672000000, 56, 1, 1),
51 PLL_RATE(696000000, 58, 1, 1),
52 PLL_RATE(720000000, 60, 1, 1),
53 PLL_RATE(744000000, 62, 1, 1),
54 PLL_RATE(768000000, 64, 1, 1),
55 PLL_RATE(792000000, 66, 1, 1),
56 PLL_RATE(816000000, 68, 1, 1),
57 PLL_RATE(840000000, 70, 1, 1),
58 PLL_RATE(864000000, 72, 1, 1),
59 PLL_RATE(888000000, 74, 1, 1),
60 PLL_RATE(912000000, 76, 1, 1),
61 PLL_RATE(936000000, 78, 1, 1),
62 PLL_RATE(960000000, 80, 1, 1),
63 PLL_RATE(984000000, 82, 1, 1),
64 PLL_RATE(1008000000, 84, 1, 1),
65 PLL_RATE(1032000000, 86, 1, 1),
66 PLL_RATE(1056000000, 88, 1, 1),
67 PLL_RATE(1080000000, 90, 1, 1),
68 PLL_RATE(1104000000, 92, 1, 1),
69 PLL_RATE(1128000000, 94, 1, 1),
70 PLL_RATE(1152000000, 96, 1, 1),
71 PLL_RATE(1176000000, 98, 1, 1),
72 PLL_RATE(1200000000, 50, 1, 0),
73 PLL_RATE(1224000000, 51, 1, 0),
74 PLL_RATE(1248000000, 52, 1, 0),
75 PLL_RATE(1272000000, 53, 1, 0),
76 PLL_RATE(1296000000, 54, 1, 0),
77 PLL_RATE(1320000000, 55, 1, 0),
78 PLL_RATE(1344000000, 56, 1, 0),
79 PLL_RATE(1368000000, 57, 1, 0),
80 PLL_RATE(1392000000, 58, 1, 0),
81 PLL_RATE(1416000000, 59, 1, 0),
82 PLL_RATE(1440000000, 60, 1, 0),
83 PLL_RATE(1464000000, 61, 1, 0),
84 PLL_RATE(1488000000, 62, 1, 0),
85 PLL_RATE(1512000000, 63, 1, 0),
86 PLL_RATE(1536000000, 64, 1, 0),
90 static const struct clk_div_table cpu_div_table[] = {
91 { .val = 1, .div = 1 },
92 { .val = 2, .div = 2 },
93 { .val = 3, .div = 3 },
94 { .val = 2, .div = 4 },
95 { .val = 3, .div = 6 },
96 { .val = 4, .div = 8 },
97 { .val = 5, .div = 10 },
98 { .val = 6, .div = 12 },
99 { .val = 7, .div = 14 },
100 { .val = 8, .div = 16 },
104 static struct clk_fixed_rate meson8b_xtal = {
105 .fixed_rate = 24000000,
106 .hw.init = &(struct clk_init_data){
109 .ops = &clk_fixed_rate_ops,
113 static struct meson_clk_pll meson8b_fixed_pll = {
115 .reg_off = HHI_MPLL_CNTL,
120 .reg_off = HHI_MPLL_CNTL,
125 .reg_off = HHI_MPLL_CNTL,
130 .hw.init = &(struct clk_init_data){
132 .ops = &meson_clk_pll_ro_ops,
133 .parent_names = (const char *[]){ "xtal" },
135 .flags = CLK_GET_RATE_NOCACHE,
139 static struct meson_clk_pll meson8b_vid_pll = {
141 .reg_off = HHI_VID_PLL_CNTL,
146 .reg_off = HHI_VID_PLL_CNTL,
151 .reg_off = HHI_VID_PLL_CNTL,
156 .hw.init = &(struct clk_init_data){
158 .ops = &meson_clk_pll_ro_ops,
159 .parent_names = (const char *[]){ "xtal" },
161 .flags = CLK_GET_RATE_NOCACHE,
165 static struct meson_clk_pll meson8b_sys_pll = {
167 .reg_off = HHI_SYS_PLL_CNTL,
172 .reg_off = HHI_SYS_PLL_CNTL,
177 .reg_off = HHI_SYS_PLL_CNTL,
181 .rate_table = sys_pll_rate_table,
182 .rate_count = ARRAY_SIZE(sys_pll_rate_table),
184 .hw.init = &(struct clk_init_data){
186 .ops = &meson_clk_pll_ops,
187 .parent_names = (const char *[]){ "xtal" },
189 .flags = CLK_GET_RATE_NOCACHE,
193 static struct clk_fixed_factor meson8b_fclk_div2 = {
196 .hw.init = &(struct clk_init_data){
198 .ops = &clk_fixed_factor_ops,
199 .parent_names = (const char *[]){ "fixed_pll" },
204 static struct clk_fixed_factor meson8b_fclk_div3 = {
207 .hw.init = &(struct clk_init_data){
209 .ops = &clk_fixed_factor_ops,
210 .parent_names = (const char *[]){ "fixed_pll" },
215 static struct clk_fixed_factor meson8b_fclk_div4 = {
218 .hw.init = &(struct clk_init_data){
220 .ops = &clk_fixed_factor_ops,
221 .parent_names = (const char *[]){ "fixed_pll" },
226 static struct clk_fixed_factor meson8b_fclk_div5 = {
229 .hw.init = &(struct clk_init_data){
231 .ops = &clk_fixed_factor_ops,
232 .parent_names = (const char *[]){ "fixed_pll" },
237 static struct clk_fixed_factor meson8b_fclk_div7 = {
240 .hw.init = &(struct clk_init_data){
242 .ops = &clk_fixed_factor_ops,
243 .parent_names = (const char *[]){ "fixed_pll" },
248 static struct meson_clk_mpll meson8b_mpll0 = {
250 .reg_off = HHI_MPLL_CNTL7,
255 .reg_off = HHI_MPLL_CNTL7,
260 .reg_off = HHI_MPLL_CNTL7,
265 .reg_off = HHI_MPLL_CNTL7,
270 .hw.init = &(struct clk_init_data){
272 .ops = &meson_clk_mpll_ops,
273 .parent_names = (const char *[]){ "fixed_pll" },
278 static struct meson_clk_mpll meson8b_mpll1 = {
280 .reg_off = HHI_MPLL_CNTL8,
285 .reg_off = HHI_MPLL_CNTL8,
290 .reg_off = HHI_MPLL_CNTL8,
295 .reg_off = HHI_MPLL_CNTL8,
300 .hw.init = &(struct clk_init_data){
302 .ops = &meson_clk_mpll_ops,
303 .parent_names = (const char *[]){ "fixed_pll" },
308 static struct meson_clk_mpll meson8b_mpll2 = {
310 .reg_off = HHI_MPLL_CNTL9,
315 .reg_off = HHI_MPLL_CNTL9,
320 .reg_off = HHI_MPLL_CNTL9,
325 .reg_off = HHI_MPLL_CNTL9,
330 .hw.init = &(struct clk_init_data){
332 .ops = &meson_clk_mpll_ops,
333 .parent_names = (const char *[]){ "fixed_pll" },
339 * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL
340 * post-dividers and should be modeled with their respective PLLs via the
341 * forthcoming coordinated clock rates feature
343 static struct meson_clk_cpu meson8b_cpu_clk = {
344 .reg_off = HHI_SYS_CPU_CLK_CNTL1,
345 .div_table = cpu_div_table,
346 .clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
347 .hw.init = &(struct clk_init_data){
349 .ops = &meson_clk_cpu_ops,
350 .parent_names = (const char *[]){ "sys_pll" },
355 static u32 mux_table_clk81[] = { 6, 5, 7 };
357 struct clk_mux meson8b_mpeg_clk_sel = {
358 .reg = (void *)HHI_MPEG_CLK_CNTL,
361 .flags = CLK_MUX_READ_ONLY,
362 .table = mux_table_clk81,
364 .hw.init = &(struct clk_init_data){
365 .name = "mpeg_clk_sel",
366 .ops = &clk_mux_ro_ops,
368 * FIXME bits 14:12 selects from 8 possible parents:
369 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
370 * fclk_div4, fclk_div3, fclk_div5
372 .parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
375 .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
379 struct clk_divider meson8b_mpeg_clk_div = {
380 .reg = (void *)HHI_MPEG_CLK_CNTL,
384 .hw.init = &(struct clk_init_data){
385 .name = "mpeg_clk_div",
386 .ops = &clk_divider_ops,
387 .parent_names = (const char *[]){ "mpeg_clk_sel" },
389 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
393 struct clk_gate meson8b_clk81 = {
394 .reg = (void *)HHI_MPEG_CLK_CNTL,
397 .hw.init = &(struct clk_init_data){
399 .ops = &clk_gate_ops,
400 .parent_names = (const char *[]){ "mpeg_clk_div" },
402 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
406 /* Everything Else (EE) domain gates */
408 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
409 static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
410 static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
411 static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
412 static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
413 static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
414 static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
415 static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
416 static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
417 static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
418 static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
419 static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
420 static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
421 static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
422 static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
423 static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
424 static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
425 static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
426 static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
428 static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
429 static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
430 static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
431 static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);
432 static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
433 static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
434 static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
435 static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
436 static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
437 static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
438 static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
439 static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
440 static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
441 static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
442 static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
443 static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
444 static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
445 static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
446 static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
447 static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
448 static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
449 static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
450 static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
451 static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
452 static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
454 static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
455 static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
456 static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
457 static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
458 static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
459 static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
460 static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
461 static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
462 static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
463 static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
464 static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
465 static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
466 static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
468 static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
469 static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
470 static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
471 static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
472 static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
473 static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
474 static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
475 static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
476 static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
477 static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
478 static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
479 static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
480 static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
481 static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
482 static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
483 static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
485 /* Always On (AO) domain gates */
487 static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
488 static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
489 static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
490 static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
492 static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
494 [CLKID_XTAL] = &meson8b_xtal.hw,
495 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
496 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
497 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
498 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
499 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
500 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
501 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
502 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
503 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
504 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
505 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
506 [CLKID_CLK81] = &meson8b_clk81.hw,
507 [CLKID_DDR] = &meson8b_ddr.hw,
508 [CLKID_DOS] = &meson8b_dos.hw,
509 [CLKID_ISA] = &meson8b_isa.hw,
510 [CLKID_PL301] = &meson8b_pl301.hw,
511 [CLKID_PERIPHS] = &meson8b_periphs.hw,
512 [CLKID_SPICC] = &meson8b_spicc.hw,
513 [CLKID_I2C] = &meson8b_i2c.hw,
514 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
515 [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
516 [CLKID_RNG0] = &meson8b_rng0.hw,
517 [CLKID_UART0] = &meson8b_uart0.hw,
518 [CLKID_SDHC] = &meson8b_sdhc.hw,
519 [CLKID_STREAM] = &meson8b_stream.hw,
520 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
521 [CLKID_SDIO] = &meson8b_sdio.hw,
522 [CLKID_ABUF] = &meson8b_abuf.hw,
523 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
524 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
525 [CLKID_SPI] = &meson8b_spi.hw,
526 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
527 [CLKID_ETH] = &meson8b_eth.hw,
528 [CLKID_DEMUX] = &meson8b_demux.hw,
529 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
530 [CLKID_IEC958] = &meson8b_iec958.hw,
531 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
532 [CLKID_AMCLK] = &meson8b_amclk.hw,
533 [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
534 [CLKID_MIXER] = &meson8b_mixer.hw,
535 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
536 [CLKID_ADC] = &meson8b_adc.hw,
537 [CLKID_BLKMV] = &meson8b_blkmv.hw,
538 [CLKID_AIU] = &meson8b_aiu.hw,
539 [CLKID_UART1] = &meson8b_uart1.hw,
540 [CLKID_G2D] = &meson8b_g2d.hw,
541 [CLKID_USB0] = &meson8b_usb0.hw,
542 [CLKID_USB1] = &meson8b_usb1.hw,
543 [CLKID_RESET] = &meson8b_reset.hw,
544 [CLKID_NAND] = &meson8b_nand.hw,
545 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
546 [CLKID_USB] = &meson8b_usb.hw,
547 [CLKID_VDIN1] = &meson8b_vdin1.hw,
548 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
549 [CLKID_EFUSE] = &meson8b_efuse.hw,
550 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
551 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
552 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
553 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
554 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
555 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
556 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
557 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
558 [CLKID_DVIN] = &meson8b_dvin.hw,
559 [CLKID_UART2] = &meson8b_uart2.hw,
560 [CLKID_SANA] = &meson8b_sana.hw,
561 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
562 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
563 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
564 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
565 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
566 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
567 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
568 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
569 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
570 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
571 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
572 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
573 [CLKID_ENC480P] = &meson8b_enc480p.hw,
574 [CLKID_RNG1] = &meson8b_rng1.hw,
575 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
576 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
577 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
578 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
579 [CLKID_EDP] = &meson8b_edp.hw,
580 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
581 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
582 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
583 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
584 [CLKID_MPLL0] = &meson8b_mpll0.hw,
585 [CLKID_MPLL1] = &meson8b_mpll1.hw,
586 [CLKID_MPLL2] = &meson8b_mpll2.hw,
591 static struct meson_clk_pll *const meson8b_clk_plls[] = {
597 static struct meson_clk_mpll *const meson8b_clk_mplls[] = {
603 static struct clk_gate *const meson8b_clk_gates[] = {
622 &meson8b_assist_misc,
633 &meson8b_mixer_iface,
649 &meson8b_ahb_data_bus,
650 &meson8b_ahb_ctrl_bus,
651 &meson8b_hdmi_intr_sync,
653 &meson8b_usb1_ddr_bridge,
654 &meson8b_usb0_ddr_bridge,
660 &meson8b_sec_ahb_ahb3_bridge,
662 &meson8b_vclk2_venci0,
663 &meson8b_vclk2_venci1,
664 &meson8b_vclk2_vencp0,
665 &meson8b_vclk2_vencp1,
666 &meson8b_gclk_venci_int,
667 &meson8b_gclk_vencp_int,
670 &meson8b_iec958_gate,
673 &meson8b_gclk_vencl_int,
674 &meson8b_vclk2_venclmcc,
675 &meson8b_vclk2_vencl,
676 &meson8b_vclk2_other,
678 &meson8b_ao_media_cpu,
679 &meson8b_ao_ahb_sram,
684 static struct clk_mux *const meson8b_clk_muxes[] = {
685 &meson8b_mpeg_clk_sel,
688 static struct clk_divider *const meson8b_clk_dividers[] = {
689 &meson8b_mpeg_clk_div,
692 static int meson8b_clkc_probe(struct platform_device *pdev)
694 void __iomem *clk_base;
696 struct clk_hw *parent_hw;
697 struct clk *parent_clk;
698 struct device *dev = &pdev->dev;
700 /* Generic clocks and PLLs */
701 clk_base = of_iomap(dev->of_node, 1);
703 pr_err("%s: Unable to map clk base\n", __func__);
707 /* Populate base address for PLLs */
708 for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++)
709 meson8b_clk_plls[i]->base = clk_base;
711 /* Populate base address for MPLLs */
712 for (i = 0; i < ARRAY_SIZE(meson8b_clk_mplls); i++)
713 meson8b_clk_mplls[i]->base = clk_base;
715 /* Populate the base address for CPU clk */
716 meson8b_cpu_clk.base = clk_base;
718 /* Populate base address for gates */
719 for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++)
720 meson8b_clk_gates[i]->reg = clk_base +
721 (u32)meson8b_clk_gates[i]->reg;
723 /* Populate base address for muxes */
724 for (i = 0; i < ARRAY_SIZE(meson8b_clk_muxes); i++)
725 meson8b_clk_muxes[i]->reg = clk_base +
726 (u32)meson8b_clk_muxes[i]->reg;
728 /* Populate base address for dividers */
729 for (i = 0; i < ARRAY_SIZE(meson8b_clk_dividers); i++)
730 meson8b_clk_dividers[i]->reg = clk_base +
731 (u32)meson8b_clk_dividers[i]->reg;
735 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
737 for (clkid = CLKID_XTAL; clkid < CLK_NR_CLKS; clkid++) {
738 /* array might be sparse */
739 if (!meson8b_hw_onecell_data.hws[clkid])
742 /* FIXME convert to devm_clk_register */
743 ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[clkid]);
749 * Register CPU clk notifier
751 * FIXME this is wrong for a lot of reasons. First, the muxes should be
752 * struct clk_hw objects. Second, we shouldn't program the muxes in
753 * notifier handlers. The tricky programming sequence will be handled
754 * by the forthcoming coordinated clock rates mechanism once that
755 * feature is released.
757 * Furthermore, looking up the parent this way is terrible. At some
758 * point we will stop allocating a default struct clk when registering
759 * a new clk_hw, and this hack will no longer work. Releasing the ccr
760 * feature before that time solves the problem :-)
762 parent_hw = clk_hw_get_parent(&meson8b_cpu_clk.hw);
763 parent_clk = parent_hw->clk;
764 ret = clk_notifier_register(parent_clk, &meson8b_cpu_clk.clk_nb);
766 pr_err("%s: failed to register clock notifier for cpu_clk\n",
771 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
772 &meson8b_hw_onecell_data);
779 static const struct of_device_id meson8b_clkc_match_table[] = {
780 { .compatible = "amlogic,meson8b-clkc" },
784 static struct platform_driver meson8b_driver = {
785 .probe = meson8b_clkc_probe,
787 .name = "meson8b-clkc",
788 .of_match_table = meson8b_clkc_match_table,
792 builtin_platform_driver(meson8b_driver);