drivers/clk/mvebu/common.c

   1 /*
   2  * Marvell EBU SoC common clock handling
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   7  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   8  * Andrew Lunn <andrew@lunn.ch>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/clk.h>
  17 #include <linux/clkdev.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/io.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22
  23 #include "common.h"
  24
  25 /*
  26  * Core Clocks
  27  */
  28
  29 static struct clk_onecell_data clk_data;
  30
  31 void __init mvebu_coreclk_setup(struct device_node *np,
  32                                 const struct coreclk_soc_desc *desc)
  33 {
  34         const char *tclk_name = "tclk";
  35         const char *cpuclk_name = "cpuclk";
  36         void __iomem *base;
  37         unsigned long rate;
  38         int n;
  39
  40         base = of_iomap(np, 0);
  41         if (WARN_ON(!base))
  42                 return;
  43
  44         /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
  45         clk_data.clk_num = 2 + desc->num_ratios;
  46         clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
  47                                 GFP_KERNEL);
  48         if (WARN_ON(!clk_data.clks))
  49                 return;
  50
  51         /* Register TCLK */
  52         of_property_read_string_index(np, "clock-output-names", 0,
  53                                       &tclk_name);
  54         rate = desc->get_tclk_freq(base);
  55         clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL,
  56                                                    CLK_IS_ROOT, rate);
  57         WARN_ON(IS_ERR(clk_data.clks[0]));
  58
  59         /* Register CPU clock */
  60         of_property_read_string_index(np, "clock-output-names", 1,
  61                                       &cpuclk_name);
  62         rate = desc->get_cpu_freq(base);
  63         clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
  64                                                    CLK_IS_ROOT, rate);
  65         WARN_ON(IS_ERR(clk_data.clks[1]));
  66
  67         /* Register fixed-factor clocks derived from CPU clock */
  68         for (n = 0; n < desc->num_ratios; n++) {
  69                 const char *rclk_name = desc->ratios[n].name;
  70                 int mult, div;
  71
  72                 of_property_read_string_index(np, "clock-output-names",
  73                                               2+n, &rclk_name);
  74                 desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);
  75                 clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
  76                                        cpuclk_name, 0, mult, div);
  77                 WARN_ON(IS_ERR(clk_data.clks[2+n]));
  78         };
  79
  80         /* SAR register isn't needed anymore */
  81         iounmap(base);
  82
  83         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
  84 }
  85
  86 /*
  87  * Clock Gating Control
  88  */
  89
  90 struct clk_gating_ctrl {
  91         spinlock_t lock;
  92         struct clk **gates;
  93         int num_gates;
  94 };
  95
  96 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
  97
  98 static struct clk *clk_gating_get_src(
  99         struct of_phandle_args *clkspec, void *data)
 100 {
 101         struct clk_gating_ctrl *ctrl = (struct clk_gating_ctrl *)data;
 102         int n;
 103
 104         if (clkspec->args_count < 1)
 105                 return ERR_PTR(-EINVAL);
 106
 107         for (n = 0; n < ctrl->num_gates; n++) {
 108                 struct clk_gate *gate =
 109                         to_clk_gate(__clk_get_hw(ctrl->gates[n]));
 110                 if (clkspec->args[0] == gate->bit_idx)
 111                         return ctrl->gates[n];
 112         }
 113         return ERR_PTR(-ENODEV);
 114 }
 115
 116 void __init mvebu_clk_gating_setup(struct device_node *np,
 117                                    const struct clk_gating_soc_desc *desc)
 118 {
 119         struct clk_gating_ctrl *ctrl;
 120         struct clk *clk;
 121         void __iomem *base;
 122         const char *default_parent = NULL;
 123         int n;
 124
 125         base = of_iomap(np, 0);
 126         if (WARN_ON(!base))
 127                 return;
 128
 129         clk = of_clk_get(np, 0);
 130         if (!IS_ERR(clk)) {
 131                 default_parent = __clk_get_name(clk);
 132                 clk_put(clk);
 133         }
 134
 135         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
 136         if (WARN_ON(!ctrl))
 137                 return;
 138
 139         spin_lock_init(&ctrl->lock);
 140
 141         /* Count, allocate, and register clock gates */
 142         for (n = 0; desc[n].name;)
 143                 n++;
 144
 145         ctrl->num_gates = n;
 146         ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *),
 147                               GFP_KERNEL);
 148         if (WARN_ON(!ctrl->gates)) {
 149                 kfree(ctrl);
 150                 return;
 151         }
 152
 153         for (n = 0; n < ctrl->num_gates; n++) {
 154                 const char *parent =
 155                         (desc[n].parent) ? desc[n].parent : default_parent;
 156                 ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent,
 157                                         desc[n].flags, base, desc[n].bit_idx,
 158                                         0, &ctrl->lock);
 159                 WARN_ON(IS_ERR(ctrl->gates[n]));
 160         }
 161
 162         of_clk_add_provider(np, clk_gating_get_src, ctrl);
 163 }